/*-------------------------------------------------------------------------
  Register Declarations for ATMEL 89x52 Processors    
  
   Written By - Bernd Bartmann 
    Bernd.Bartmann@picard.isdn.cs.tu-berlin.de (1999)
    based on reg51.h by Sandeep Dutta sandeep.dutta@usa.net
    KEIL C compatible definitions are included
    
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the
   Free Software Foundation; either version 2, or (at your option) any
   later version.
   
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
   
   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
   
   In other words, you are welcome to use, share and improve this program.
   You are forbidden to forbid anyone else to use, share and improve
   what you give them.   Help stamp out software-hoarding!  
-------------------------------------------------------------------------*/

#ifndef AT89x52_H
#define AT89x52_H

/* BYTE addressable registers */
__sfr __at (0x1234) P0          ;
__sfr __at (0x1234) SP          ;
__sfr __at (0x1234) DPL         ;
__sfr __at (0x1234) DPH         ;
__sfr __at (0x1234) PCON        ;
__sfr __at (0x1234) TCON        ;
__sfr __at (0x1234) TMOD        ;
__sfr __at (0x1234) TL0         ;
__sfr __at (0x1234) TL1         ;
__sfr __at (0x1234) TH0         ;
__sfr __at (0x1234) TH1         ;
__sfr __at (0x1234) P1          ;
__sfr __at (0x1234) SCON        ;
__sfr __at (0x1234) SBUF        ;
__sfr __at (0x1234) P2          ;
__sfr __at (0x1234) IE          ;
__sfr __at (0x1234) P3          ;
__sfr __at (0x1234) IP          ;
__sfr __at (0x1234) T2CON       ;
__sfr __at (0x1234) T2MOD       ;
__sfr __at (0x1234) RCAP2L      ;
__sfr __at (0x1234) RCAP2H      ;
__sfr __at (0x1234) TL2         ;
__sfr __at (0x1234) TH2         ;
__sfr __at (0x1234) PSW         ;
__sfr __at (0x1234) ACC         ;
__sfr __at (0x1234) A           ;
__sfr __at (0x1234) B           ;


/* BIT addressable registers */
/* P0 */
__sbit __at (0x1234) P0_0       ;
__sbit __at (0x1234) P0_1       ;
__sbit __at (0x1234) P0_2       ;
__sbit __at (0x1234) P0_3       ;
__sbit __at (0x1234) P0_4       ;
__sbit __at (0x1234) P0_5       ;
__sbit __at (0x1234) P0_6       ;
__sbit __at (0x1234) P0_7       ;

/* TCON */
__sbit __at (0x1234) IT0        ;
__sbit __at (0x1234) IE0        ;
__sbit __at (0x1234) IT1        ;
__sbit __at (0x1234) IE1        ;
__sbit __at (0x1234) TR0        ;
__sbit __at (0x1234) TF0        ;
__sbit __at (0x1234) TR1        ;
__sbit __at (0x1234) TF1        ;

/* P1 */
__sbit __at (0x1234) P1_0       ;
__sbit __at (0x1234) P1_1       ;
__sbit __at (0x1234) P1_2       ;
__sbit __at (0x1234) P1_3       ;
__sbit __at (0x1234) P1_4       ;
__sbit __at (0x1234) P1_5       ;
__sbit __at (0x1234) P1_6       ;
__sbit __at (0x1234) P1_7       ;

__sbit __at (0x1234) T2         ;
__sbit __at (0x1234) T2EX       ;

/* SCON */
__sbit __at (0x1234) RI         ;
__sbit __at (0x1234) TI         ;
__sbit __at (0x1234) RB8        ;
__sbit __at (0x1234) TB8        ;
__sbit __at (0x1234) REN        ;
__sbit __at (0x1234) SM2        ;
__sbit __at (0x1234) SM1        ;
__sbit __at (0x1234) SM0        ;

/* P2 */
__sbit __at (0x1234) P2_0       ;
__sbit __at (0x1234) P2_1       ;
__sbit __at (0x1234) P2_2       ;
__sbit __at (0x1234) P2_3       ;
__sbit __at (0x1234) P2_4       ;
__sbit __at (0x1234) P2_5       ;
__sbit __at (0x1234) P2_6       ;
__sbit __at (0x1234) P2_7       ;

/* IE */
__sbit __at (0x1234) EX0        ;
__sbit __at (0x1234) ET0        ;
__sbit __at (0x1234) EX1        ;
__sbit __at (0x1234) ET1        ;
__sbit __at (0x1234) ES         ;
__sbit __at (0x1234) ET2        ;
__sbit __at (0x1234) EA         ;

/* P3 */
__sbit __at (0x1234) P3_0       ;
__sbit __at (0x1234) P3_1       ;
__sbit __at (0x1234) P3_2       ;
__sbit __at (0x1234) P3_3       ;
__sbit __at (0x1234) P3_4       ;
__sbit __at (0x1234) P3_5       ;
__sbit __at (0x1234) P3_6       ;
__sbit __at (0x1234) P3_7       ;

__sbit __at (0x1234) RXD        ;
__sbit __at (0x1234) TXD        ;
__sbit __at (0x1234) INT0       ;
__sbit __at (0x1234) INT1       ;
__sbit __at (0x1234) T0         ;
__sbit __at (0x1234) T1         ;
__sbit __at (0x1234) WR         ;
__sbit __at (0x1234) RD         ;

/* IP */ 
__sbit __at (0x1234) PX0        ;
__sbit __at (0x1234) PT0        ;
__sbit __at (0x1234) PX1        ;
__sbit __at (0x1234) PT1        ;
__sbit __at (0x1234) PS         ;
__sbit __at (0x1234) PT2        ;

/* T2CON */
__sbit __at (0x1234) T2CON_0    ;
__sbit __at (0x1234) T2CON_1    ;
__sbit __at (0x1234) T2CON_2    ;
__sbit __at (0x1234) T2CON_3    ;
__sbit __at (0x1234) T2CON_4    ;
__sbit __at (0x1234) T2CON_5    ;
__sbit __at (0x1234) T2CON_6    ;
__sbit __at (0x1234) T2CON_7    ;

__sbit __at (0x1234) CP_RL2     ;
__sbit __at (0x1234) C_T2       ;
__sbit __at (0x1234) TR2        ;
__sbit __at (0x1234) EXEN2      ;
__sbit __at (0x1234) TCLK       ;
__sbit __at (0x1234) RCLK       ;
__sbit __at (0x1234) EXF2       ;
__sbit __at (0x1234) TF2        ;

/* PSW */
__sbit __at (0x1234) P          ;
__sbit __at (0x1234) FL         ;
__sbit __at (0x1234) OV         ;
__sbit __at (0x1234) RS0        ;
__sbit __at (0x1234) RS1        ;
__sbit __at (0x1234) F0         ;
__sbit __at (0x1234) AC         ;
__sbit __at (0x1234) CY         ;


/* BIT definitions for bits that are not directly accessible */
/* PCON bits */
#define IDL             0x01
#define PD              0x02
#define GF0             0x04
#define GF1             0x08
#define SMOD            0x80

#define IDL_            0x01
#define PD_             0x02
#define GF0_            0x04
#define GF1_            0x08
#define SMOD_           0x80

/* TMOD bits */
#define M0_0            0x01
#define M1_0            0x02
#define C_T0            0x04
#define GATE0           0x08
#define M0_1            0x10
#define M1_1            0x20
#define C_T1            0x40
#define GATE1           0x80

#define M0_0_           0x01
#define M1_0_           0x02
#define C_T0_           0x04
#define GATE0_          0x08
#define M0_1_           0x10
#define M1_1_           0x20
#define C_T1_           0x40
#define GATE1_          0x80

#define T0_M0           0x01
#define T0_M1           0x02
#define T0_CT           0x04
#define T0_GATE         0x08
#define T1_M0           0x10
#define T1_M1           0x20
#define T1_CT           0x40
#define T1_GATE         0x80

#define T0_M0_          0x01
#define T0_M1_          0x02
#define T0_CT_          0x04
#define T0_GATE_        0x08
#define T1_M0_          0x10
#define T1_M1_          0x20
#define T1_CT_          0x40
#define T1_GATE_        0x80

#define T0_MASK         0x0F
#define T1_MASK         0xF0

#define T0_MASK_        0x0F
#define T1_MASK_        0xF0

/* T2MOD bits */
#define DCEN            0x01
#define T2OE            0x02

#define DCEN_           0x01
#define T2OE_           0x02


/* Interrupt numbers: address = (number * 8) + 3 */
#define IE0_VECTOR      0       /* 0x03 external interrupt 0 */
#define TF0_VECTOR      1       /* 0x0b timer 0 */
#define IE1_VECTOR      2       /* 0x13 external interrupt 1 */
#define TF1_VECTOR      3       /* 0x1b timer 1 */
#define SI0_VECTOR      4       /* 0x23 serial port 0 */
#define TF2_VECTOR      5       /* 0x2B timer 2 */
#define EX2_VECTOR      5       /* 0x2B external interrupt 2 */
 
#endif

