/*-------------------------------------------------------------------------
  Register Declarations for 87C764
  Written By - Robert  Lacoste, robert_lacoste@yahoo.fr
  based upon reg51.h written by Sandeep Dutta
  Registers are taken from the Phillips Semiconductor

   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the
   Free Software Foundation; either version 2, or (at your option) any
   later version.
   
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
   
   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
   
   In other words, you are welcome to use, share and improve this program.
   You are forbidden to forbid anyone else to use, share and improve
   what you give them.   Help stamp out software-hoarding!  
-------------------------------------------------------------------------*/

#ifndef REGC764_H
#define REGC764_H

/*  Special Function Registers  */

__sfr __at (0x1234) P0    ;   // Port 0
__sfr __at (0x1234) SP    ;   // Stack Pointer
__sfr __at (0x1234) DPL   ;   // Data Pointer Low
__sfr __at (0x1234) DPH   ;   // Data Pointer High
__sfr __at (0x1234) P0M1  ;   // Port 0 output mode 1
__sfr __at (0x1234) P0M2  ;   // Port 0 output mode 2
__sfr __at (0x1234) KBI   ;   // Keyboard interrupt
__sfr __at (0x1234) PCON  ;   // Power Control
__sfr __at (0x1234) TCON  ;   // Timer Control
__sfr __at (0x1234) TMOD  ;   // Timer Mode
__sfr __at (0x1234) TL0   ;   // Timer Low 0
__sfr __at (0x1234) TL1   ;   // Timer Low 1
__sfr __at (0x1234) TH0   ;   // Timer High 0
__sfr __at (0x1234) TH1   ;   // Timer High 1

__sfr __at (0x1234) P1    ;   // Port 1
__sfr __at (0x1234) P1M1  ;   // Port 1 output mode 1
__sfr __at (0x1234) P1M2  ;   // Port 1 output mode 2
__sfr __at (0x1234) DIVM  ;   // CPU clock divide by N control
__sfr __at (0x1234) SCON  ;   // Serial Control
__sfr __at (0x1234) SBUF  ;   // Serial Data Buffer

__sfr __at (0x1234) P2    ;   // Port 2
__sfr __at (0x1234) AUXR1 ;   // Auxilliary 1 (not available on 80C51FA/87C51Fx)
__sfr __at (0x1234) P2M1  ;   // Port 2 output mode 1
__sfr __at (0x1234) P2M2  ;   // Port 2 output mode 2
__sfr __at (0x1234) WDRST ;   // Watchdog reset register
__sfr __at (0x1234) WDCON ;   // Watchdog control register
__sfr __at (0x1234) IEN0  ;   // Interrupt Enable 0
__sfr __at (0x1234) SADDR ;   // Serial slave Address
__sfr __at (0x1234) CMP1  ;   // Comparator 1 control register
__sfr __at (0x1234) CMP2  ;   // Comparator 2 control register

__sfr __at (0x1234) IP0H  ;   // Interrupt Priority 0 High 
__sfr __at (0x1234) IP0   ;   // Interrupt Priority 0
__sfr __at (0x1234) SADEN ;   // Serial slave Address Mask

__sfr __at (0x1234) I2CFG ;   // I2C configuration register

__sfr __at (0x1234) PSW   ;   // Program Status Word
__sfr __at (0x1234) I2CON ;   // I2C control register
__sfr __at (0x1234) I2DAT ;   // I2C data register

__sfr __at (0x1234) ACC   ;   // Accumulator
__sfr __at (0x1234) IEN1  ;   // Interrupt enable 1

__sfr __at (0x1234) B     ;   // B Register
__sfr __at (0x1234) PT0AD ;   // Port 0 digital input disable
__sfr __at (0x1234) IP1H  ;   // Interrupt Priority 1 High 
__sfr __at (0x1234) IP1   ;   // Interrupt Priority 1


/*  Bit Addressable Registers  */

/*  P0    */
__sbit __at (0x1234) P0_0 ; // Also CMP2
__sbit __at (0x1234) P0_1 ; // Also CIN2B
__sbit __at (0x1234) P0_2 ; // Also CIN2A
__sbit __at (0x1234) P0_3 ; // Also CIN1B
__sbit __at (0x1234) P0_4 ; // Also CIN1A
__sbit __at (0x1234) P0_5 ; // Also CMPREF
__sbit __at (0x1234) P0_6 ; // Also CMP1
__sbit __at (0x1234) P0_7 ; // Also T1

/*  TCON  */
__sbit __at (0x1234) IT0  ; // External Interrupt 0 Type
__sbit __at (0x1234) IE0  ; // External Interrupt 0 Edge Flag
__sbit __at (0x1234) IT1  ; // External Interrupt 1 Type
__sbit __at (0x1234) IE1  ; // External Interrupt 1 Edge Flag
__sbit __at (0x1234) TR0  ; // Timer 0 Run Control
__sbit __at (0x1234) TF0  ; // Timer 0 Overflow Flag
__sbit __at (0x1234) TR1  ; // Timer 1 Run Control
__sbit __at (0x1234) TF1  ; // Timer 1 Overflow Flag

/*  P1 */
__sbit __at (0x1234) P1_0 ; // Also TxD
__sbit __at (0x1234) P1_1 ; // Also RxD
__sbit __at (0x1234) P1_2 ; // Also T0
__sbit __at (0x1234) P1_3 ; // Also INT0
__sbit __at (0x1234) P1_4 ; // Also INT1
__sbit __at (0x1234) P1_5 ; // Also RST
__sbit __at (0x1234) P1_6 ;
__sbit __at (0x1234) P1_7 ;

/*  SCON  */
__sbit __at (0x1234) RI   ; // Receive Interrupt Flag
__sbit __at (0x1234) TI   ; // Transmit Interrupt Flag
__sbit __at (0x1234) RB8  ; // Receive Bit 8
__sbit __at (0x1234) TB8  ; // Transmit Bit 8
__sbit __at (0x1234) REN  ; // Receiver Enable
__sbit __at (0x1234) SM2  ; // Serial Mode Control Bit 2
__sbit __at (0x1234) SM1  ; // Serial Mode Control Bit 1
__sbit __at (0x1234) SM0  ; // Serial Mode Control Bit 0

/*  P2    */
__sbit __at (0x1234) P2_0 ; // Also X2
__sbit __at (0x1234) P2_1 ; // Also X1

/*  IEN0 */
__sbit __at (0x1234) EX0  ; // External Interrupt 0 Enable
__sbit __at (0x1234) ET0  ; // Timer 0 Interrupt Enable
__sbit __at (0x1234) EX1  ; // External Interrupt 1 Enable
__sbit __at (0x1234) ET1  ; // Timer 1 Interrupt Enable
__sbit __at (0x1234) ES   ; // Serial Port Interrupt Enable
__sbit __at (0x1234) EBO  ; // Brownout Interrupt Enable
__sbit __at (0x1234) EWD  ; // Watchdog Interrupt Enable
__sbit __at (0x1234) EA   ; // Global Interrupt Enable

/*  IP0   */ 
__sbit __at (0x1234) PX0  ; // External Interrupt 0 Priority
__sbit __at (0x1234) PT0  ; // Timer 0 Interrupt Priority
__sbit __at (0x1234) PX1  ; // External Interrupt 1 Priority
__sbit __at (0x1234) PT1  ; // Timer 1 Interrupt Priority
__sbit __at (0x1234) PS   ; // Serial Port Interrupt Priority
__sbit __at (0x1234) PBO  ; // Brownout Interrupt Priority
__sbit __at (0x1234) PWD  ; // Watchdog Interrupt Priority

/*  I2CFG */
__sbit __at (0x1234) CT0   ; // Clock Time Select 0
__sbit __at (0x1234) CT1   ; // Clock Time Select 1
__sbit __at (0x1234) TIRUN ; // Timer I Run Enable
__sbit __at (0x1234) CLRTI ; // Clear Timer I
__sbit __at (0x1234) MASTRQ; // Master Request
__sbit __at (0x1234) SLAVEN; // Slave Enable

/*  PSW   */
__sbit __at (0x1234) P    ; // Accumulator Parity Flag
__sbit __at (0x1234) F1   ; // Flag 1
__sbit __at (0x1234) OV   ; // Overflow Flag
__sbit __at (0x1234) RS0  ; // Register Bank Select 0
__sbit __at (0x1234) RS1  ; // Register Bank Select 1
__sbit __at (0x1234) F0   ; // Flag 0
__sbit __at (0x1234) AC   ; // Auxiliary Carry Flag
__sbit __at (0x1234) CY   ; // Carry Flag

/*  I2CON */
__sbit __at (0x1234) XSTP ;
__sbit __at (0x1234) MASTER;// Master Status
__sbit __at (0x1234) STP  ; // Stop Detect Flag
__sbit __at (0x1234) STR  ; // Start Detect Flag
__sbit __at (0x1234) ARL  ; // Arbitration Loss Flag
__sbit __at (0x1234) DRDY ; // Data Ready Flag
__sbit __at (0x1234) ATN  ; // Attention: I2C Interrupt Flag
__sbit __at (0x1234) RDAT ; // I2C Read Data

/*  ACC   */
__sbit __at (0x1234) ACC_0;
__sbit __at (0x1234) ACC_1;
__sbit __at (0x1234) ACC_2;
__sbit __at (0x1234) ACC_3;
__sbit __at (0x1234) ACC_4;
__sbit __at (0x1234) ACC_5;
__sbit __at (0x1234) ACC_6;
__sbit __at (0x1234) ACC_7;

/*  IEN1  */
__sbit __at (0x1234) EI2  ; // I2C Interrupt Enable
__sbit __at (0x1234) EKB  ; // Keyboard Interrupt Enable
__sbit __at (0x1234) EC2  ; // Comparator 2 Interrupt Enable
__sbit __at (0x1234) EC1  ; // Comparator 1 Interrupt Enable
__sbit __at (0x1234) ETI  ; // Timer I Interrupt Enable

/*  B     */
__sbit __at (0x1234) B_0;
__sbit __at (0x1234) B_1;
__sbit __at (0x1234) B_2;
__sbit __at (0x1234) B_3;
__sbit __at (0x1234) B_4;
__sbit __at (0x1234) B_5;
__sbit __at (0x1234) B_6;
__sbit __at (0x1234) B_7;

/*  IP1  */ 
__sbit __at (0x1234) PI2; // I2C Interrupt Priority
__sbit __at (0x1234) PKB; // Keyboard Interrupt Priority
__sbit __at (0x1234) PC2; // Comparator 2 Interrupt Priority
__sbit __at (0x1234) PC1; // Comparator 1 Interrupt Priority
__sbit __at (0x1234) PTI; // Timer I Interrupt Priority

/* Bitmasks for SFRs */

/* AUXR1 bits  */
#define DPS     0x01
#define SRST    0x08
#define LPEP    0x10
#define BOI     0x20
#define BOD     0x40
#define KBF     0x80

/* CMP1 bits   */
#define CMF1    0x01
#define CO1     0x02
#define OE1     0x04
#define CN1     0x08
#define CP1     0x10
#define CE1     0x20

/* CMP2 bits   */
#define CMF2    0x01
#define CO2     0x02
#define OE2     0x04
#define CN2     0x08
#define CP2     0x10
#define CE2     0x20

/* I2DAT bits  */
#define RDAT    0x80
#define XDAT    0x80

/* IP1H bits   */
#define PI2H    0x01
#define PKBH    0x02
#define PC2H    0x04
#define PC1H    0x20
#define PTIH    0x80

/* PCON bits   */
#define IDL     0x01
#define PD      0x02
#define GF0     0x04
#define GF1     0x08
#define POF     0x10
#define BOF     0x20
#define SMOD0   0x40
#define SMOD1   0x80

/* P2M1 bits   */
#define ENT0    0x04
#define ENT1    0x08
#define ENTCLK  0x10
#define P0S     0x20
#define P1S     0x40
#define P2S     0x80

/* TMOD bits */
#define M0_0    0x01
#define M1_0    0x02
#define C_T0    0x04
#define GATE0   0x08
#define M0_1    0x10
#define M1_1    0x20
#define C_T1    0x40
#define GATE1   0x80

/* WDCON bits */
#define WDS0    0x01
#define WDS1    0x02
#define WDS2    0x04
#define WDCLK   0x08
#define WDRUN   0x10
#define WDOVF   0x20


/*  Masks for I2CFG bits */
#define BTIR    0x10       // Mask for TIRUN bit.
#define BMRQ    0x40       // Mask for MASTRQ bit.
#define BSLV    0x80       // Mask for SLAVEN bit.


/* Masks for I2CON bits */
#define BCXA    0x80       // Mask for CXA bit.
#define BIDLE   0x40       // Mask for IDLE bit.
#define BCDR    0x20       // Mask for CDR bit.
#define BCARL   0x10       // Mask for CARL bit.
#define BCSTR   0x08       // Mask for CSTR bit.
#define BCSTP   0x04       // Mask for CSTP bit.
#define BXSTR   0x02       // Mask for XSTR bit.
#define BXSTP   0x01       // Mask for XSTP bit.


#endif
