/*-------------------------------------------------------------------------
   Register Declarations for the Cygnal/SiLabs C8051F04x Processor Range

   Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl

   This library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Lesser General Public
   License as published by the Free Software Foundation; either
   version 2.1 of the License, or (at your option) any later version.

   This library is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   Lesser General Public License for more details.

   You should have received a copy of the GNU Lesser General Public
   License along with this library; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
-------------------------------------------------------------------------*/

#ifndef C8051F040_H
#define C8051F040_H


/*  BYTE Registers  */

/*  All Pages */
__sfr __at (0x1234) P0       ;  /* PORT 0                                        */
__sfr __at (0x1234) SP       ;  /* STACK POINTER                                 */
__sfr __at (0x1234) DPL      ;  /* DATA POINTER - LOW BYTE                       */
__sfr __at (0x1234) DPH      ;  /* DATA POINTER - HIGH BYTE                      */
__sfr __at (0x1234) SFRPAGE  ;  /* SFR PAGE SELECT                               */
__sfr __at (0x1234) SFRNEXT  ;  /* SFR STACK NEXT PAGE                           */
__sfr __at (0x1234) SFRLAST  ;  /* SFR STACK LAST PAGE                           */
__sfr __at (0x1234) PCON     ;  /* POWER CONTROL                                 */
__sfr __at (0x1234) P1       ;  /* PORT 1                                        */
__sfr __at (0x1234) P2       ;  /* PORT 2                                        */
__sfr __at (0x1234) IE       ;  /* INTERRUPT ENABLE                              */
__sfr __at (0x1234) P3       ;  /* PORT 3                                        */
__sfr __at (0x1234) IP       ;  /* INTERRUPT PRIORITY                            */
__sfr __at (0x1234) PSW      ;  /* PROGRAM STATUS WORD                           */
__sfr __at (0x1234) ACC      ;  /* ACCUMULATOR                                   */
__sfr __at (0x1234) EIE1     ;  /* EXTERNAL INTERRUPT ENABLE 1                   */
__sfr __at (0x1234) EIE2     ;  /* EXTERNAL INTERRUPT ENABLE 2                   */
__sfr __at (0x1234) B        ;  /* B REGISTER                                    */
__sfr __at (0x1234) EIP1     ;  /* EXTERNAL INTERRUPT PRIORITY REGISTER 1        */
__sfr __at (0x1234) EIP2     ;  /* EXTERNAL INTERRUPT PRIORITY REGISTER 2        */
__sfr __at (0x1234) WDTCN    ;  /* WATCHDOG TIMER CONTROL                        */

/*  Page 0x00 */
__sfr __at (0x1234) TCON     ;  /* TIMER CONTROL                                 */
__sfr __at (0x1234) TMOD     ;  /* TIMER MODE                                    */
__sfr __at (0x1234) TL0      ;  /* TIMER 0 - LOW BYTE                            */
__sfr __at (0x1234) TL1      ;  /* TIMER 1 - LOW BYTE                            */
__sfr __at (0x1234) TH0      ;  /* TIMER 0 - HIGH BYTE                           */
__sfr __at (0x1234) TH1      ;  /* TIMER 1 - HIGH BYTE                           */
__sfr __at (0x1234) CKCON    ;  /* TIMER 0/1 CLOCK CONTROL                       */
__sfr __at (0x1234) PSCTL    ;  /* FLASH WRITE/ERASE CONTROL                     */
__sfr __at (0x1234) SSTA0    ;  /* UART 0 STATUS                                 */
__sfr __at (0x1234) SCON0    ;  /* UART 0 CONTROL                                */
__sfr __at (0x1234) SCON     ;  /* UART 0 CONTROL                                */
__sfr __at (0x1234) SBUF0    ;  /* UART 0 BUFFER                                 */
__sfr __at (0x1234) SBUF     ;  /* UART 0 BUFFER                                 */
__sfr __at (0x1234) SPI0CFG  ;  /* SPI 0 CONFIGURATION                           */
__sfr __at (0x1234) SPI0DAT  ;  /* SPI 0 DATA                                    */
__sfr __at (0x1234) SPI0CKR  ;  /* SPI 0 CLOCK RATE CONTROL                      */
__sfr __at (0x1234) EMI0TC   ;  /* EMIF TIMING CONTROL                           */
__sfr __at (0x1234) EMI0CN   ;  /* EMIF CONTROL                                  */
__sfr __at (0x1234) _XPAGE   ;  /* XDATA/PDATA PAGE                              */
__sfr __at (0x1234) EMI0CF   ;  /* EMIF CONFIGURATION                            */
__sfr __at (0x1234) SADDR0   ;  /* UART 0 SLAVE ADDRESS                          */
__sfr __at (0x1234) FLSCL    ;  /* FLASH SCALE                                   */
__sfr __at (0x1234) SADEN0   ;  /* UART 0 SLAVE ADDRESS MASK                     */
__sfr __at (0x1234) AMX0CF   ;  /* ADC 0 MUX CONFIGURATION                       */
__sfr __at (0x1234) AMX0SL   ;  /* ADC 0 MUX CHANNEL SELECTION                   */
__sfr __at (0x1234) ADC0CF   ;  /* ADC 0 CONFIGURATION                           */
__sfr __at (0x1234) AMX0PRT  ;  /* ADC 0 PORT 3 I/O PIN SELECT                   */
__sfr __at (0x1234) ADC0L    ;  /* ADC 0 DATA - LOW BYTE                         */
__sfr __at (0x1234) ADC0H    ;  /* ADC 0 DATA - HIGH BYTE                        */
__sfr __at (0x1234) SMB0CN   ;  /* SMBUS 0 CONTROL                               */
__sfr __at (0x1234) SMB0STA  ;  /* SMBUS 0 STATUS                                */
__sfr __at (0x1234) SMB0DAT  ;  /* SMBUS 0 DATA                                  */
__sfr __at (0x1234) SMB0ADR  ;  /* SMBUS 0 SLAVE ADDRESS                         */
__sfr __at (0x1234) ADC0GTL  ;  /* ADC 0 GREATER-THAN REGISTER - LOW BYTE        */
__sfr __at (0x1234) ADC0GTH  ;  /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE       */
__sfr __at (0x1234) ADC0LTL  ;  /* ADC 0 LESS-THAN REGISTER - LOW BYTE           */
__sfr __at (0x1234) ADC0LTH  ;  /* ADC 0 LESS-THAN REGISTER - HIGH BYTE          */
__sfr __at (0x1234) TMR2CN   ;  /* TIMER 2 CONTROL                               */
__sfr __at (0x1234) TMR2CF   ;  /* TIMER 2 CONFIGURATION                         */
__sfr __at (0x1234) RCAP2L   ;  /* TIMER 2 CAPTURE REGISTER - LOW BYTE           */
__sfr __at (0x1234) RCAP2H   ;  /* TIMER 2 CAPTURE REGISTER - HIGH BYTE          */
__sfr __at (0x1234) TMR2L    ;  /* TIMER 2 - LOW BYTE                            */
__sfr __at (0x1234) TL2      ;  /* TIMER 2 - LOW BYTE                            */
__sfr __at (0x1234) TMR2H    ;  /* TIMER 2 - HIGH BYTE                           */
__sfr __at (0x1234) TH2      ;  /* TIMER 2 - HIGH BYTE                           */
__sfr __at (0x1234) SMB0CR   ;  /* SMBUS 0 CLOCK RATE                            */
__sfr __at (0x1234) REF0CN   ;  /* VOLTAGE REFERENCE 0 CONTROL                   */
__sfr __at (0x1234) DAC0L    ;  /* DAC 0 REGISTER - LOW BYTE                     */
__sfr __at (0x1234) DAC0H    ;  /* DAC 0 REGISTER - HIGH BYTE                    */
__sfr __at (0x1234) DAC0CN   ;  /* DAC 0 CONTROL                                 */
__sfr __at (0x1234) HVA0CN   ;  /* HIGH VOLTAGE DIFFERENTIAL AMP CONTROL         */
__sfr __at (0x1234) PCA0CN   ;  /* PCA 0 COUNTER CONTROL                         */
__sfr __at (0x1234) PCA0MD   ;  /* PCA 0 COUNTER MODE                            */
__sfr __at (0x1234) PCA0CPM0 ;  /* PCA 0 MODULE 0 CONTROL                        */
__sfr __at (0x1234) PCA0CPM1 ;  /* PCA 0 MODULE 1 CONTROL                        */
__sfr __at (0x1234) PCA0CPM2 ;  /* PCA 0 MODULE 2 CONTROL                        */
__sfr __at (0x1234) PCA0CPM3 ;  /* PCA 0 MODULE 3 CONTROL                        */
__sfr __at (0x1234) PCA0CPM4 ;  /* PCA 0 MODULE 4 CONTROL                        */
__sfr __at (0x1234) PCA0CPM5 ;  /* PCA 0 MODULE 5 CONTROL                        */
__sfr __at (0x1234) PCA0CPL5 ;  /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE     */
__sfr __at (0x1234) PCA0CPH5 ;  /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE    */
__sfr __at (0x1234) ADC0CN   ;  /* ADC 0 CONTROL                                 */
__sfr __at (0x1234) PCA0CPL2 ;  /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE     */
__sfr __at (0x1234) PCA0CPH2 ;  /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE    */
__sfr __at (0x1234) PCA0CPL3 ;  /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE     */
__sfr __at (0x1234) PCA0CPH3 ;  /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE    */
__sfr __at (0x1234) PCA0CPL4 ;  /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE     */
__sfr __at (0x1234) PCA0CPH4 ;  /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE    */
__sfr __at (0x1234) RSTSRC   ;  /* RESET SOURCE                                  */
__sfr __at (0x1234) SPI0CN   ;  /* SPI 0 CONTROL                                 */
__sfr __at (0x1234) PCA0L    ;  /* PCA 0 TIMER - LOW BYTE                        */
__sfr __at (0x1234) PCA0H    ;  /* PCA 0 TIMER - HIGH BYTE                       */
__sfr __at (0x1234) PCA0CPL0 ;  /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE     */
__sfr __at (0x1234) PCA0CPH0 ;  /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE    */
__sfr __at (0x1234) PCA0CPL1 ;  /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE     */
__sfr __at (0x1234) PCA0CPH1 ;  /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE    */

/*  Page 0x01 */
__sfr __at (0x1234) CPT0CN   ;  /* COMPARATOR 0 CONTROL                          */
__sfr __at (0x1234) CPT0MD   ;  /* COMPARATOR 0 CONFIGURATION                    */
__sfr __at (0x1234) SCON1    ;  /* UART 1 CONTROL                                */
__sfr __at (0x1234) SBUF1    ;  /* UART 1 BUFFER                                 */
__sfr __at (0x1234) CAN0STA  ;  /* CAN 0 STATUS                                  */
__sfr __at (0x1234) TMR3CN   ;  /* TIMER 3 CONTROL                               */
__sfr __at (0x1234) TMR3CF   ;  /* TIMER 3 CONFIGURATION                         */
__sfr __at (0x1234) RCAP3L   ;  /* TIMER 3 CAPTURE REGISTER - LOW BYTE           */
__sfr __at (0x1234) RCAP3H   ;  /* TIMER 3 CAPTURE REGISTER - HIGH BYTE          */
__sfr __at (0x1234) TMR3L    ;  /* TIMER 3 - LOW BYTE                            */
__sfr __at (0x1234) TMR3H    ;  /* TIMER 3 - HIGH BYTE                           */
__sfr __at (0x1234) DAC1L    ;  /* DAC 1 REGISTER - LOW BYTE                     */
__sfr __at (0x1234) DAC1H    ;  /* DAC 1 REGISTER - HIGH BYTE                    */
__sfr __at (0x1234) DAC1CN   ;  /* DAC 1 CONTROL                                 */
__sfr __at (0x1234) CAN0DATL ;  /* CAN 0 DATA REGISTER LOW                       */
__sfr __at (0x1234) CAN0DATH ;  /* CAN 0 DATA REGISTER HIGH                      */
__sfr __at (0x1234) CAN0ADR  ;  /* CAN 0 ADDRESS                                 */
__sfr __at (0x1234) CAN0TST  ;  /* CAN 0 TEST REGISTER                           */
__sfr __at (0x1234) CAN0CN   ;  /* CAN 0 CONTROL                                 */

/*  Page 0x02 */
__sfr __at (0x1234) CPT1CN   ;  /* COMPARATOR 1 CONTROL                          */
__sfr __at (0x1234) CPT1MD   ;  /* COMPARATOR 1 CONFIGURATION                    */
__sfr __at (0x1234) AMX2CF   ;  /* ADC 2 MUX CONFIGURATION                       */
__sfr __at (0x1234) AMX2SL   ;  /* ADC 2 MUX CHANNEL SELECTION                   */
__sfr __at (0x1234) ADC2CF   ;  /* ADC 2 CONFIGURATION                           */
__sfr __at (0x1234) ADC2     ;  /* ADC 2 DATA                                    */
__sfr __at (0x1234) ADC2GT   ;  /* ADC 2 GREATER-THAN REGISTER                   */
__sfr __at (0x1234) ADC2LT   ;  /* ADC 2 LESS-THAN REGISTER                      */
__sfr __at (0x1234) TMR4CN   ;  /* TIMER 4 CONTROL                               */
__sfr __at (0x1234) TMR4CF   ;  /* TIMER 4 CONFIGURATION                         */
__sfr __at (0x1234) RCAP4L   ;  /* TIMER 4 CAPTURE REGISTER - LOW BYTE           */
__sfr __at (0x1234) RCAP4H   ;  /* TIMER 4 CAPTURE REGISTER - HIGH BYTE          */
__sfr __at (0x1234) TMR4L    ;  /* TIMER 4 - LOW BYTE                            */
__sfr __at (0x1234) TMR4H    ;  /* TIMER 4 - HIGH BYTE                           */
__sfr __at (0x1234) ADC2CN   ;  /* ADC 2 CONTROL                                 */

/*  Page 0x03 */
__sfr __at (0x1234) CPT2CN   ;  /* COMPARATOR 2 CONTROL                          */
__sfr __at (0x1234) CPT2MD   ;  /* COMPARATOR 2 CONFIGURATION                    */

/*  Page 0x0F */
__sfr __at (0x1234) OSCICN   ;  /* INTERNAL OSCILLATOR CONTROL                   */
__sfr __at (0x1234) OSCICL   ;  /* INTERNAL OSCILLATOR CALIBRATION               */
__sfr __at (0x1234) OSCXCN   ;  /* EXTERNAL OSCILLATOR CONTROL                   */
__sfr __at (0x1234) SFRPGCN  ;  /* SFR PAGE CONTROL                              */
__sfr __at (0x1234) CLKSEL   ;  /* SYSTEM CLOCK SELECT                           */
__sfr __at (0x1234) P4MDOUT  ;  /* PORT 4 OUTPUT MODE                            */
__sfr __at (0x1234) P5MDOUT  ;  /* PORT 5 OUTPUT MODE                            */
__sfr __at (0x1234) P6MDOUT  ;  /* PORT 6 OUTPUT MODE                            */
__sfr __at (0x1234) P7MDOUT  ;  /* PORT 7 OUTPUT MODE                            */
__sfr __at (0x1234) P0MDOUT  ;  /* PORT 0 OUTPUT MODE                            */
__sfr __at (0x1234) P1MDOUT  ;  /* PORT 1 OUTPUT MODE                            */
__sfr __at (0x1234) P2MDOUT  ;  /* PORT 2 OUTPUT MODE CONFIGURATION              */
__sfr __at (0x1234) P3MDOUT  ;  /* PORT 3 OUTPUT MODE CONFIGURATION              */
__sfr __at (0x1234) P1MDIN   ;  /* PORT 1 INPUT MODE                             */
__sfr __at (0x1234) P2MDIN   ;  /* PORT 2 INPUT MODE                             */
__sfr __at (0x1234) P3MDIN   ;  /* PORT 3 INPUT MODE                             */
__sfr __at (0x1234) FLACL    ;  /* FLASH ACCESS LIMIT                            */
__sfr __at (0x1234) P4       ;  /* PORT 4                                        */
__sfr __at (0x1234) P5       ;  /* PORT 5                                        */
__sfr __at (0x1234) XBR0     ;  /* CROSSBAR CONFIGURATION REGISTER 0             */
__sfr __at (0x1234) XBR1     ;  /* CROSSBAR CONFIGURATION REGISTER 1             */
__sfr __at (0x1234) XBR2     ;  /* CROSSBAR CONFIGURATION REGISTER 2             */
__sfr __at (0x1234) XBR3     ;  /* CROSSBAR CONFIGURATION REGISTER 3             */
__sfr __at (0x1234) P6       ;  /* PORT 6                                        */
__sfr __at (0x1234) P7       ;  /* PORT 7                                        */

/*
Do NOT use sfr16 for CAN0DAT !
*/

/*  BIT Registers  */

/*  P0  0x80 */
__sbit __at (0x1234) P0_0    ;
__sbit __at (0x1234) P0_1    ;
__sbit __at (0x1234) P0_2    ;
__sbit __at (0x1234) P0_3    ;
__sbit __at (0x1234) P0_4    ;
__sbit __at (0x1234) P0_5    ;
__sbit __at (0x1234) P0_6    ;
__sbit __at (0x1234) P0_7    ;

/*  TCON  0x88 */
__sbit __at (0x1234) IT0     ;  /* EXT. INTERRUPT 0 TYPE                         */
__sbit __at (0x1234) IE0     ;  /* EXT. INTERRUPT 0 EDGE FLAG                    */
__sbit __at (0x1234) IT1     ;  /* EXT. INTERRUPT 1 TYPE                         */
__sbit __at (0x1234) IE1     ;  /* EXT. INTERRUPT 1 EDGE FLAG                    */
__sbit __at (0x1234) TR0     ;  /* TIMER 0 ON/OFF CONTROL                        */
__sbit __at (0x1234) TF0     ;  /* TIMER 0 OVERFLOW FLAG                         */
__sbit __at (0x1234) TR1     ;  /* TIMER 1 ON/OFF CONTROL                        */
__sbit __at (0x1234) TF1     ;  /* TIMER 1 OVERFLOW FLAG                         */

/*  CPT0CN  0x88 */
__sbit __at (0x1234) CP0HYN0 ;  /* COMPARATOR 0 NEGATIVE HYSTERESIS 0            */
__sbit __at (0x1234) CP0HYN1 ;  /* COMPARATOR 0 NEGATIVE HYSTERESIS 1            */
__sbit __at (0x1234) CP0HYP0 ;  /* COMPARATOR 0 POSITIVE HYSTERESIS 0            */
__sbit __at (0x1234) CP0HYP1 ;  /* COMPARATOR 0 POSITIVE HYSTERESIS 1            */
__sbit __at (0x1234) CP0FIF  ;  /* COMPARATOR 0 FALLING EDGE INTERRUPT           */
__sbit __at (0x1234) CP0RIF  ;  /* COMPARATOR 0 RISING EDGE INTERRUPT            */
__sbit __at (0x1234) CP0OUT  ;  /* COMPARATOR 0 OUTPUT                           */
__sbit __at (0x1234) CP0EN   ;  /* COMPARATOR 0 ENABLE                           */

/*  CPT1CN  0x88 */
__sbit __at (0x1234) CP1HYN0 ;  /* COMPARATOR 1 NEGATIVE HYSTERESIS 0            */
__sbit __at (0x1234) CP1HYN1 ;  /* COMPARATOR 1 NEGATIVE HYSTERESIS 1            */
__sbit __at (0x1234) CP1HYP0 ;  /* COMPARATOR 1 POSITIVE HYSTERESIS 0            */
__sbit __at (0x1234) CP1HYP1 ;  /* COMPARATOR 1 POSITIVE HYSTERESIS 1            */
__sbit __at (0x1234) CP1FIF  ;  /* COMPARATOR 1 FALLING EDGE INTERRUPT           */
__sbit __at (0x1234) CP1RIF  ;  /* COMPARATOR 1 RISING EDGE INTERRUPT            */
__sbit __at (0x1234) CP1OUT  ;  /* COMPARATOR 1 OUTPUT                           */
__sbit __at (0x1234) CP1EN   ;  /* COMPARATOR 1 ENABLE                           */

/*  CPT2CN  0x88 */
__sbit __at (0x1234) CP2HYN0 ;  /* COMPARATOR 2 NEGATIVE HYSTERESIS 0            */
__sbit __at (0x1234) CP2HYN1 ;  /* COMPARATOR 2 NEGATIVE HYSTERESIS 1            */
__sbit __at (0x1234) CP2HYP0 ;  /* COMPARATOR 2 POSITIVE HYSTERESIS 0            */
__sbit __at (0x1234) CP2HYP1 ;  /* COMPARATOR 2 POSITIVE HYSTERESIS 1            */
__sbit __at (0x1234) CP2FIF  ;  /* COMPARATOR 2 FALLING EDGE INTERRUPT           */
__sbit __at (0x1234) CP2RIF  ;  /* COMPARATOR 2 RISING EDGE INTERRUPT            */
__sbit __at (0x1234) CP2OUT  ;  /* COMPARATOR 2 OUTPUT                           */
__sbit __at (0x1234) CP2EN   ;  /* COMPARATOR 2 ENABLE                           */

/*  P1  0x90 */
__sbit __at (0x1234) P1_0    ;
__sbit __at (0x1234) P1_1    ;
__sbit __at (0x1234) P1_2    ;
__sbit __at (0x1234) P1_3    ;
__sbit __at (0x1234) P1_4    ;
__sbit __at (0x1234) P1_5    ;
__sbit __at (0x1234) P1_6    ;
__sbit __at (0x1234) P1_7    ;

/*  SCON0  0x98 */
__sbit __at (0x1234) RI0     ;  /* UART 0 RX INTERRUPT FLAG                      */
__sbit __at (0x1234) RI      ;  /* UART 0 RX INTERRUPT FLAG                      */
__sbit __at (0x1234) TI0     ;  /* UART 0 TX INTERRUPT FLAG                      */
__sbit __at (0x1234) TI      ;  /* UART 0 TX INTERRUPT FLAG                      */
__sbit __at (0x1234) RB80    ;  /* UART 0 RX BIT 8                               */
__sbit __at (0x1234) TB80    ;  /* UART 0 TX BIT 8                               */
__sbit __at (0x1234) REN0    ;  /* UART 0 RX ENABLE                              */
__sbit __at (0x1234) REN     ;  /* UART 0 RX ENABLE                              */
__sbit __at (0x1234) SM20    ;  /* UART 0 MULTIPROCESSOR EN                      */
__sbit __at (0x1234) SM10    ;  /* UART 0 MODE 1                                 */
__sbit __at (0x1234) SM00    ;  /* UART 0 MODE 0                                 */

/*  SCON1  0x98 */
__sbit __at (0x1234) RI1     ;  /* UART 1 RX INTERRUPT FLAG                      */
__sbit __at (0x1234) TI1     ;  /* UART 1 TX INTERRUPT FLAG                      */
__sbit __at (0x1234) RB81    ;  /* UART 1 RX BIT 8                               */
__sbit __at (0x1234) TB81    ;  /* UART 1 TX BIT 8                               */
__sbit __at (0x1234) REN1    ;  /* UART 1 RX ENABLE                              */
__sbit __at (0x1234) MCE1    ;  /* UART 1 MCE                                    */
__sbit __at (0x1234) S1MODE  ;  /* UART 1 MODE                                   */

/*  P2  0xA0 */
__sbit __at (0x1234) P2_0    ;
__sbit __at (0x1234) P2_1    ;
__sbit __at (0x1234) P2_2    ;
__sbit __at (0x1234) P2_3    ;
__sbit __at (0x1234) P2_4    ;
__sbit __at (0x1234) P2_5    ;
__sbit __at (0x1234) P2_6    ;
__sbit __at (0x1234) P2_7    ;

/*  IE  0xA8 */
__sbit __at (0x1234) EX0     ;  /* EXTERNAL INTERRUPT 0 ENABLE                   */
__sbit __at (0x1234) ET0     ;  /* TIMER 0 INTERRUPT ENABLE                      */
__sbit __at (0x1234) EX1     ;  /* EXTERNAL INTERRUPT 1 ENABLE                   */
__sbit __at (0x1234) ET1     ;  /* TIMER 1 INTERRUPT ENABLE                      */
__sbit __at (0x1234) ES0     ;  /* UART0 INTERRUPT ENABLE                        */
__sbit __at (0x1234) ES      ;  /* UART0 INTERRUPT ENABLE                        */
__sbit __at (0x1234) ET2     ;  /* TIMER 2 INTERRUPT ENABLE                      */
__sbit __at (0x1234) EA      ;  /* GLOBAL INTERRUPT ENABLE                       */

/*  P3  0xB0 */
__sbit __at (0x1234) P3_0    ;
__sbit __at (0x1234) P3_1    ;
__sbit __at (0x1234) P3_2    ;
__sbit __at (0x1234) P3_3    ;
__sbit __at (0x1234) P3_4    ;
__sbit __at (0x1234) P3_5    ;
__sbit __at (0x1234) P3_6    ;
__sbit __at (0x1234) P3_7    ;

/*  IP  0xB8 */
__sbit __at (0x1234) PX0     ;  /* EXTERNAL INTERRUPT 0 PRIORITY                 */
__sbit __at (0x1234) PT0     ;  /* TIMER 0 PRIORITY                              */
__sbit __at (0x1234) PX1     ;  /* EXTERNAL INTERRUPT 1 PRIORITY                 */
__sbit __at (0x1234) PT1     ;  /* TIMER 1 PRIORITY                              */
__sbit __at (0x1234) PS0     ;  /* SERIAL PORT PRIORITY                          */
__sbit __at (0x1234) PS      ;  /* SERIAL PORT PRIORITY                          */
__sbit __at (0x1234) PT2     ;  /* TIMER 2 PRIORITY                              */

/*  SMB0CN  0xC0 */
__sbit __at (0x1234) SMBTOE  ;  /* SMBUS 0 TIMEOUT ENABLE                        */
__sbit __at (0x1234) SMBFTE  ;  /* SMBUS 0 FREE TIMER ENABLE                     */
__sbit __at (0x1234) AA      ;  /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG               */
__sbit __at (0x1234) SI      ;  /* SMBUS 0 INTERRUPT PENDING FLAG                */
__sbit __at (0x1234) STO     ;  /* SMBUS 0 STOP FLAG                             */
__sbit __at (0x1234) STA     ;  /* SMBUS 0 START FLAG                            */
__sbit __at (0x1234) ENSMB   ;  /* SMBUS 0 ENABLE                                */
__sbit __at (0x1234) BUSY    ;  /* SMBUS 0 BUSY                                  */

/*  CAN0STA  0xC0 */
__sbit __at (0x1234) CANTXOK ;  /* CAN TRANSMITTED A MESSAGE SUCCESSFULLY        */
__sbit __at (0x1234) CANRXOK ;  /* CAN RECEIVED A MESSAGE SUCCESSFULLY           */
__sbit __at (0x1234) CANEPASS;  /* CAN ERROR PASSIVE                             */
__sbit __at (0x1234) CANEWARN;  /* CAN WARNING STATUS                            */
__sbit __at (0x1234) CANBOFF ;  /* CAN BUSOFF STATUS                             */

/*  TMR2CN  0xC8 */
__sbit __at (0x1234) CPRL2   ;  /* TIMER 2 CAPTURE SELECT                        */
__sbit __at (0x1234) CT2     ;  /* TIMER 2 COUNTER SELECT                        */
__sbit __at (0x1234) TR2     ;  /* TIMER 2 ON/OFF CONTROL                        */
__sbit __at (0x1234) EXEN2   ;  /* TIMER 2 EXTERNAL ENABLE FLAG                  */
__sbit __at (0x1234) EXF2    ;  /* TIMER 2 EXTERNAL FLAG                         */
__sbit __at (0x1234) TF2     ;  /* TIMER 2 OVERFLOW FLAG                         */

/*  TMR3CN  0xC8 */
__sbit __at (0x1234) CPRL3   ;  /* TIMER 3 CAPTURE SELECT                        */
__sbit __at (0x1234) CT3     ;  /* TIMER 3 COUNTER SELECT                        */
__sbit __at (0x1234) TR3     ;  /* TIMER 3 ON/OFF CONTROL                        */
__sbit __at (0x1234) EXEN3   ;  /* TIMER 3 EXTERNAL ENABLE FLAG                  */
__sbit __at (0x1234) EXF3    ;  /* TIMER 3 EXTERNAL FLAG                         */
__sbit __at (0x1234) TF3     ;  /* TIMER 3 OVERFLOW FLAG                         */

/*  TMR4CN  0xC8 */
__sbit __at (0x1234) CPRL4   ;  /* TIMER 4 CAPTURE SELECT                        */
__sbit __at (0x1234) CT4     ;  /* TIMER 4 COUNTER SELECT                        */
__sbit __at (0x1234) TR4     ;  /* TIMER 4 ON/OFF CONTROL                        */
__sbit __at (0x1234) EXEN4   ;  /* TIMER 4 EXTERNAL ENABLE FLAG                  */
__sbit __at (0x1234) EXF4    ;  /* TIMER 4 EXTERNAL FLAG                         */
__sbit __at (0x1234) TF4     ;  /* TIMER 4 OVERFLOW FLAG                         */

/*  P4  0xC8 */
__sbit __at (0x1234) P4_0    ;
__sbit __at (0x1234) P4_1    ;
__sbit __at (0x1234) P4_2    ;
__sbit __at (0x1234) P4_3    ;
__sbit __at (0x1234) P4_4    ;
__sbit __at (0x1234) P4_5    ;
__sbit __at (0x1234) P4_6    ;
__sbit __at (0x1234) P4_7    ;

/*  PSW  0xD0 */
__sbit __at (0x1234) P       ;  /* ACCUMULATOR PARITY FLAG                       */
__sbit __at (0x1234) F1      ;  /* USER FLAG 1                                   */
__sbit __at (0x1234) OV      ;  /* OVERFLOW FLAG                                 */
__sbit __at (0x1234) RS0     ;  /* REGISTER BANK SELECT 0                        */
__sbit __at (0x1234) RS1     ;  /* REGISTER BANK SELECT 1                        */
__sbit __at (0x1234) F0      ;  /* USER FLAG 0                                   */
__sbit __at (0x1234) AC      ;  /* AUXILIARY CARRY FLAG                          */
__sbit __at (0x1234) CY      ;  /* CARRY FLAG                                    */

/*  PCA0CN  0xD8 */
__sbit __at (0x1234) CCF0    ;  /* PCA 0 MODULE 0 INTERRUPT FLAG                 */
__sbit __at (0x1234) CCF1    ;  /* PCA 0 MODULE 1 INTERRUPT FLAG                 */
__sbit __at (0x1234) CCF2    ;  /* PCA 0 MODULE 2 INTERRUPT FLAG                 */
__sbit __at (0x1234) CCF3    ;  /* PCA 0 MODULE 3 INTERRUPT FLAG                 */
__sbit __at (0x1234) CCF4    ;  /* PCA 0 MODULE 4 INTERRUPT FLAG                 */
__sbit __at (0x1234) CCF5    ;  /* PCA 0 MODULE 5 INTERRUPT FLAG                 */
__sbit __at (0x1234) CR      ;  /* PCA 0 COUNTER RUN CONTROL BIT                 */
__sbit __at (0x1234) CF      ;  /* PCA 0 COUNTER OVERFLOW FLAG                   */

/*  P5  0xD8 */
__sbit __at (0x1234) P5_0    ;
__sbit __at (0x1234) P5_1    ;
__sbit __at (0x1234) P5_2    ;
__sbit __at (0x1234) P5_3    ;
__sbit __at (0x1234) P5_4    ;
__sbit __at (0x1234) P5_5    ;
__sbit __at (0x1234) P5_6    ;
__sbit __at (0x1234) P5_7    ;

/*  ADC0CN  0xE8 */
__sbit __at (0x1234) AD0LJST ;  /* ADC 0 RIGHT JUSTIFY DATA BIT                  */
__sbit __at (0x1234) AD0WINT ;  /* ADC 0 WINDOW INTERRUPT FLAG                   */
__sbit __at (0x1234) AD0CM0  ;  /* ADC 0 CONVERT START MODE BIT 0                */
__sbit __at (0x1234) AD0CM1  ;  /* ADC 0 CONVERT START MODE BIT 1                */
__sbit __at (0x1234) AD0BUSY ;  /* ADC 0 BUSY FLAG                               */
__sbit __at (0x1234) AD0INT  ;  /* ADC 0 EOC INTERRUPT FLAG                      */
__sbit __at (0x1234) AD0TM   ;  /* ADC 0 TRACK MODE                              */
__sbit __at (0x1234) AD0EN   ;  /* ADC 0 ENABLE                                  */

/*  ADC2CN  0xE8 */
__sbit __at (0x1234) AD2WINT ;  /* ADC 2 WINDOW INTERRUPT FLAG                   */
__sbit __at (0x1234) AD2CM0  ;  /* ADC 2 CONVERT START MODE BIT 0                */
__sbit __at (0x1234) AD2CM1  ;  /* ADC 2 CONVERT START MODE BIT 1                */
__sbit __at (0x1234) AD2CM2  ;  /* ADC 2 CONVERT START MODE BIT 2                */
__sbit __at (0x1234) AD2BUSY ;  /* ADC 2 BUSY FLAG                               */
__sbit __at (0x1234) AD2INT  ;  /* ADC 2 EOC INTERRUPT FLAG                      */
__sbit __at (0x1234) AD2TM   ;  /* ADC 2 TRACK MODE                              */
__sbit __at (0x1234) AD2EN   ;  /* ADC 2 ENABLE                                  */

/*  P6  0xE8 */
__sbit __at (0x1234) P6_0    ;
__sbit __at (0x1234) P6_1    ;
__sbit __at (0x1234) P6_2    ;
__sbit __at (0x1234) P6_3    ;
__sbit __at (0x1234) P6_4    ;
__sbit __at (0x1234) P6_5    ;
__sbit __at (0x1234) P6_6    ;
__sbit __at (0x1234) P6_7    ;

/*  SPI0CN  0xF8 */
__sbit __at (0x1234) SPIEN   ;  /* SPI 0 SPI ENABLE                              */
__sbit __at (0x1234) TXBMT   ;  /* SPI 0 TX BUFFER EMPTY FLAG                    */
__sbit __at (0x1234) NSSMD0  ;  /* SPI 0 SLAVE SELECT MODE 0                     */
__sbit __at (0x1234) NSSMD1  ;  /* SPI 0 SLAVE SELECT MODE 1                     */
__sbit __at (0x1234) RXOVRN  ;  /* SPI 0 RX OVERRUN FLAG                         */
__sbit __at (0x1234) MODF    ;  /* SPI 0 MODE FAULT FLAG                         */
__sbit __at (0x1234) WCOL    ;  /* SPI 0 WRITE COLLISION FLAG                    */
__sbit __at (0x1234) SPIF    ;  /* SPI 0 INTERRUPT FLAG                          */

/*  CAN0CN  0xF8 */
__sbit __at (0x1234) CANINIT ;  /* CAN INITIALIZATION                            */
__sbit __at (0x1234) CANIE   ;  /* CAN MODULE INTERRUPT ENABLE                   */
__sbit __at (0x1234) CANSIE  ;  /* CAN STATUS CHANGE INTERRUPT ENABLE            */
__sbit __at (0x1234) CANEIE  ;  /* CAN ERROR INTERRUPT ENABLE                    */
__sbit __at (0x1234) CANIF   ;  /* CAN INTERRUPT FLAG                            */
__sbit __at (0x1234) CANDAR  ;  /* CAN DISABLE AUTOMATIC RETRANSMISSION          */
__sbit __at (0x1234) CANCCE  ;  /* CAN CONFIGURATION CHANGE ENABLE               */
__sbit __at (0x1234) CANTEST ;  /* CAN TEST MODE ENABLE                          */

/*  P7  0xF8 */
__sbit __at (0x1234) P7_0    ;
__sbit __at (0x1234) P7_1    ;
__sbit __at (0x1234) P7_2    ;
__sbit __at (0x1234) P7_3    ;
__sbit __at (0x1234) P7_4    ;
__sbit __at (0x1234) P7_5    ;
__sbit __at (0x1234) P7_6    ;
__sbit __at (0x1234) P7_7    ;


/* Predefined SFR Bit Masks */

#define IDLE              0x01    /* PCON                                */
#define STOP              0x02    /* PCON                                */
#define ECCF              0x01    /* PCA0CPMn                            */
#define PWM               0x02    /* PCA0CPMn                            */
#define TOG               0x04    /* PCA0CPMn                            */
#define MAT               0x08    /* PCA0CPMn                            */
#define CAPN              0x10    /* PCA0CPMn                            */
#define CAPP              0x20    /* PCA0CPMn                            */
#define ECOM              0x40    /* PCA0CPMn                            */
#define PWM16             0x80    /* PCA0CPMn                            */
#define PORSF             0x02    /* RSTSRC                              */
#define SWRSF             0x10    /* RSTSRC                              */


/* SFR PAGE DEFINITIONS */

#define CONFIG_PAGE       0x0F     /* SYSTEM AND PORT CONFIGURATION PAGE */
#define LEGACY_PAGE       0x00     /* LEGACY SFR PAGE                    */
#define TIMER01_PAGE      0x00     /* TIMER 0 AND TIMER 1                */
#define CPT0_PAGE         0x01     /* COMPARATOR 0                       */
#define CPT1_PAGE         0x02     /* COMPARATOR 1                       */
#define CPT2_PAGE         0x03     /* COMPARATOR 2                       */
#define UART0_PAGE        0x00     /* UART 0                             */
#define UART1_PAGE        0x01     /* UART 1                             */
#define SPI0_PAGE         0x00     /* SPI 0                              */
#define EMI0_PAGE         0x00     /* EXTERNAL MEMORY INTERFACE          */
#define ADC0_PAGE         0x00     /* ADC 0                              */
#define ADC2_PAGE         0x02     /* ADC 2                              */
#define SMB0_PAGE         0x00     /* SMBUS 0                            */
#define TMR2_PAGE         0x00     /* TIMER 2                            */
#define TMR3_PAGE         0x01     /* TIMER 3                            */
#define TMR4_PAGE         0x02     /* TIMER 4                            */
#define DAC0_PAGE         0x00     /* DAC 0                              */
#define DAC1_PAGE         0x01     /* DAC 1                              */
#define PCA0_PAGE         0x00     /* PCA 0                              */
#define CAN0_PAGE         0x01     /* CAN 0                              */

#endif
