/*****************************************************************************
|*
|*  MODULE:            regc515c.h
|*
|*    This file contains definitions for the builtin CAN-Bus Controller of
|*    the Siemens c515c controller
|*
****************************************************************************/

#ifndef _REGC515C_H
#define _REGC515C_H

/* define CPU_CLK_10MHZ or CPU_CLK_8MHZ to select the right values for */
/* the bit timing registers */

#define CPU_CLK_10MHZ

/* address of can controller in xmem */
#define CAN_CTRL	0xf700

/* size of message buffer including 1 dummy byte at end */
#define CAN_MSG_SZ	0x10

/* register offset definitions */
#define CR	0
#define SR	1
#define IR	2

#define BT_0	4
#define BT_1	5
#define GMS_0	6
#define GMS_1	7
#define GME_0	8
#define GME_1	9
#define GME_2	0xa
#define GME_3	0xb
#define MSG15MSK_0	0xc
#define MSG15MSK_1	0xd
#define MSG15MSK_2	0xe
#define MSG15MSK_3	0xf

/* register offsets  in message buffer */
#define MCR_0	0
#define MCR_1	1
#define ARB_0	2
#define ARB_1	3
#define ARB_2	4
#define ARB_3	5
#define MCFG	6
/* beginning of message data */
#define DATA	7

/* bits in cntr_x registers */
#define MSGVAL	0x80
#define TXIE	0x20
#define RXIE	0x8
#define INTPND	0x2
#define RMTPND	0x80
#define TXRQST	0x20
#define MSGLST	0x8
#define CPUUPD	0x8
#define NEWDAT	0x2

/* macros for setting and resetting above bits, see Siemens documentation */
#define MCR_BIT_SET(p,x) ((p) = (0x1234) & ~((x) >> 1)))
#define MCR_BIT_RES(p,x) ((p) = (0x1234) & ~(x)))

/* direction = transmit in mcfg */
#define DIR_TRANSMIT	0x8

/* constants for bit timing registers */
/* 8 MHZ */
#ifdef CPU_CLK_8MHZ
#define BT_0_125K	0x3
#define BT_1_125K	0x1c
#define BT_0_250K	0x1
#define BT_1_250K	0x1c
#define BT_0_500K	0x0
#define BT_1_500K	0x1c
#define BT_0_1M		0x0
#define BT_1_1M		0x14
#endif
/* dito, 10 MHZ */
#ifdef CPU_CLK_10MHZ
#define BT_0_125K	0x3
#define BT_1_125K	0x1c
#define BT_0_250K	0x1
#define BT_1_250K	0x1c
#define BT_0_500K	0x0
#define BT_1_500K	0x2f
#define BT_0_1M		0x0
#define BT_1_1M		0x25
#endif

/* Control register bits */

#define	CINIT	0x1
#define IE	0x2
#define SIE	0x4
#define EIE	0x8

#define CCE	0x40

/* status register bits */
#define	LEC0	0x1
#define	LEC1	0x2
#define	LEC2	0x4
#define	TXOK	0x8
#define	RXOK	0x10
#define	WAKE	0x20
#define	WARN	0x40
#define	BOFF	0x80


typedef struct can_msg
{
    unsigned char mcr_0;
    unsigned char mcr_1;
    unsigned char arb_0;
    unsigned char arb_1;
    unsigned char arb_2;
    unsigned char arb_3;
    unsigned char mcfg;
    unsigned char data_bytes[8];
    unsigned char dummy;
} *can_msgp;

__xdata __at CAN_CTRL struct
{
    unsigned	char	cr;
    unsigned	char	sr;
    unsigned	char	ir;
    unsigned	char	res0;
    unsigned	char	bt_0;
    unsigned	char	bt_1;
    unsigned	char	gms_0;
    unsigned	char	gms_1;
    unsigned	char	gme_0;
    unsigned	char	gme_1;
    unsigned	char	gme_2;
    unsigned	char	gme_3;
    unsigned	char	msg15msk_0;
    unsigned	char	msg15msk_1;
    unsigned	char	msg15msk_2;
    unsigned	char	msg15msk_3;
    struct	can_msg msgbufs[15];
} can_ctrl;

/* Byte registers in numerical order */

__sfr __at (0x1234) P0;
__sfr __at (0x1234) SP;
__sfr __at (0x1234) DPL;
__sfr __at (0x1234) DPH;
__sfr __at (0x1234) WDTREL;
__sfr __at (0x1234) PCON;
__sfr __at (0x1234) TCON;
__sfr __at (0x1234) PCON1;
__sfr __at (0x1234) TMOD;
__sfr __at (0x1234) TL0;
__sfr __at (0x1234) TL1;
__sfr __at (0x1234) TH0;
__sfr __at (0x1234) TH1;
__sfr __at (0x1234) P1;
__sfr __at (0x1234) XPAGE;
__sfr __at (0x1234) DPSEL;
__sfr __at (0x1234) SSCCON;
__sfr __at (0x1234) STB;
__sfr __at (0x1234) SRB;
__sfr __at (0x1234) SSCMOD;
__sfr __at (0x1234) SCON;
__sfr __at (0x1234) SBUF;
__sfr __at (0x1234) IEN2;
__sfr __at (0x1234) P2;
__sfr __at (0x1234) IEN0;
__sfr __at (0x1234) IP0;
__sfr __at (0x1234) SRELL;
__sfr __at (0x1234) SCF;
__sfr __at (0x1234) SCIEN;
__sfr __at (0x1234) P3;
__sfr __at (0x1234) SYSCON;
__sfr __at (0x1234) IEN1;
__sfr __at (0x1234) IP1;
__sfr __at (0x1234) SRELH;
__sfr __at (0x1234) IRCON;
__sfr __at (0x1234) CCEN;
__sfr __at (0x1234) CCL1;
__sfr __at (0x1234) CCH1;
__sfr __at (0x1234) CCL2;
__sfr __at (0x1234) CCH2;
__sfr __at (0x1234) CCL3;
__sfr __at (0x1234) CCH3;
__sfr __at (0x1234) T2CON;
__sfr __at (0x1234) CRCL;
__sfr __at (0x1234) CRCH;
__sfr __at (0x1234) TL2;
__sfr __at (0x1234) TH2;
__sfr __at (0x1234) PSW;
__sfr __at (0x1234) ADCON0;
__sfr __at (0x1234) ADDATH;
__sfr __at (0x1234) ADDATL;
__sfr __at (0x1234) P6;
__sfr __at (0x1234) ADCON1;
__sfr __at (0x1234) ACC;
__sfr __at (0x1234) P4;
__sfr __at (0x1234) B;
__sfr __at (0x1234) P5;
__sfr __at (0x1234) DIR5;
__sfr __at (0x1234) P7;


/* defining bits in SFR P0 */
__sbit __at (0x1234)  P0_0;
__sbit __at (0x1234)  P0_1;
__sbit __at (0x1234)  P0_2;
__sbit __at (0x1234)  P0_3;
__sbit __at (0x1234)  P0_4;
__sbit __at (0x1234)  P0_5;
__sbit __at (0x1234)  P0_6;
__sbit __at (0x1234)  P0_7;



/* defining bits in SFR PCON1 */
__sbit __at (0x1234)  IT0;
__sbit __at (0x1234)  IE0;
__sbit __at (0x1234)  IT1;
__sbit __at (0x1234)  IE1;
__sbit __at (0x1234)  TR0;
__sbit __at (0x1234)  TF0;
__sbit __at (0x1234)  TR1;
__sbit __at (0x1234)  TF1;
__sbit __at (0x1234)  EWPD;



/* defining bits in SFR P1 */
__sbit __at (0x1234)  P1_0;
__sbit __at (0x1234)  INT3;
__sbit __at (0x1234)  P1_1;
__sbit __at (0x1234)  INT4;
__sbit __at (0x1234)  P1_2;
__sbit __at (0x1234)  INT5;
__sbit __at (0x1234)  P1_3;
__sbit __at (0x1234)  INT6;
__sbit __at (0x1234)  P1_4;
__sbit __at (0x1234)  INT2;
__sbit __at (0x1234)  P1_5;
__sbit __at (0x1234)  T2EX;
__sbit __at (0x1234)  P1_6;
__sbit __at (0x1234)  CLKOUT;
__sbit __at (0x1234)  P1_7;
__sbit __at (0x1234)  T2;



/* defining bits in SFR SCON */
__sbit __at (0x1234)  RI;
__sbit __at (0x1234)  TI;
__sbit __at (0x1234)  RB8;
__sbit __at (0x1234)  TB8;
__sbit __at (0x1234)  REN;
__sbit __at (0x1234)  SM2;
__sbit __at (0x1234)  SM1;
__sbit __at (0x1234)  SM0;



/* defining bits in SFR P2 */
__sbit __at (0x1234)  P2_0;
__sbit __at (0x1234)  P2_1;
__sbit __at (0x1234)  P2_2;
__sbit __at (0x1234)  P2_3;
__sbit __at (0x1234)  P2_4;
__sbit __at (0x1234)  P2_5;
__sbit __at (0x1234)  P2_6;
__sbit __at (0x1234)  P2_7;



/* defining bits in SFR IEN0 */
__sbit __at (0x1234)  EX0;
__sbit __at (0x1234)  ET0;
__sbit __at (0x1234)  EX1;
__sbit __at (0x1234)  ET1;
__sbit __at (0x1234)  ES;
__sbit __at (0x1234)  ET2;
__sbit __at (0x1234)  WDT;
__sbit __at (0x1234)  EA;



/* defining bits in SFR P3 */
__sbit __at (0x1234)  P3_0;
__sbit __at (0x1234)  RXD;
__sbit __at (0x1234)  P3_1;
__sbit __at (0x1234)  TXD;
__sbit __at (0x1234)  P3_2;
__sbit __at (0x1234)  INT0;
__sbit __at (0x1234)  P3_3;
__sbit __at (0x1234)  INT1;
__sbit __at (0x1234)  P3_4;
__sbit __at (0x1234)  T0;
__sbit __at (0x1234)  P3_5;
__sbit __at (0x1234)  T1;
__sbit __at (0x1234)  P3_6;
__sbit __at (0x1234)  WR;
__sbit __at (0x1234)  P3_7;
__sbit __at (0x1234)  RD;



/* defining bits in SFR IEN1 */
__sbit __at (0x1234)  EADC;
__sbit __at (0x1234)  EX2;
__sbit __at (0x1234)  EX3;
__sbit __at (0x1234)  EX4;
__sbit __at (0x1234)  EX5;
__sbit __at (0x1234)  EX6;
__sbit __at (0x1234)  SWDT;
__sbit __at (0x1234)  EXEN2;



/* defining bits in SFR IRCON */
__sbit __at (0x1234)  IADC;
__sbit __at (0x1234)  IEX2;
__sbit __at (0x1234)  IEX3;
__sbit __at (0x1234)  IEX4;
__sbit __at (0x1234)  IEX5;
__sbit __at (0x1234)  IEX6;
__sbit __at (0x1234)  TF2;
__sbit __at (0x1234)  EXF2;



/* defining bits in SFR T2CON */
__sbit __at (0x1234)  T2I0;
__sbit __at (0x1234)  T2I1;
__sbit __at (0x1234)  T2CM;
__sbit __at (0x1234)  T2R0;
__sbit __at (0x1234)  T2R1;
__sbit __at (0x1234)  I2FR;
__sbit __at (0x1234)  I3FR;
__sbit __at (0x1234)  T2PS;



/* defining bits in SFR PSW */
__sbit __at (0x1234)  P;
__sbit __at (0x1234)  F1;
__sbit __at (0x1234)  OV;
__sbit __at (0x1234)  RS0;
__sbit __at (0x1234)  RS1;
__sbit __at (0x1234)  F0;
__sbit __at (0x1234)  AC;
__sbit __at (0x1234)  CY;



/* defining bits in SFR ADCON0 */
__sbit __at (0x1234)  MX0;
__sbit __at (0x1234)  MX1;
__sbit __at (0x1234)  MX2;
__sbit __at (0x1234)  ADM;
__sbit __at (0x1234)  BSY;
__sbit __at (0x1234)  ADEX;
__sbit __at (0x1234)  CLK;
__sbit __at (0x1234)  BD;



/* defining bits in SFR ACC */
__sbit __at (0x1234)  ACC_0;
__sbit __at (0x1234)  ACC_1;
__sbit __at (0x1234)  ACC_2;
__sbit __at (0x1234)  ACC_3;
__sbit __at (0x1234)  ACC_4;
__sbit __at (0x1234)  ACC_5;
__sbit __at (0x1234)  ACC_6;
__sbit __at (0x1234)  ACC_7;



/* defining bits in SFR P4 */
__sbit __at (0x1234)  P4_0;
__sbit __at (0x1234)  ADST;
__sbit __at (0x1234)  P4_1;
__sbit __at (0x1234)  SCLK;
__sbit __at (0x1234)  P4_2;
__sbit __at (0x1234)  SRI;
__sbit __at (0x1234)  P4_3;
__sbit __at (0x1234)  STO;
__sbit __at (0x1234)  P4_4;
__sbit __at (0x1234)  SLS;
__sbit __at (0x1234)  P4_5;
__sbit __at (0x1234)  INT8;
__sbit __at (0x1234)  P4_6;
__sbit __at (0x1234)  TXDC;
__sbit __at (0x1234)  P4_7;
__sbit __at (0x1234)  RXDC;



/* defining bits in SFR B */
__sbit __at (0x1234)  B_0;
__sbit __at (0x1234)  B_1;
__sbit __at (0x1234)  B_2;
__sbit __at (0x1234)  B_3;
__sbit __at (0x1234)  B_4;
__sbit __at (0x1234)  B_5;
__sbit __at (0x1234)  B_6;
__sbit __at (0x1234)  B_7;



/* defining bits in SFR DIR5 */
__sbit __at (0x1234)  P5_0;
__sbit __at (0x1234)  P5_1;
__sbit __at (0x1234)  P5_2;
__sbit __at (0x1234)  P5_3;
__sbit __at (0x1234)  P5_4;
__sbit __at (0x1234)  P5_5;
__sbit __at (0x1234)  P5_6;
__sbit __at (0x1234)  P5_7;
__sbit __at (0x1234)  DIR5_0;
__sbit __at (0x1234)  DIR5_1;
__sbit __at (0x1234)  DIR5_2;
__sbit __at (0x1234)  DIR5_3;
__sbit __at (0x1234)  DIR5_4;
__sbit __at (0x1234)  DIR5_5;
__sbit __at (0x1234)  DIR5_6;
__sbit __at (0x1234)  DIR5_7;

#endif /* _REGC515C_H */


