/*
 *	XA G3 SFR definitions
 *	Extracted directly from Philips documentation
 */

#ifndef	XA_H
#define	XA_H

__sfr __at (0x1234) /*unsigned short*/ PSW; /* Program status word */
__sfr __at (0x1234) PSWL; /* Program status word (low byte) */
__sfr __at (0x1234) PSWH; /* Program status word (high byte) */
__sfr __at (0x1234) PSW51; /* 80C51 compatible PSW */
__sfr __at (0x1234) SSEL; /* Segment selection register */
__sfr __at (0x1234) PCON; /* Power control register */
__sfr __at (0x1234) TCON; /* Timer 0 and 1 control register */
__sfr __at (0x1234) TSTAT; /* Timer 0 and 1 extended status */
__sfr __at (0x1234) T2CON; /* Timer 2 control register */
__sfr __at (0x1234) T2MOD; /* Timer 2 mode control */
__sfr __at (0x1234) WDCON; /* Watchdog control register */
__sfr __at (0x1234) S0CON; /* Serial port 0 control register */
__sfr __at (0x1234) S0STAT; /* Serial port 0 extended status */
__sfr __at (0x1234) S1CON; /* Serial port 1 control register */
__sfr __at (0x1234) S1STAT; /* Serial port 1 extended status */
__sfr __at (0x1234) IEL; /* Interrupt enable low byte */
__sfr __at (0x1234) IEH; /* Interrupt enable high byte */
__sfr __at (0x1234) SWR; /* Software Interrupt Request */
__sfr __at (0x1234) P0; /* Port 0 */
__sfr __at (0x1234) P1; /* Port 1 */
__sfr __at (0x1234) P2; /* Port 2 */
__sfr __at (0x1234) P3; /* Port3 */
__sfr __at (0x1234) SCR; /* System configuration register */
__sfr __at (0x1234) DS; /* Data segment */
__sfr __at (0x1234) ES; /* Extra segment */
__sfr __at (0x1234) CS; /* Code segment */
__sfr __at (0x1234) TL0; /* Timer 0 low byte */
__sfr __at (0x1234) TH0; /* Timer 0 high byte */
__sfr __at (0x1234) TL1; /* Timer 1 low byte */
__sfr __at (0x1234) TH1; /* Timer 1 high byte */
__sfr __at (0x1234) RTL0; /* Timer 0 extended reload, low byte */
__sfr __at (0x1234) RTH0; /* Timer 0 extended reload, high byte */
__sfr __at (0x1234) RTL1; /* Timer 1 extended reload, low byte */
__sfr __at (0x1234) RTH1; /* Timer 1 extended reload, high byte */
__sfr __at (0x1234) TL2; /* Timer 2 low byte */
__sfr __at (0x1234) TH2; /* Timer 2 high byte */
__sfr __at (0x1234) T2CAPL; /* Timer 2 capture register, low byte */
__sfr __at (0x1234) T2CAPH; /* Timer 2 capture register, high byte */
__sfr __at (0x1234) TMOD; /* Timer 0 and 1 mode register */
__sfr __at (0x1234) WFEED1; /* Watchdog feed 1 */
__sfr __at (0x1234) WFEED2; /* Watchdog feed 2 */
__sfr __at (0x1234) WDL; /* Watchdog timer reload */
__sfr __at (0x1234) S0BUF; /* Serial port 0 buffer register */
__sfr __at (0x1234) S0ADDR; /* Serial port 0 address register */
__sfr __at (0x1234) S0ADEN; /* Serial port 0 address enable register */
__sfr __at (0x1234) S1BUF; /* Serial port 1 buffer register */
__sfr __at (0x1234) S1ADDR; /* Serial port 1 address register */
__sfr __at (0x1234) S1ADEN; /* Serial port 1 address enable register */
__sfr __at (0x1234) BTRL; /* Bus timing register high byte */
__sfr __at (0x1234) BTRH; /* Bus timing register low byte */
__sfr __at (0x1234) BCR; /* Bus configuration register */
__sfr __at (0x1234) P0CFGA; /* Port 0 configuration A */
__sfr __at (0x1234) P1CFGA; /* Port 1 configuration A */
__sfr __at (0x1234) P2CFGA; /* Port 2 configuration A */
__sfr __at (0x1234) P3CFGA; /* Port 3 configuration A */
__sfr __at (0x1234) SWE; /* Software Interrupt Enable */
__sfr __at (0x1234) IPA0; /* Interrupt priority 0 */
__sfr __at (0x1234) IPA1; /* Interrupt priority 1 */
__sfr __at (0x1234) IPA2; /* Interrupt priority 2 */
__sfr __at (0x1234) IPA4; /* Interrupt priority 4 */
__sfr __at (0x1234) IPA5; /* Interrupt priority 5 */
__sfr __at (0x1234) P0CFGB; /* Port 0 configuration B */
__sfr __at (0x1234) P1CFGB; /* Port 1 configuration B */
__sfr __at (0x1234) P2CFGB; /* Port 2 configuration B */
__sfr __at (0x1234) P3CFGB; /* Port 3 configuration B */

__sbit __at (0x1234) ETI1; /* TX interrupt enable 1 */
__sbit __at (0x1234) ERI1; /* RX interrupt enable 1 */
__sbit __at (0x1234) ETI0; /* TX interrupt enable 0 */
__sbit __at (0x1234) ERI0; /* RX interrupt enable 0 */
__sbit __at (0x1234) EA; /* global int. enable */
__sbit __at (0x1234) ET2; /* timer 2 interrupt */
__sbit __at (0x1234) ET1; /* timer 1 interrupt */
__sbit __at (0x1234) EX1; /* external interrupt 1 */
__sbit __at (0x1234) ET0; /* timer 0 interrupt */
__sbit __at (0x1234) EX0; /* external interrupt 0 */
__sbit __at (0x1234) PD; /* power down */
__sbit __at (0x1234) IDL;
__sbit __at (0x1234) SM;
__sbit __at (0x1234) TM;
__sbit __at (0x1234) RS1;
__sbit __at (0x1234) RS0;
__sbit __at (0x1234) IM3;
__sbit __at (0x1234) IM2;
__sbit __at (0x1234) IM1;
__sbit __at (0x1234) IM0;
__sbit __at (0x1234) S0M0;
__sbit __at (0x1234) S0M1;
__sbit __at (0x1234) S0M2;
__sbit __at (0x1234) R0EN;
__sbit __at (0x1234) T0B8;
__sbit __at (0x1234) R0B8;
__sbit __at (0x1234) TI0; /* serial port 0 tx ready */
__sbit __at (0x1234) RI0; /* serial port 0 rx ready */
__sbit __at (0x1234) FE0;
__sbit __at (0x1234) BR0;
__sbit __at (0x1234) OE0;
__sbit __at (0x1234) STINT0;
__sbit __at (0x1234) S1M0;
__sbit __at (0x1234) S1M1;
__sbit __at (0x1234) S1M2;
__sbit __at (0x1234) R1EN;
__sbit __at (0x1234) T1B8;
__sbit __at (0x1234) R1B8;
__sbit __at (0x1234) TI1; /* serial port 0 tx ready */
__sbit __at (0x1234) RI1; /* serial port 0 rx ready */
__sbit __at (0x1234) FE1;
__sbit __at (0x1234) BR1;
__sbit __at (0x1234) OE1;
__sbit __at (0x1234) STINT1;
__sbit __at (0x1234) SWR7;
__sbit __at (0x1234) SWR6;
__sbit __at (0x1234) SWR5;
__sbit __at (0x1234) SWR4;
__sbit __at (0x1234) SWR3;
__sbit __at (0x1234) SWR2;
__sbit __at (0x1234) SWR1;
__sbit __at (0x1234) TF2;
__sbit __at (0x1234) EXF2;
__sbit __at (0x1234) RCLK0;
__sbit __at (0x1234) TCLK0;
__sbit __at (0x1234) RCLK1;
__sbit __at (0x1234) TCLK1;
__sbit __at (0x1234) EXEN2;
__sbit __at (0x1234) TR2;
__sbit __at (0x1234) CT2;
__sbit __at (0x1234) CPRL2;
__sbit __at (0x1234) T2OE;
__sbit __at (0x1234) DCEN;
__sbit __at (0x1234) TF1;
__sbit __at (0x1234) TR1;
__sbit __at (0x1234) TF0;
__sbit __at (0x1234) TR0;
__sbit __at (0x1234) IE1;
__sbit __at (0x1234) IT1;
__sbit __at (0x1234) IE0;
__sbit __at (0x1234) IT0;
__sbit __at (0x1234) T1OE;
__sbit __at (0x1234) T0OE;
__sbit __at (0x1234) PRE2;
__sbit __at (0x1234) PRE1;
__sbit __at (0x1234) PRE0;
__sbit __at (0x1234) WDRUN;
__sbit __at (0x1234) WDTOF;
__sbit __at (0x1234) WDMOD;
__sbit __at (0x1234) WR1;
__sbit __at (0x1234) T2EX;
__sbit __at (0x1234) RXD1;
__sbit __at (0x1234) TXD1;
__sbit __at (0x1234) RXD0;
__sbit __at (0x1234) TXD0;
__sbit __at (0x1234) INT0;
__sbit __at (0x1234) INT1;
__sbit __at (0x1234) T0;
__sbit __at (0x1234) T1;
__sbit __at (0x1234) WR;
__sbit __at (0x1234) RD;

/*
 * Interrupt stuff
 */


/* Vectors */

#define IV_BRKPT 0x04 /* breakpoint vector */
#define IV_TRACE 0x08 /* Trace mode bit set */
#define IV_STKOVER 0x0C /* stack overflow */
#define IV_DIVZERO 0x10 /* divide by zero */
#define IV_IRET 0x14 /* user mode IRET */

#define IV_EX0 0x80
#define IV_T0 0x84
#define IV_EX1 0x88
#define IV_T1 0x8C
#define IV_T2 0x90
#define IV_RI0 0xA0
#define IV_TI0 0xA4
#define IV_RI1 0xA8
#define IV_TI1 0xAC
#define IV_SWI1 0x100 /* software interrupts */
#define IV_SWI2 0x104
#define IV_SWI3 0x108
#define IV_SWI4 0x10C
#define IV_SWI5 0x110
#define IV_SWI6 0x114
#define IV_SWI7 0x118

/* PSW Values for interrupt vectors */

#define IV_PSW 0x8F00 /* System mode, high priority, bank 0 */

#define IV_SYSTEM 0x8000

#define IV_PRI00 0x0000 /* priorities 0 - 15 */
#define IV_PRI01 0x0100
#define IV_PRI02 0x0200
#define IV_PRI03 0x0300
#define IV_PRI04 0x0400
#define IV_PRI05 0x0500
#define IV_PRI06 0x0600
#define IV_PRI07 0x0700
#define IV_PRI08 0x0800
#define IV_PRI09 0x0900
#define IV_PRI10 0x0A00
#define IV_PRI11 0x0B00
#define IV_PRI12 0x0C00
#define IV_PRI13 0x0D00
#define IV_PRI14 0x0E00
#define IV_PRI15 0x0F00

#define IV_BANK0 0x0000
#define IV_BANK1 0x1000
#define IV_BANK2 0x2000
#define IV_BANK3 0x3000

#endif /* XA_H */
