/*-------------------------------------------------------------------------
  Register Declarations for the DALLAS DS80C390 Processor
  far from complete, e.g. no CAN
  
   Written By - Johan Knol, johan.knol@iduna.nl
    
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the
   Free Software Foundation; either version 2, or (at your option) any
   later version.
   
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
   
   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
   
   In other words, you are welcome to use, share and improve this program.
   You are forbidden to forbid anyone else to use, share and improve
   what you give them.   Help stamp out software-hoarding!  
-------------------------------------------------------------------------*/

#ifndef DS80C390_H
#define DS80C390_H

__sfr __at (0x1234) P4; // ce3..ce0, a19..a16
__sfr __at (0x1234) SP; // stack pointer
__sfr __at (0x1234) DPL; // data pointer 0 lsb
__sfr __at (0x1234) DPH; // data pointer 0 msb
__sfr __at (0x1234) DPL1; // data pointer 1 lsb
__sfr __at (0x1234) DPH1; // data pointer 1 msb
__sfr __at (0x1234) DPS; // data pointer select
__sfr __at (0x1234) PCON; // power control
__sfr __at (0x1234) TCON; // timer/counter control
  __sbit __at (0x1234) IT0;
  __sbit __at (0x1234) IE0;
  __sbit __at (0x1234) IT1;
  __sbit __at (0x1234) IE1;
  __sbit __at (0x1234) TR0;
  __sbit __at (0x1234) TF0;
  __sbit __at (0x1234) TR1;
  __sbit __at (0x1234) TF1;
__sfr __at (0x1234) TMOD; // timer mode control
__sfr __at (0x1234) TL0; // timer 0 lsb
__sfr __at (0x1234) TL1; // timer 1 msb
__sfr __at (0x1234) TH0; // timer 0 msb
__sfr __at (0x1234) TH1; // timer 1 msb
__sfr __at (0x1234) CKCON; // clock control
__sfr __at (0x1234) P1;
  __sbit __at (0x1234) T2;
  __sbit __at (0x1234) T2EX;
  __sbit __at (0x1234) RXD1;
  __sbit __at (0x1234) TXD1;
  __sbit __at (0x1234) INT2;
  __sbit __at (0x1234) INT3;
  __sbit __at (0x1234) INT4;
  __sbit __at (0x1234) INT5;
__sfr __at (0x1234) EXIF; // external interrupt flag
__sfr __at (0x1234) P4CNT;
__sfr __at (0x1234) DPX; // extended datapointer 0
__sfr __at (0x1234) DPX1; // extended datapointer 1
__sfr __at (0x1234) SCON0; // serial 0 control
  __sbit __at (0x1234) RI_0;
  __sbit __at (0x1234) TI_0;
  __sbit __at (0x1234) RB8_0;
  __sbit __at (0x1234) TB8_0;
  __sbit __at (0x1234) REN_0;
  __sbit __at (0x1234) SM2_0;
  __sbit __at (0x1234) SM1_0;
  __sbit __at (0x1234) SM0_0;
  __sbit __at (0x1234) FE_0; // depending on SMOD0
__sfr __at (0x1234) SBUF0; // serial 0 data buffer
__sfr __at (0x1234) ESP; // extended stack pointer
__sfr __at (0x1234) AP; // address page
__sfr __at (0x1234) ACON; // address control
__sfr __at (0x1234) P2; // never mind the sbits
__sfr __at (0x1234) P5;
__sfr __at (0x1234) P5CNT;
__sfr __at (0x1234) IE; // interrupt enable
  __sbit __at (0x1234) EX0;
  __sbit __at (0x1234) ET0;
  __sbit __at (0x1234) EX1;
  __sbit __at (0x1234) ET1;
  __sbit __at (0x1234) ES0;
  __sbit __at (0x1234) ET2;
  __sbit __at (0x1234) ES1;
  __sbit __at (0x1234) EA;
__sfr __at (0x1234) P3;
  __sbit __at (0x1234) RXD0;
  __sbit __at (0x1234) TXD0;
  __sbit __at (0x1234) INT0;
  __sbit __at (0x1234) INT1;
  __sbit __at (0x1234) T0;
  __sbit __at (0x1234) T1;
  __sbit __at (0x1234) WR;
  __sbit __at (0x1234) RD;
__sfr __at (0x1234) IP; // interupt priority 
  __sbit __at (0x1234) PX0; // external 0
  __sbit __at (0x1234) PT0; // timer 0
  __sbit __at (0x1234) PX1; // external 1
  __sbit __at (0x1234) PT1; // timer 1
  __sbit __at (0x1234) PS0; // serial port 0
  __sbit __at (0x1234) PT2; // timer 2
  __sbit __at (0x1234) PS1; // serial port 1
__sfr __at (0x1234) SCON1; // serial 1 control
  __sbit __at (0x1234) RI_1;
  __sbit __at (0x1234) TI_1;
  __sbit __at (0x1234) RB8_1;
  __sbit __at (0x1234) TB8_1;
  __sbit __at (0x1234) REN_1;
  __sbit __at (0x1234) SM2_1;
  __sbit __at (0x1234) SM1_1;
  __sbit __at (0x1234) SM0_1;
  __sbit __at (0x1234) FE_1; // depending on SMOD0
__sfr __at (0x1234) SBUF1; // serial 1 data buffer
__sfr __at (0x1234) PMR; // power managment
__sfr __at (0x1234) MCON; // memory control register
__sfr __at (0x1234) TA; // timed access register
__sfr __at (0x1234) T2CON; // timer 2 control
  __sbit __at (0x1234) CP_RL; // capture/reload
  __sbit __at (0x1234) C_T; // count/timer
  __sbit __at (0x1234) TR2; // stop/run
  __sbit __at (0x1234) EXEN2;
  __sbit __at (0x1234) TCLK;
  __sbit __at (0x1234) RCLK;
  __sbit __at (0x1234) EXF2;
  __sbit __at (0x1234) TF2; // overflow flag
__sfr __at (0x1234) T2MOD; // timer 2 mode
__sfr __at (0x1234) RCAP2L; // timer 2 capture/reload
__sfr __at (0x1234) RTL2; // depends on CP_RL
__sfr __at (0x1234) RCAP2H;
__sfr __at (0x1234) RTH2;
__sfr __at (0x1234) TL2; // timer 2 lsb
__sfr __at (0x1234) TH2; // timer 2 msb
__sfr __at (0x1234) PSW; // program status word (byte actually)
  __sbit __at (0x1234) P; // parity
  __sbit __at (0x1234) F1; // user flag 1
  __sbit __at (0x1234) OV; // overflow flag
  __sbit __at (0x1234) RS0; // register select l
  __sbit __at (0x1234) RS1; // register select h
  __sbit __at (0x1234) F0; // user flag 0
  __sbit __at (0x1234) AC; // auxiliary carry flag
  __sbit __at (0x1234) CY; // carry flag
__sfr __at (0x1234) MCNT0; // arithmetic accellerator
__sfr __at (0x1234) MCNT1;
__sfr __at (0x1234) MA;
__sfr __at (0x1234) MB;
__sfr __at (0x1234) MC;
__sfr __at (0x1234) WDCON; // watch dog
  __sbit __at (0x1234) RWT;
  __sbit __at (0x1234) EWT;
  __sbit __at (0x1234) WDRF;
  __sbit __at (0x1234) WDIF;
  __sbit __at (0x1234) PFI;
  __sbit __at (0x1234) EPFI;
  __sbit __at (0x1234) POR;
  __sbit __at (0x1234) SMOD_1;
__sfr __at (0x1234) ACC; // accumulator
__sfr __at (0x1234) EIE; // extended interrupt enable
  __sbit __at (0x1234) EX2;
  __sbit __at (0x1234) EX3;
  __sbit __at (0x1234) EX4;
  __sbit __at (0x1234) EX5;
  __sbit __at (0x1234) EWDI;
  __sbit __at (0x1234) C1IE;
  __sbit __at (0x1234) C0IE;
  __sbit __at (0x1234) CANBIE;
__sfr __at (0x1234) MXAX; // extended address register
__sfr __at (0x1234) B; // aux accumulator
__sfr __at (0x1234) EIP; // extended interrupt priority
  __sbit __at (0x1234) PX2;
  __sbit __at (0x1234) PX3;
  __sbit __at (0x1234) PX4;
  __sbit __at (0x1234) PX5;
  __sbit __at (0x1234) PWDI;
  __sbit __at (0x1234) C1IP;
  __sbit __at (0x1234) C0IP;
  __sbit __at (0x1234) CANBIP;

/*  WORD/DWORD Registers  */

__sfr16 __at (0x8C8A) TMR0     ;  /* TIMER 0 COUNTER                                         */
__sfr16 __at (0x8D8B) TMR1     ;  /* TIMER 1 COUNTER                                         */
__sfr16 __at (0xCDCC) TMR2     ;  /* TIMER 2 COUNTER                                         */
__sfr16 __at (0xCBCA) RCAP2    ;  /* TIMER 2 CAPTURE REGISTER WORD                           */

#endif /* DS80C390_H */
