/* Based on CPU DB MC68HC908GR60A_64, version 2.87.097 (RegistersPrg V2.30) */
/*
** ###################################################################
**     Filename  : mc68hc908gr60a.h
**     Processor : MC68HC908GR60ACFU
**     FileFormat: V2.30
**     DataSheet : MC68HC908GR60A Rev. 5 04/2007
**     Compiler  : CodeWarrior compiler
**     Date/Time : 11.9.2009, 14:08
**     Abstract  :
**         This header implements the mapping of I/O devices.
**
**     Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved.
**     
**     http      : www.freescale.com
**     mail      : support@freescale.com
**
**     CPU Registers Revisions:
**      - 06.12.2007, V2.87.094:
**              - Renamed bit SCIACTL_AOVFL ==> SCIACTL_AROVFL. REASON: Bug-fix (#4090 in Issue Manager).
**
**     File-Format-Revisions:
**      - 14.11.2005, V2.00 :
**               - Deprecated symbols added for backward compatibility (section at the end of this file)
**      - 15.11.2005, V2.01 :
**               - Changes have not affected this file (because they are related to another family)
**      - 17.12.2005, V2.02 :
**               - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778
**      - 16.01.2006, V2.03 :
**               - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920.
**               - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const")
**      - 08.03.2006, V2.04 :
**               - Support for bit(s) names duplicated with any register name in .h header files
**      - 24.03.2006, V2.05 :
**               - Changes have not affected this file (because they are related to another family)
**      - 26.04.2006, V2.06 :
**               - Absolute assembly supported (depreciated symbols are not defined)
**      - 27.04.2006, V2.07 :
**               - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA).
**      - 07.06.2006, V2.08 :
**               - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM.
**      - 03.07.2006, V2.09 :
**               - Flash commands constants supported
**      - 27.10.2006, V2.10 :
**               - __RESET_WATCHDOG improved formating and re-definition
**      - 23.11.2006, V2.11 :
**               - Changes have not affected this file (because they are related to another family)
**      - 22.01.2007, V2.12 :
**               - Changes have not affected this file (because they are related to another family)
**      - 01.03.2007, V2.13 :
**               - Flash commands constants values converted to HEX format
**      - 02.03.2007, V2.14 :
**               - Interrupt vector numbers added into .H, see VectorNumber_*
**      - 26.03.2007, V2.15 :
**               - Changes have not affected this file (because they are related to another family)
**      - 10.05.2007, V2.16 :
**               - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ)
**      - 05.06.2007, V2.17 :
**               - Changes have not affected this file (because they are related to another family)
**      - 19.07.2007, V2.18 :
**               - Improved number of blanked lines inside register structures
**      - 06.08.2007, V2.19 :
**               - CPUDB revisions generated ahead of the file-format revisions.
**      - 11.09.2007, V2.20 :
**               - Added comment about initialization of unbonded pins.
**      - 02.01.2008, V2.21 :
**               - Changes have not affected this file (because they are related to another family)
**      - 13.02.2008, V2.22 :
**               - Changes have not affected this file (because they are related to another family)
**      - 20.02.2008, V2.23 :
**               - Changes have not affected this file (because they are related to another family)
**      - 03.07.2008, V2.24 :
**               - Added support for bits with name starting with number (like "1HZ")
**      - 28.11.2008, V2.25 :
**               - StandBy RAM array declaration for ANSI-C added
**      - 1.12.2008, V2.26 :
**               - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map.
**      - 17.3.2009, V2.27 :
**               - Merged bit-group is not generated, if the name matches with another bit name in the register
**      - 6.4.2009, V2.28 :
**               - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB
**      - 3.8.2009, V2.29 :
**               - If there is just one bits group matching register name, single bits are not generated
**      - 10.9.2009, V2.30 :
**               - Fixed generation of registers arrays.
**
**     Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific
**     derivative device. To avoid extra current drain from floating input pins, the user’s reset
**     initialization routine in the application program must either enable on-chip pull-up devices
**     or change the direction of unconnected pins to outputs so the pins do not float.
** ###################################################################
*/

#ifndef _MC68HC908GR60A_H
#define _MC68HC908GR60A_H

/* Types definition */
typedef unsigned char byte;
typedef unsigned int word;
typedef unsigned long dword;
typedef unsigned long dlong[2];

/* Watchdog reset macro */
#ifndef __RESET_WATCHDOG
#ifdef _lint
  #define __RESET_WATCHDOG()  /* empty */
#else
  #define __RESET_WATCHDOG() {asm sta COPCTL;}
#endif
#endif /* __RESET_WATCHDOG */

#define REG_BASE 0x0000                /* Base address for the I/O register block */


#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */

/**************** interrupt vector numbers ****************/
#define VectorNumber_TIM2CH5            25
#define VectorNumber_TIM2CH4            24
#define VectorNumber_TIM2CH3            23
#define VectorNumber_TIM2CH2            22
#define VectorNumber_Reserved4          21
#define VectorNumber_Reserved5          20
#define VectorNumber_Reserved6          19
#define VectorNumber_Reserved7          18
#define VectorNumber_TBM                17
#define VectorNumber_ADC                16
#define VectorNumber_KBD                15
#define VectorNumber_SCITransmit        14
#define VectorNumber_SCIReceive         13
#define VectorNumber_SCIError           12
#define VectorNumber_SPITransmit        11
#define VectorNumber_SPIReceive         10
#define VectorNumber_TIM2Ovr            9
#define VectorNumber_TIM2CH1            8
#define VectorNumber_TIM2CH0            7
#define VectorNumber_TIM1Ovr            6
#define VectorNumber_TIM1CH1            5
#define VectorNumber_TIM1CH0            4
#define VectorNumber_PLL                3
#define VectorNumber_IRQ                2
#define VectorNumber_SWI                1
#define VectorNumber_RESET              0

/**************** interrupt vector table ****************/
#define INT_TIM2CH5                     0x0000FFCC
#define INT_TIM2CH4                     0x0000FFCE
#define INT_TIM2CH3                     0x0000FFD0
#define INT_TIM2CH2                     0x0000FFD2
#define Reserved4                       0x0000FFD4
#define Reserved5                       0x0000FFD6
#define Reserved6                       0x0000FFD8
#define Reserved7                       0x0000FFDA
#define INT_TBM                         0x0000FFDC
#define INT_ADC                         0x0000FFDE
#define INT_KBD                         0x0000FFE0
#define INT_SCITransmit                 0x0000FFE2
#define INT_SCIReceive                  0x0000FFE4
#define INT_SCIError                    0x0000FFE6
#define INT_SPITransmit                 0x0000FFE8
#define INT_SPIReceive                  0x0000FFEA
#define INT_TIM2Ovr                     0x0000FFEC
#define INT_TIM2CH1                     0x0000FFEE
#define INT_TIM2CH0                     0x0000FFF0
#define INT_TIM1Ovr                     0x0000FFF2
#define INT_TIM1CH1                     0x0000FFF4
#define INT_TIM1CH0                     0x0000FFF6
#define INT_PLL                         0x0000FFF8
#define INT_IRQ                         0x0000FFFA
#define INT_SWI                         0x0000FFFC
#define INT_RESET                       0x0000FFFE

/**************** registers I/O map ****************/

/*** PTA - Port A Data Register; 0x00000000 ***/
typedef union {
  byte Byte;
  struct {
    byte PTA0        :1;                                       /* Port A Data Bit 0 */
    byte PTA1        :1;                                       /* Port A Data Bit 1 */
    byte PTA2        :1;                                       /* Port A Data Bit 2 */
    byte PTA3        :1;                                       /* Port A Data Bit 3 */
    byte PTA4        :1;                                       /* Port A Data Bit 4 */
    byte PTA5        :1;                                       /* Port A Data Bit 5 */
    byte PTA6        :1;                                       /* Port A Data Bit 6 */
    byte PTA7        :1;                                       /* Port A Data Bit 7 */
  } Bits;
} PTASTR;
extern volatile PTASTR _PTA;
#define PTA                             _PTA.Byte
#define PTA_PTA0                        _PTA.Bits.PTA0
#define PTA_PTA1                        _PTA.Bits.PTA1
#define PTA_PTA2                        _PTA.Bits.PTA2
#define PTA_PTA3                        _PTA.Bits.PTA3
#define PTA_PTA4                        _PTA.Bits.PTA4
#define PTA_PTA5                        _PTA.Bits.PTA5
#define PTA_PTA6                        _PTA.Bits.PTA6
#define PTA_PTA7                        _PTA.Bits.PTA7

#define PTA_PTA0_MASK                   1
#define PTA_PTA1_MASK                   2
#define PTA_PTA2_MASK                   4
#define PTA_PTA3_MASK                   8
#define PTA_PTA4_MASK                   16
#define PTA_PTA5_MASK                   32
#define PTA_PTA6_MASK                   64
#define PTA_PTA7_MASK                   128


/*** PTB - Port B Data Register; 0x00000001 ***/
typedef union {
  byte Byte;
  struct {
    byte PTB0        :1;                                       /* Port B Data Bit 0 */
    byte PTB1        :1;                                       /* Port B Data Bit 1 */
    byte PTB2        :1;                                       /* Port B Data Bit 2 */
    byte PTB3        :1;                                       /* Port B Data Bit 3 */
    byte PTB4        :1;                                       /* Port B Data Bit 4 */
    byte PTB5        :1;                                       /* Port B Data Bit 5 */
    byte PTB6        :1;                                       /* Port B Data Bit 6 */
    byte PTB7        :1;                                       /* Port B Data Bit 7 */
  } Bits;
} PTBSTR;
extern volatile PTBSTR _PTB;
#define PTB                             _PTB.Byte
#define PTB_PTB0                        _PTB.Bits.PTB0
#define PTB_PTB1                        _PTB.Bits.PTB1
#define PTB_PTB2                        _PTB.Bits.PTB2
#define PTB_PTB3                        _PTB.Bits.PTB3
#define PTB_PTB4                        _PTB.Bits.PTB4
#define PTB_PTB5                        _PTB.Bits.PTB5
#define PTB_PTB6                        _PTB.Bits.PTB6
#define PTB_PTB7                        _PTB.Bits.PTB7

#define PTB_PTB0_MASK                   1
#define PTB_PTB1_MASK                   2
#define PTB_PTB2_MASK                   4
#define PTB_PTB3_MASK                   8
#define PTB_PTB4_MASK                   16
#define PTB_PTB5_MASK                   32
#define PTB_PTB6_MASK                   64
#define PTB_PTB7_MASK                   128


/*** PTC - Port C Data Register; 0x00000002 ***/
typedef union {
  byte Byte;
  struct {
    byte PTC0        :1;                                       /* Port C Data Bit 0 */
    byte PTC1        :1;                                       /* Port C Data Bit 1 */
    byte PTC2        :1;                                       /* Port C Data Bit 2 */
    byte PTC3        :1;                                       /* Port C Data Bit 3 */
    byte PTC4        :1;                                       /* Port C Data Bit 4 */
    byte PTC5        :1;                                       /* Port C Data Bit 5 */
    byte PTC6        :1;                                       /* Port C Data Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpPTC  :7;
    byte         :1;
  } MergedBits;
} PTCSTR;
extern volatile PTCSTR _PTC;
#define PTC                             _PTC.Byte
#define PTC_PTC0                        _PTC.Bits.PTC0
#define PTC_PTC1                        _PTC.Bits.PTC1
#define PTC_PTC2                        _PTC.Bits.PTC2
#define PTC_PTC3                        _PTC.Bits.PTC3
#define PTC_PTC4                        _PTC.Bits.PTC4
#define PTC_PTC5                        _PTC.Bits.PTC5
#define PTC_PTC6                        _PTC.Bits.PTC6
#define PTC_PTC                         _PTC.MergedBits.grpPTC

#define PTC_PTC0_MASK                   1
#define PTC_PTC1_MASK                   2
#define PTC_PTC2_MASK                   4
#define PTC_PTC3_MASK                   8
#define PTC_PTC4_MASK                   16
#define PTC_PTC5_MASK                   32
#define PTC_PTC6_MASK                   64
#define PTC_PTC_MASK                    127
#define PTC_PTC_BITNUM                  0


/*** PTD - Port D Data Register; 0x00000003 ***/
typedef union {
  byte Byte;
  struct {
    byte PTD0        :1;                                       /* Port D Data Bit 0 */
    byte PTD1        :1;                                       /* Port D Data Bit 1 */
    byte PTD2        :1;                                       /* Port D Data Bit 2 */
    byte PTD3        :1;                                       /* Port D Data Bit 3 */
    byte PTD4        :1;                                       /* Port D Data Bit 4 */
    byte PTD5        :1;                                       /* Port D Data Bit 5 */
    byte PTD6        :1;                                       /* Port D Data Bit 6 */
    byte PTD7        :1;                                       /* Port D Data Bit 7 */
  } Bits;
} PTDSTR;
extern volatile PTDSTR _PTD;
#define PTD                             _PTD.Byte
#define PTD_PTD0                        _PTD.Bits.PTD0
#define PTD_PTD1                        _PTD.Bits.PTD1
#define PTD_PTD2                        _PTD.Bits.PTD2
#define PTD_PTD3                        _PTD.Bits.PTD3
#define PTD_PTD4                        _PTD.Bits.PTD4
#define PTD_PTD5                        _PTD.Bits.PTD5
#define PTD_PTD6                        _PTD.Bits.PTD6
#define PTD_PTD7                        _PTD.Bits.PTD7

#define PTD_PTD0_MASK                   1
#define PTD_PTD1_MASK                   2
#define PTD_PTD2_MASK                   4
#define PTD_PTD3_MASK                   8
#define PTD_PTD4_MASK                   16
#define PTD_PTD5_MASK                   32
#define PTD_PTD6_MASK                   64
#define PTD_PTD7_MASK                   128


/*** DDRA - Data Direction Register A; 0x00000004 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRA0       :1;                                       /* Data Direction Register A Bit 0 */
    byte DDRA1       :1;                                       /* Data Direction Register A Bit 1 */
    byte DDRA2       :1;                                       /* Data Direction Register A Bit 2 */
    byte DDRA3       :1;                                       /* Data Direction Register A Bit 3 */
    byte DDRA4       :1;                                       /* Data Direction Register A Bit 4 */
    byte DDRA5       :1;                                       /* Data Direction Register A Bit 5 */
    byte DDRA6       :1;                                       /* Data Direction Register A Bit 6 */
    byte DDRA7       :1;                                       /* Data Direction Register A Bit 7 */
  } Bits;
} DDRASTR;
extern volatile DDRASTR _DDRA;
#define DDRA                            _DDRA.Byte
#define DDRA_DDRA0                      _DDRA.Bits.DDRA0
#define DDRA_DDRA1                      _DDRA.Bits.DDRA1
#define DDRA_DDRA2                      _DDRA.Bits.DDRA2
#define DDRA_DDRA3                      _DDRA.Bits.DDRA3
#define DDRA_DDRA4                      _DDRA.Bits.DDRA4
#define DDRA_DDRA5                      _DDRA.Bits.DDRA5
#define DDRA_DDRA6                      _DDRA.Bits.DDRA6
#define DDRA_DDRA7                      _DDRA.Bits.DDRA7

#define DDRA_DDRA0_MASK                 1
#define DDRA_DDRA1_MASK                 2
#define DDRA_DDRA2_MASK                 4
#define DDRA_DDRA3_MASK                 8
#define DDRA_DDRA4_MASK                 16
#define DDRA_DDRA5_MASK                 32
#define DDRA_DDRA6_MASK                 64
#define DDRA_DDRA7_MASK                 128


/*** DDRB - Data Direction Register B; 0x00000005 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRB0       :1;                                       /* Data Direction Register B Bit 0 */
    byte DDRB1       :1;                                       /* Data Direction Register B Bit 1 */
    byte DDRB2       :1;                                       /* Data Direction Register B Bit 2 */
    byte DDRB3       :1;                                       /* Data Direction Register B Bit 3 */
    byte DDRB4       :1;                                       /* Data Direction Register B Bit 4 */
    byte DDRB5       :1;                                       /* Data Direction Register B Bit 5 */
    byte DDRB6       :1;                                       /* Data Direction Register B Bit 6 */
    byte DDRB7       :1;                                       /* Data Direction Register B Bit 7 */
  } Bits;
} DDRBSTR;
extern volatile DDRBSTR _DDRB;
#define DDRB                            _DDRB.Byte
#define DDRB_DDRB0                      _DDRB.Bits.DDRB0
#define DDRB_DDRB1                      _DDRB.Bits.DDRB1
#define DDRB_DDRB2                      _DDRB.Bits.DDRB2
#define DDRB_DDRB3                      _DDRB.Bits.DDRB3
#define DDRB_DDRB4                      _DDRB.Bits.DDRB4
#define DDRB_DDRB5                      _DDRB.Bits.DDRB5
#define DDRB_DDRB6                      _DDRB.Bits.DDRB6
#define DDRB_DDRB7                      _DDRB.Bits.DDRB7

#define DDRB_DDRB0_MASK                 1
#define DDRB_DDRB1_MASK                 2
#define DDRB_DDRB2_MASK                 4
#define DDRB_DDRB3_MASK                 8
#define DDRB_DDRB4_MASK                 16
#define DDRB_DDRB5_MASK                 32
#define DDRB_DDRB6_MASK                 64
#define DDRB_DDRB7_MASK                 128


/*** DDRC - Data Direction Register C; 0x00000006 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRC0       :1;                                       /* Data Direction Register C Bit 0 */
    byte DDRC1       :1;                                       /* Data Direction Register C Bit 1 */
    byte DDRC2       :1;                                       /* Data Direction Register C Bit 2 */
    byte DDRC3       :1;                                       /* Data Direction Register C Bit 3 */
    byte DDRC4       :1;                                       /* Data Direction Register C Bit 4 */
    byte DDRC5       :1;                                       /* Data Direction Register C Bit 5 */
    byte DDRC6       :1;                                       /* Data Direction Register C Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpDDRC :7;
    byte         :1;
  } MergedBits;
} DDRCSTR;
extern volatile DDRCSTR _DDRC;
#define DDRC                            _DDRC.Byte
#define DDRC_DDRC0                      _DDRC.Bits.DDRC0
#define DDRC_DDRC1                      _DDRC.Bits.DDRC1
#define DDRC_DDRC2                      _DDRC.Bits.DDRC2
#define DDRC_DDRC3                      _DDRC.Bits.DDRC3
#define DDRC_DDRC4                      _DDRC.Bits.DDRC4
#define DDRC_DDRC5                      _DDRC.Bits.DDRC5
#define DDRC_DDRC6                      _DDRC.Bits.DDRC6
#define DDRC_DDRC                       _DDRC.MergedBits.grpDDRC

#define DDRC_DDRC0_MASK                 1
#define DDRC_DDRC1_MASK                 2
#define DDRC_DDRC2_MASK                 4
#define DDRC_DDRC3_MASK                 8
#define DDRC_DDRC4_MASK                 16
#define DDRC_DDRC5_MASK                 32
#define DDRC_DDRC6_MASK                 64
#define DDRC_DDRC_MASK                  127
#define DDRC_DDRC_BITNUM                0


/*** DDRD - Data Direction Register D; 0x00000007 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRD0       :1;                                       /* Data Direction Register D Bit 0 */
    byte DDRD1       :1;                                       /* Data Direction Register D Bit 1 */
    byte DDRD2       :1;                                       /* Data Direction Register D Bit 2 */
    byte DDRD3       :1;                                       /* Data Direction Register D Bit 3 */
    byte DDRD4       :1;                                       /* Data Direction Register D Bit 4 */
    byte DDRD5       :1;                                       /* Data Direction Register D Bit 5 */
    byte DDRD6       :1;                                       /* Data Direction Register D Bit 6 */
    byte DDRD7       :1;                                       /* Data Direction Register D Bit 7 */
  } Bits;
} DDRDSTR;
extern volatile DDRDSTR _DDRD;
#define DDRD                            _DDRD.Byte
#define DDRD_DDRD0                      _DDRD.Bits.DDRD0
#define DDRD_DDRD1                      _DDRD.Bits.DDRD1
#define DDRD_DDRD2                      _DDRD.Bits.DDRD2
#define DDRD_DDRD3                      _DDRD.Bits.DDRD3
#define DDRD_DDRD4                      _DDRD.Bits.DDRD4
#define DDRD_DDRD5                      _DDRD.Bits.DDRD5
#define DDRD_DDRD6                      _DDRD.Bits.DDRD6
#define DDRD_DDRD7                      _DDRD.Bits.DDRD7

#define DDRD_DDRD0_MASK                 1
#define DDRD_DDRD1_MASK                 2
#define DDRD_DDRD2_MASK                 4
#define DDRD_DDRD3_MASK                 8
#define DDRD_DDRD4_MASK                 16
#define DDRD_DDRD5_MASK                 32
#define DDRD_DDRD6_MASK                 64
#define DDRD_DDRD7_MASK                 128


/*** PTE - Port E Data Register; 0x00000008 ***/
typedef union {
  byte Byte;
  struct {
    byte PTE0        :1;                                       /* Port E Data Bit 0 */
    byte PTE1        :1;                                       /* Port E Data Bit 1 */
    byte PTE2        :1;                                       /* Port E Data Bit 2 */
    byte PTE3        :1;                                       /* Port E Data Bit 3 */
    byte PTE4        :1;                                       /* Port E Data Bit 4 */
    byte PTE5        :1;                                       /* Port E Data Bit 5 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpPTE  :6;
    byte         :1;
    byte         :1;
  } MergedBits;
} PTESTR;
extern volatile PTESTR _PTE;
#define PTE                             _PTE.Byte
#define PTE_PTE0                        _PTE.Bits.PTE0
#define PTE_PTE1                        _PTE.Bits.PTE1
#define PTE_PTE2                        _PTE.Bits.PTE2
#define PTE_PTE3                        _PTE.Bits.PTE3
#define PTE_PTE4                        _PTE.Bits.PTE4
#define PTE_PTE5                        _PTE.Bits.PTE5
#define PTE_PTE                         _PTE.MergedBits.grpPTE

#define PTE_PTE0_MASK                   1
#define PTE_PTE1_MASK                   2
#define PTE_PTE2_MASK                   4
#define PTE_PTE3_MASK                   8
#define PTE_PTE4_MASK                   16
#define PTE_PTE5_MASK                   32
#define PTE_PTE_MASK                    63
#define PTE_PTE_BITNUM                  0


/*** SCPSC - ESCI Prescaler Register; 0x00000009 ***/
typedef union {
  byte Byte;
  struct {
    byte PSSB0       :1;                                       /* Clock Insertion Select Bit 0 */
    byte PSSB1       :1;                                       /* Clock Insertion Select Bit 1 */
    byte PSSB2       :1;                                       /* Clock Insertion Select Bit 2 */
    byte PSSB3       :1;                                       /* Clock Insertion Select Bit 3 */
    byte PSSB4       :1;                                       /* Clock Insertion Select Bit 4 */
    byte PDS0        :1;                                       /* Prescaler Divisor Select Bit 0 */
    byte PDS1        :1;                                       /* Prescaler Divisor Select Bit 1 */
    byte PDS2        :1;                                       /* Prescaler Divisor Select Bit 2 */
  } Bits;
  struct {
    byte grpPSSB :5;
    byte grpPDS  :3;
  } MergedBits;
} SCPSCSTR;
extern volatile SCPSCSTR _SCPSC;
#define SCPSC                           _SCPSC.Byte
#define SCPSC_PSSB0                     _SCPSC.Bits.PSSB0
#define SCPSC_PSSB1                     _SCPSC.Bits.PSSB1
#define SCPSC_PSSB2                     _SCPSC.Bits.PSSB2
#define SCPSC_PSSB3                     _SCPSC.Bits.PSSB3
#define SCPSC_PSSB4                     _SCPSC.Bits.PSSB4
#define SCPSC_PDS0                      _SCPSC.Bits.PDS0
#define SCPSC_PDS1                      _SCPSC.Bits.PDS1
#define SCPSC_PDS2                      _SCPSC.Bits.PDS2
#define SCPSC_PSSB                      _SCPSC.MergedBits.grpPSSB
#define SCPSC_PDS                       _SCPSC.MergedBits.grpPDS

#define SCPSC_PSSB0_MASK                1
#define SCPSC_PSSB1_MASK                2
#define SCPSC_PSSB2_MASK                4
#define SCPSC_PSSB3_MASK                8
#define SCPSC_PSSB4_MASK                16
#define SCPSC_PDS0_MASK                 32
#define SCPSC_PDS1_MASK                 64
#define SCPSC_PDS2_MASK                 128
#define SCPSC_PSSB_MASK                 31
#define SCPSC_PSSB_BITNUM               0
#define SCPSC_PDS_MASK                  224
#define SCPSC_PDS_BITNUM                5


/*** SCIACTL - ESCI Arbiter Control Register; 0x0000000A ***/
typedef union {
  byte Byte;
  struct {
    byte ARD8        :1;                                       /* Arbiter Counter MSB */
    byte AROVFL      :1;                                       /* Arbiter Counter Overflow Bit */
    byte ARUN        :1;                                       /* Arbiter Counter Running Flag */
    byte AFIN        :1;                                       /* Arbiter Bit Time Measurement Finish Flag */
    byte ACLK        :1;                                       /* Arbiter Counter Clock Select Bit */
    byte AM0         :1;                                       /* Arbiter Mode Select Bit 0 */
    byte ALOST       :1;                                       /* Arbitration Lost Flag */
    byte AM1         :1;                                       /* Arbiter Mode Select Bit 1 */
  } Bits;
} SCIACTLSTR;
extern volatile SCIACTLSTR _SCIACTL;
#define SCIACTL                         _SCIACTL.Byte
#define SCIACTL_ARD8                    _SCIACTL.Bits.ARD8
#define SCIACTL_AROVFL                  _SCIACTL.Bits.AROVFL
#define SCIACTL_ARUN                    _SCIACTL.Bits.ARUN
#define SCIACTL_AFIN                    _SCIACTL.Bits.AFIN
#define SCIACTL_ACLK                    _SCIACTL.Bits.ACLK
#define SCIACTL_AM0                     _SCIACTL.Bits.AM0
#define SCIACTL_ALOST                   _SCIACTL.Bits.ALOST
#define SCIACTL_AM1                     _SCIACTL.Bits.AM1

#define SCIACTL_ARD8_MASK               1
#define SCIACTL_AROVFL_MASK             2
#define SCIACTL_ARUN_MASK               4
#define SCIACTL_AFIN_MASK               8
#define SCIACTL_ACLK_MASK               16
#define SCIACTL_AM0_MASK                32
#define SCIACTL_ALOST_MASK              64
#define SCIACTL_AM1_MASK                128


/*** SCIADAT - ESCI Arbiter Data Register; 0x0000000B ***/
typedef union {
  byte Byte;
  struct {
    byte ARD0        :1;                                       /* Arbiter Least Significant Counter Bit 0 */
    byte ARD1        :1;                                       /* Arbiter Least Significant Counter Bit 1 */
    byte ARD2        :1;                                       /* Arbiter Least Significant Counter Bit 2 */
    byte ARD3        :1;                                       /* Arbiter Least Significant Counter Bit 3 */
    byte ARD4        :1;                                       /* Arbiter Least Significant Counter Bit 4 */
    byte ARD5        :1;                                       /* Arbiter Least Significant Counter Bit 5 */
    byte ARD6        :1;                                       /* Arbiter Least Significant Counter Bit 6 */
    byte ARD7        :1;                                       /* Arbiter Least Significant Counter Bit 7 */
  } Bits;
} SCIADATSTR;
extern volatile SCIADATSTR _SCIADAT;
#define SCIADAT                         _SCIADAT.Byte
#define SCIADAT_ARD0                    _SCIADAT.Bits.ARD0
#define SCIADAT_ARD1                    _SCIADAT.Bits.ARD1
#define SCIADAT_ARD2                    _SCIADAT.Bits.ARD2
#define SCIADAT_ARD3                    _SCIADAT.Bits.ARD3
#define SCIADAT_ARD4                    _SCIADAT.Bits.ARD4
#define SCIADAT_ARD5                    _SCIADAT.Bits.ARD5
#define SCIADAT_ARD6                    _SCIADAT.Bits.ARD6
#define SCIADAT_ARD7                    _SCIADAT.Bits.ARD7

#define SCIADAT_ARD0_MASK               1
#define SCIADAT_ARD1_MASK               2
#define SCIADAT_ARD2_MASK               4
#define SCIADAT_ARD3_MASK               8
#define SCIADAT_ARD4_MASK               16
#define SCIADAT_ARD5_MASK               32
#define SCIADAT_ARD6_MASK               64
#define SCIADAT_ARD7_MASK               128


/*** DDRE - Data Direction Register E; 0x0000000C ***/
typedef union {
  byte Byte;
  struct {
    byte DDRE0       :1;                                       /* Data Direction Register E Bit 0 */
    byte DDRE1       :1;                                       /* Data Direction Register E Bit 1 */
    byte DDRE2       :1;                                       /* Data Direction Register E Bit 2 */
    byte DDRE3       :1;                                       /* Data Direction Register E Bit 3 */
    byte DDRE4       :1;                                       /* Data Direction Register E Bit 4 */
    byte DDRE5       :1;                                       /* Data Direction Register E Bit 5 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDDRE :6;
    byte         :1;
    byte         :1;
  } MergedBits;
} DDRESTR;
extern volatile DDRESTR _DDRE;
#define DDRE                            _DDRE.Byte
#define DDRE_DDRE0                      _DDRE.Bits.DDRE0
#define DDRE_DDRE1                      _DDRE.Bits.DDRE1
#define DDRE_DDRE2                      _DDRE.Bits.DDRE2
#define DDRE_DDRE3                      _DDRE.Bits.DDRE3
#define DDRE_DDRE4                      _DDRE.Bits.DDRE4
#define DDRE_DDRE5                      _DDRE.Bits.DDRE5
#define DDRE_DDRE                       _DDRE.MergedBits.grpDDRE

#define DDRE_DDRE0_MASK                 1
#define DDRE_DDRE1_MASK                 2
#define DDRE_DDRE2_MASK                 4
#define DDRE_DDRE3_MASK                 8
#define DDRE_DDRE4_MASK                 16
#define DDRE_DDRE5_MASK                 32
#define DDRE_DDRE_MASK                  63
#define DDRE_DDRE_BITNUM                0


/*** PTAPUE - Port A Input Pullup Enable Register; 0x0000000D ***/
typedef union {
  byte Byte;
  struct {
    byte PTAPUE0     :1;                                       /* Port A Input Pullup Enable Bit 0 */
    byte PTAPUE1     :1;                                       /* Port A Input Pullup Enable Bit 1 */
    byte PTAPUE2     :1;                                       /* Port A Input Pullup Enable Bit 2 */
    byte PTAPUE3     :1;                                       /* Port A Input Pullup Enable Bit 3 */
    byte PTAPUE4     :1;                                       /* Port A Input Pullup Enable Bit 4 */
    byte PTAPUE5     :1;                                       /* Port A Input Pullup Enable Bit 5 */
    byte PTAPUE6     :1;                                       /* Port A Input Pullup Enable Bit 6 */
    byte PTAPUE7     :1;                                       /* Port A Input Pullup Enable Bit 7 */
  } Bits;
} PTAPUESTR;
extern volatile PTAPUESTR _PTAPUE;
#define PTAPUE                          _PTAPUE.Byte
#define PTAPUE_PTAPUE0                  _PTAPUE.Bits.PTAPUE0
#define PTAPUE_PTAPUE1                  _PTAPUE.Bits.PTAPUE1
#define PTAPUE_PTAPUE2                  _PTAPUE.Bits.PTAPUE2
#define PTAPUE_PTAPUE3                  _PTAPUE.Bits.PTAPUE3
#define PTAPUE_PTAPUE4                  _PTAPUE.Bits.PTAPUE4
#define PTAPUE_PTAPUE5                  _PTAPUE.Bits.PTAPUE5
#define PTAPUE_PTAPUE6                  _PTAPUE.Bits.PTAPUE6
#define PTAPUE_PTAPUE7                  _PTAPUE.Bits.PTAPUE7

#define PTAPUE_PTAPUE0_MASK             1
#define PTAPUE_PTAPUE1_MASK             2
#define PTAPUE_PTAPUE2_MASK             4
#define PTAPUE_PTAPUE3_MASK             8
#define PTAPUE_PTAPUE4_MASK             16
#define PTAPUE_PTAPUE5_MASK             32
#define PTAPUE_PTAPUE6_MASK             64
#define PTAPUE_PTAPUE7_MASK             128


/*** PTCPUE - Port C Input Pullup Enable Register; 0x0000000E ***/
typedef union {
  byte Byte;
  struct {
    byte PTCPUE0     :1;                                       /* Port C Input Pullup Enable Bit 0 */
    byte PTCPUE1     :1;                                       /* Port C Input Pullup Enable Bit 1 */
    byte PTCPUE2     :1;                                       /* Port C Input Pullup Enable Bit 2 */
    byte PTCPUE3     :1;                                       /* Port C Input Pullup Enable Bit 3 */
    byte PTCPUE4     :1;                                       /* Port C Input Pullup Enable Bit 4 */
    byte PTCPUE5     :1;                                       /* Port C Input Pullup Enable Bit 5 */
    byte PTCPUE6     :1;                                       /* Port C Input Pullup Enable Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpPTCPUE :7;
    byte         :1;
  } MergedBits;
} PTCPUESTR;
extern volatile PTCPUESTR _PTCPUE;
#define PTCPUE                          _PTCPUE.Byte
#define PTCPUE_PTCPUE0                  _PTCPUE.Bits.PTCPUE0
#define PTCPUE_PTCPUE1                  _PTCPUE.Bits.PTCPUE1
#define PTCPUE_PTCPUE2                  _PTCPUE.Bits.PTCPUE2
#define PTCPUE_PTCPUE3                  _PTCPUE.Bits.PTCPUE3
#define PTCPUE_PTCPUE4                  _PTCPUE.Bits.PTCPUE4
#define PTCPUE_PTCPUE5                  _PTCPUE.Bits.PTCPUE5
#define PTCPUE_PTCPUE6                  _PTCPUE.Bits.PTCPUE6
#define PTCPUE_PTCPUE                   _PTCPUE.MergedBits.grpPTCPUE

#define PTCPUE_PTCPUE0_MASK             1
#define PTCPUE_PTCPUE1_MASK             2
#define PTCPUE_PTCPUE2_MASK             4
#define PTCPUE_PTCPUE3_MASK             8
#define PTCPUE_PTCPUE4_MASK             16
#define PTCPUE_PTCPUE5_MASK             32
#define PTCPUE_PTCPUE6_MASK             64
#define PTCPUE_PTCPUE_MASK              127
#define PTCPUE_PTCPUE_BITNUM            0


/*** PTDPUE - Port D Input Pullup Enable Register; 0x0000000F ***/
typedef union {
  byte Byte;
  struct {
    byte PTDPUE0     :1;                                       /* Port D Input Pullup Enable Bit 0 */
    byte PTDPUE1     :1;                                       /* Port D Input Pullup Enable Bit 1 */
    byte PTDPUE2     :1;                                       /* Port D Input Pullup Enable Bit 2 */
    byte PTDPUE3     :1;                                       /* Port D Input Pullup Enable Bit 3 */
    byte PTDPUE4     :1;                                       /* Port D Input Pullup Enable Bit 4 */
    byte PTDPUE5     :1;                                       /* Port D Input Pullup Enable Bit 5 */
    byte PTDPUE6     :1;                                       /* Port D Input Pullup Enable Bit 6 */
    byte PTDPUE7     :1;                                       /* Port D Input Pullup Enable Bit 7 */
  } Bits;
} PTDPUESTR;
extern volatile PTDPUESTR _PTDPUE;
#define PTDPUE                          _PTDPUE.Byte
#define PTDPUE_PTDPUE0                  _PTDPUE.Bits.PTDPUE0
#define PTDPUE_PTDPUE1                  _PTDPUE.Bits.PTDPUE1
#define PTDPUE_PTDPUE2                  _PTDPUE.Bits.PTDPUE2
#define PTDPUE_PTDPUE3                  _PTDPUE.Bits.PTDPUE3
#define PTDPUE_PTDPUE4                  _PTDPUE.Bits.PTDPUE4
#define PTDPUE_PTDPUE5                  _PTDPUE.Bits.PTDPUE5
#define PTDPUE_PTDPUE6                  _PTDPUE.Bits.PTDPUE6
#define PTDPUE_PTDPUE7                  _PTDPUE.Bits.PTDPUE7

#define PTDPUE_PTDPUE0_MASK             1
#define PTDPUE_PTDPUE1_MASK             2
#define PTDPUE_PTDPUE2_MASK             4
#define PTDPUE_PTDPUE3_MASK             8
#define PTDPUE_PTDPUE4_MASK             16
#define PTDPUE_PTDPUE5_MASK             32
#define PTDPUE_PTDPUE6_MASK             64
#define PTDPUE_PTDPUE7_MASK             128


/*** SPCR - SPI Control Register; 0x00000010 ***/
typedef union {
  byte Byte;
  struct {
    byte SPTIE       :1;                                       /* SPI Transmit Interrupt Enable Bit */
    byte SPE         :1;                                       /* SPI Enable Bit */
    byte SPWOM       :1;                                       /* SPI Wired-OR Mode Bit */
    byte CPHA        :1;                                       /* Clock Phase Bit */
    byte CPOL        :1;                                       /* Clock Polarity Bit */
    byte SPMSTR      :1;                                       /* SPI Master Bit */
    byte             :1; 
    byte SPRIE       :1;                                       /* SPI Receiver Interrupt Enable Bit */
  } Bits;
} SPCRSTR;
extern volatile SPCRSTR _SPCR;
#define SPCR                            _SPCR.Byte
#define SPCR_SPTIE                      _SPCR.Bits.SPTIE
#define SPCR_SPE                        _SPCR.Bits.SPE
#define SPCR_SPWOM                      _SPCR.Bits.SPWOM
#define SPCR_CPHA                       _SPCR.Bits.CPHA
#define SPCR_CPOL                       _SPCR.Bits.CPOL
#define SPCR_SPMSTR                     _SPCR.Bits.SPMSTR
#define SPCR_SPRIE                      _SPCR.Bits.SPRIE

#define SPCR_SPTIE_MASK                 1
#define SPCR_SPE_MASK                   2
#define SPCR_SPWOM_MASK                 4
#define SPCR_CPHA_MASK                  8
#define SPCR_CPOL_MASK                  16
#define SPCR_SPMSTR_MASK                32
#define SPCR_SPRIE_MASK                 128


/*** SPSCR - SPI Status and Control Register; 0x00000011 ***/
typedef union {
  byte Byte;
  struct {
    byte SPR0        :1;                                       /* SPI Baud Rate Select Bit 0 */
    byte SPR1        :1;                                       /* SPI Baud Rate Select Bit 1 */
    byte MODFEN      :1;                                       /* Mode Fault Enable Bit */
    byte SPTE        :1;                                       /* SPI Transmitter Empty Bit */
    byte MODF        :1;                                       /* Mode Fault Bit */
    byte OVRF        :1;                                       /* Overflow Bit */
    byte ERRIE       :1;                                       /* Error Interrupt Enable Bit */
    byte SPRF        :1;                                       /* SPI Receiver Full Bit */
  } Bits;
  struct {
    byte grpSPR  :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} SPSCRSTR;
extern volatile SPSCRSTR _SPSCR;
#define SPSCR                           _SPSCR.Byte
#define SPSCR_SPR0                      _SPSCR.Bits.SPR0
#define SPSCR_SPR1                      _SPSCR.Bits.SPR1
#define SPSCR_MODFEN                    _SPSCR.Bits.MODFEN
#define SPSCR_SPTE                      _SPSCR.Bits.SPTE
#define SPSCR_MODF                      _SPSCR.Bits.MODF
#define SPSCR_OVRF                      _SPSCR.Bits.OVRF
#define SPSCR_ERRIE                     _SPSCR.Bits.ERRIE
#define SPSCR_SPRF                      _SPSCR.Bits.SPRF
#define SPSCR_SPR                       _SPSCR.MergedBits.grpSPR

#define SPSCR_SPR0_MASK                 1
#define SPSCR_SPR1_MASK                 2
#define SPSCR_MODFEN_MASK               4
#define SPSCR_SPTE_MASK                 8
#define SPSCR_MODF_MASK                 16
#define SPSCR_OVRF_MASK                 32
#define SPSCR_ERRIE_MASK                64
#define SPSCR_SPRF_MASK                 128
#define SPSCR_SPR_MASK                  3
#define SPSCR_SPR_BITNUM                0


/*** SPDR - SPI Data Register; 0x00000012 ***/
typedef union {
  byte Byte;
  struct {
    byte R0_T0       :1;                                       /* Receive/Transmit Data Bit 0 */
    byte R1_T1       :1;                                       /* Receive/Transmit Data Bit 1 */
    byte R2_T2       :1;                                       /* Receive/Transmit Data Bit 2 */
    byte R3_T3       :1;                                       /* Receive/Transmit Data Bit 3 */
    byte R4_T4       :1;                                       /* Receive/Transmit Data Bit 4 */
    byte R5_T5       :1;                                       /* Receive/Transmit Data Bit 5 */
    byte R6_T6       :1;                                       /* Receive/Transmit Data Bit 6 */
    byte R7_T7       :1;                                       /* Receive/Transmit Data Bit 7 */
  } Bits;
} SPDRSTR;
extern volatile SPDRSTR _SPDR;
#define SPDR                            _SPDR.Byte
#define SPDR_R0_T0                      _SPDR.Bits.R0_T0
#define SPDR_R1_T1                      _SPDR.Bits.R1_T1
#define SPDR_R2_T2                      _SPDR.Bits.R2_T2
#define SPDR_R3_T3                      _SPDR.Bits.R3_T3
#define SPDR_R4_T4                      _SPDR.Bits.R4_T4
#define SPDR_R5_T5                      _SPDR.Bits.R5_T5
#define SPDR_R6_T6                      _SPDR.Bits.R6_T6
#define SPDR_R7_T7                      _SPDR.Bits.R7_T7

#define SPDR_R0_T0_MASK                 1
#define SPDR_R1_T1_MASK                 2
#define SPDR_R2_T2_MASK                 4
#define SPDR_R3_T3_MASK                 8
#define SPDR_R4_T4_MASK                 16
#define SPDR_R5_T5_MASK                 32
#define SPDR_R6_T6_MASK                 64
#define SPDR_R7_T7_MASK                 128


/*** SCC1 - ESCI Control Register 1; 0x00000013 ***/
typedef union {
  byte Byte;
  struct {
    byte PTY         :1;                                       /* Parity Bit */
    byte PEN         :1;                                       /* Parity Enable Bit */
    byte ILTY        :1;                                       /* Idle Line Type Bit */
    byte WAKE        :1;                                       /* Wakeup Condition Bit */
    byte M           :1;                                       /* Mode (Character Length) Bit */
    byte TXINV       :1;                                       /* Transmit Inversion Bit */
    byte ENSCI       :1;                                       /* Enable ESCI Bit */
    byte LOOPS       :1;                                       /* Loop Mode Select Bit */
  } Bits;
} SCC1STR;
extern volatile SCC1STR _SCC1;
#define SCC1                            _SCC1.Byte
#define SCC1_PTY                        _SCC1.Bits.PTY
#define SCC1_PEN                        _SCC1.Bits.PEN
#define SCC1_ILTY                       _SCC1.Bits.ILTY
#define SCC1_WAKE                       _SCC1.Bits.WAKE
#define SCC1_M                          _SCC1.Bits.M
#define SCC1_TXINV                      _SCC1.Bits.TXINV
#define SCC1_ENSCI                      _SCC1.Bits.ENSCI
#define SCC1_LOOPS                      _SCC1.Bits.LOOPS

#define SCC1_PTY_MASK                   1
#define SCC1_PEN_MASK                   2
#define SCC1_ILTY_MASK                  4
#define SCC1_WAKE_MASK                  8
#define SCC1_M_MASK                     16
#define SCC1_TXINV_MASK                 32
#define SCC1_ENSCI_MASK                 64
#define SCC1_LOOPS_MASK                 128


/*** SCC2 - ESCI Control Register 2; 0x00000014 ***/
typedef union {
  byte Byte;
  struct {
    byte SBK         :1;                                       /* Send Break Bit */
    byte RWU         :1;                                       /* Receiver Wakeup Bit */
    byte RE          :1;                                       /* Receiver Enable Bit */
    byte TE          :1;                                       /* Transmitter Enable Bit */
    byte ILIE        :1;                                       /* Idle Line Interrupt Enable Bit */
    byte SCRIE       :1;                                       /* ESCI Receive Interrupt Enable Bit */
    byte TCIE        :1;                                       /* Transmission Complete Interrupt Enable Bit */
    byte SCTIE       :1;                                       /* ESCI Transmit Interrupt Enable Bit */
  } Bits;
} SCC2STR;
extern volatile SCC2STR _SCC2;
#define SCC2                            _SCC2.Byte
#define SCC2_SBK                        _SCC2.Bits.SBK
#define SCC2_RWU                        _SCC2.Bits.RWU
#define SCC2_RE                         _SCC2.Bits.RE
#define SCC2_TE                         _SCC2.Bits.TE
#define SCC2_ILIE                       _SCC2.Bits.ILIE
#define SCC2_SCRIE                      _SCC2.Bits.SCRIE
#define SCC2_TCIE                       _SCC2.Bits.TCIE
#define SCC2_SCTIE                      _SCC2.Bits.SCTIE

#define SCC2_SBK_MASK                   1
#define SCC2_RWU_MASK                   2
#define SCC2_RE_MASK                    4
#define SCC2_TE_MASK                    8
#define SCC2_ILIE_MASK                  16
#define SCC2_SCRIE_MASK                 32
#define SCC2_TCIE_MASK                  64
#define SCC2_SCTIE_MASK                 128


/*** SCC3 - ESCI Control Register 3; 0x00000015 ***/
typedef union {
  byte Byte;
  struct {
    byte PEIE        :1;                                       /* Receiver Parity Error Interrupt Enable Bit */
    byte FEIE        :1;                                       /* Receiver Framing Error Interrupt Enable Bit */
    byte NEIE        :1;                                       /* Receiver Noise Error Interrupt Enable Bit */
    byte ORIE        :1;                                       /* Receiver Overrun Interrupt Enable Bit */
    byte             :1; 
    byte             :1; 
    byte T8          :1;                                       /* Transmitted Bit 8 */
    byte R8          :1;                                       /* Received Bit 8 */
  } Bits;
} SCC3STR;
extern volatile SCC3STR _SCC3;
#define SCC3                            _SCC3.Byte
#define SCC3_PEIE                       _SCC3.Bits.PEIE
#define SCC3_FEIE                       _SCC3.Bits.FEIE
#define SCC3_NEIE                       _SCC3.Bits.NEIE
#define SCC3_ORIE                       _SCC3.Bits.ORIE
#define SCC3_T8                         _SCC3.Bits.T8
#define SCC3_R8                         _SCC3.Bits.R8

#define SCC3_PEIE_MASK                  1
#define SCC3_FEIE_MASK                  2
#define SCC3_NEIE_MASK                  4
#define SCC3_ORIE_MASK                  8
#define SCC3_T8_MASK                    64
#define SCC3_R8_MASK                    128


/*** SCS1 - ESCI Status Register 1; 0x00000016 ***/
typedef union {
  byte Byte;
  struct {
    byte PE          :1;                                       /* Receiver Parity Error Bit */
    byte FE          :1;                                       /* Receiver Framing Error Bit */
    byte NF          :1;                                       /* Receiver Noise Flag Bit */
    byte OR          :1;                                       /* Receiver Overrun Bit */
    byte IDLE        :1;                                       /* Receiver Idle Bit */
    byte SCRF        :1;                                       /* SCI Receiver Full Bit */
    byte TC          :1;                                       /* Transmission Complete Bit */
    byte SCTE        :1;                                       /* SCI Transmitter Empty Bit */
  } Bits;
} SCS1STR;
extern volatile SCS1STR _SCS1;
#define SCS1                            _SCS1.Byte
#define SCS1_PE                         _SCS1.Bits.PE
#define SCS1_FE                         _SCS1.Bits.FE
#define SCS1_NF                         _SCS1.Bits.NF
#define SCS1_OR                         _SCS1.Bits.OR
#define SCS1_IDLE                       _SCS1.Bits.IDLE
#define SCS1_SCRF                       _SCS1.Bits.SCRF
#define SCS1_TC                         _SCS1.Bits.TC
#define SCS1_SCTE                       _SCS1.Bits.SCTE

#define SCS1_PE_MASK                    1
#define SCS1_FE_MASK                    2
#define SCS1_NF_MASK                    4
#define SCS1_OR_MASK                    8
#define SCS1_IDLE_MASK                  16
#define SCS1_SCRF_MASK                  32
#define SCS1_TC_MASK                    64
#define SCS1_SCTE_MASK                  128


/*** SCS2 - ESCI Status Register 2; 0x00000017 ***/
typedef union {
  byte Byte;
  struct {
    byte RPF         :1;                                       /* Reception in Progress Flag Bit */
    byte BKF         :1;                                       /* Break Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SCS2STR;
extern volatile SCS2STR _SCS2;
#define SCS2                            _SCS2.Byte
#define SCS2_RPF                        _SCS2.Bits.RPF
#define SCS2_BKF                        _SCS2.Bits.BKF

#define SCS2_RPF_MASK                   1
#define SCS2_BKF_MASK                   2


/*** SCDR - ESCI Data Register; 0x00000018 ***/
typedef union {
  byte Byte;
  struct {
    byte R0_T0       :1;                                       /* Receive/Transmit Data Bit 0 */
    byte R1_T1       :1;                                       /* Receive/Transmit Data Bit 1 */
    byte R2_T2       :1;                                       /* Receive/Transmit Data Bit 2 */
    byte R3_T3       :1;                                       /* Receive/Transmit Data Bit 3 */
    byte R4_T4       :1;                                       /* Receive/Transmit Data Bit 4 */
    byte R5_T5       :1;                                       /* Receive/Transmit Data Bit 5 */
    byte R6_T6       :1;                                       /* Receive/Transmit Data Bit 6 */
    byte R7_T7       :1;                                       /* Receive/Transmit Data Bit 7 */
  } Bits;
} SCDRSTR;
extern volatile SCDRSTR _SCDR;
#define SCDR                            _SCDR.Byte
#define SCDR_R0_T0                      _SCDR.Bits.R0_T0
#define SCDR_R1_T1                      _SCDR.Bits.R1_T1
#define SCDR_R2_T2                      _SCDR.Bits.R2_T2
#define SCDR_R3_T3                      _SCDR.Bits.R3_T3
#define SCDR_R4_T4                      _SCDR.Bits.R4_T4
#define SCDR_R5_T5                      _SCDR.Bits.R5_T5
#define SCDR_R6_T6                      _SCDR.Bits.R6_T6
#define SCDR_R7_T7                      _SCDR.Bits.R7_T7

#define SCDR_R0_T0_MASK                 1
#define SCDR_R1_T1_MASK                 2
#define SCDR_R2_T2_MASK                 4
#define SCDR_R3_T3_MASK                 8
#define SCDR_R4_T4_MASK                 16
#define SCDR_R5_T5_MASK                 32
#define SCDR_R6_T6_MASK                 64
#define SCDR_R7_T7_MASK                 128


/*** SCBR - ESCI Baud Rate Register; 0x00000019 ***/
typedef union {
  byte Byte;
  struct {
    byte SCR0        :1;                                       /* ESCI Baud Rate Select Bit 0 */
    byte SCR1        :1;                                       /* ESCI Baud Rate Select Bit 1 */
    byte SCR2        :1;                                       /* ESCI Baud Rate Select Bit 2 */
    byte             :1; 
    byte SCP0        :1;                                       /* ESCI Baud Rate Prescaler Bit 0 */
    byte SCP1        :1;                                       /* ESCI Baud Rate Prescaler Bit 1 */
    byte LINR        :1;                                       /* LIN Break Symbol Receiver Bit */
    byte LINT        :1;                                       /* LIN Breal Symbol Transmit Enable */
  } Bits;
  struct {
    byte grpSCR  :3;
    byte         :1;
    byte grpSCP  :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} SCBRSTR;
extern volatile SCBRSTR _SCBR;
#define SCBR                            _SCBR.Byte
#define SCBR_SCR0                       _SCBR.Bits.SCR0
#define SCBR_SCR1                       _SCBR.Bits.SCR1
#define SCBR_SCR2                       _SCBR.Bits.SCR2
#define SCBR_SCP0                       _SCBR.Bits.SCP0
#define SCBR_SCP1                       _SCBR.Bits.SCP1
#define SCBR_LINR                       _SCBR.Bits.LINR
#define SCBR_LINT                       _SCBR.Bits.LINT
#define SCBR_SCR                        _SCBR.MergedBits.grpSCR
#define SCBR_SCP                        _SCBR.MergedBits.grpSCP

#define SCBR_SCR0_MASK                  1
#define SCBR_SCR1_MASK                  2
#define SCBR_SCR2_MASK                  4
#define SCBR_SCP0_MASK                  16
#define SCBR_SCP1_MASK                  32
#define SCBR_LINR_MASK                  64
#define SCBR_LINT_MASK                  128
#define SCBR_SCR_MASK                   7
#define SCBR_SCR_BITNUM                 0
#define SCBR_SCP_MASK                   48
#define SCBR_SCP_BITNUM                 4


/*** INTKBSCR - Keyboard Status and Control Register; 0x0000001A ***/
typedef union {
  byte Byte;
  struct {
    byte MODEK       :1;                                       /* Keyboard Triggering Sensitivity Bit */
    byte IMASKK      :1;                                       /* Keyboard Interrupt Mask Bit */
    byte ACKK        :1;                                       /* Keyboard Acknowledge Bit */
    byte KEYF        :1;                                       /* Keyboard Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} INTKBSCRSTR;
extern volatile INTKBSCRSTR _INTKBSCR;
#define INTKBSCR                        _INTKBSCR.Byte
#define INTKBSCR_MODEK                  _INTKBSCR.Bits.MODEK
#define INTKBSCR_IMASKK                 _INTKBSCR.Bits.IMASKK
#define INTKBSCR_ACKK                   _INTKBSCR.Bits.ACKK
#define INTKBSCR_KEYF                   _INTKBSCR.Bits.KEYF

#define INTKBSCR_MODEK_MASK             1
#define INTKBSCR_IMASKK_MASK            2
#define INTKBSCR_ACKK_MASK              4
#define INTKBSCR_KEYF_MASK              8


/*** INTKBIER - Keyboard Interrupt Enable Register; 0x0000001B ***/
typedef union {
  byte Byte;
  struct {
    byte KBIE0       :1;                                       /* Keyboard Interrupt Enable Bit 0 */
    byte KBIE1       :1;                                       /* Keyboard Interrupt Enable Bit 1 */
    byte KBIE2       :1;                                       /* Keyboard Interrupt Enable Bit 2 */
    byte KBIE3       :1;                                       /* Keyboard Interrupt Enable Bit 3 */
    byte KBIE4       :1;                                       /* Keyboard Interrupt Enable Bit 4 */
    byte KBIE5       :1;                                       /* Keyboard Interrupt Enable Bit 5 */
    byte KBIE6       :1;                                       /* Keyboard Interrupt Enable Bit 6 */
    byte KBIE7       :1;                                       /* Keyboard Interrupt Enable Bit 7 */
  } Bits;
} INTKBIERSTR;
extern volatile INTKBIERSTR _INTKBIER;
#define INTKBIER                        _INTKBIER.Byte
#define INTKBIER_KBIE0                  _INTKBIER.Bits.KBIE0
#define INTKBIER_KBIE1                  _INTKBIER.Bits.KBIE1
#define INTKBIER_KBIE2                  _INTKBIER.Bits.KBIE2
#define INTKBIER_KBIE3                  _INTKBIER.Bits.KBIE3
#define INTKBIER_KBIE4                  _INTKBIER.Bits.KBIE4
#define INTKBIER_KBIE5                  _INTKBIER.Bits.KBIE5
#define INTKBIER_KBIE6                  _INTKBIER.Bits.KBIE6
#define INTKBIER_KBIE7                  _INTKBIER.Bits.KBIE7

#define INTKBIER_KBIE0_MASK             1
#define INTKBIER_KBIE1_MASK             2
#define INTKBIER_KBIE2_MASK             4
#define INTKBIER_KBIE3_MASK             8
#define INTKBIER_KBIE4_MASK             16
#define INTKBIER_KBIE5_MASK             32
#define INTKBIER_KBIE6_MASK             64
#define INTKBIER_KBIE7_MASK             128


/*** TBCR - Timebase Control Register; 0x0000001C ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte TBON        :1;                                       /* Timebase Enabled */
    byte TBIE        :1;                                       /* Timebase Interrupt Enable */
    byte TACK        :1;                                       /* Timebase ACKnowledge */
    byte TBR0        :1;                                       /* Timebase Rate Selection Bit 0 */
    byte TBR1        :1;                                       /* Timebase Rate Selection Bit 1 */
    byte TBR2        :1;                                       /* Timebase Rate Selection Bit2 */
    byte TBIF        :1;                                       /* Timebase Interrupt Flag */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpTBR  :3;
    byte         :1;
  } MergedBits;
} TBCRSTR;
extern volatile TBCRSTR _TBCR;
#define TBCR                            _TBCR.Byte
#define TBCR_TBON                       _TBCR.Bits.TBON
#define TBCR_TBIE                       _TBCR.Bits.TBIE
#define TBCR_TACK                       _TBCR.Bits.TACK
#define TBCR_TBR0                       _TBCR.Bits.TBR0
#define TBCR_TBR1                       _TBCR.Bits.TBR1
#define TBCR_TBR2                       _TBCR.Bits.TBR2
#define TBCR_TBIF                       _TBCR.Bits.TBIF
#define TBCR_TBR                        _TBCR.MergedBits.grpTBR

#define TBCR_TBON_MASK                  2
#define TBCR_TBIE_MASK                  4
#define TBCR_TACK_MASK                  8
#define TBCR_TBR0_MASK                  16
#define TBCR_TBR1_MASK                  32
#define TBCR_TBR2_MASK                  64
#define TBCR_TBIF_MASK                  128
#define TBCR_TBR_MASK                   112
#define TBCR_TBR_BITNUM                 4


/*** INTSCR - IRQ Status and Control Register; 0x0000001D ***/
typedef union {
  byte Byte;
  struct {
    byte MODE        :1;                                       /* IRQ Edge/Level Select Bit */
    byte IMASK       :1;                                       /* IRQ Interrupt Mask Bit */
    byte ACK         :1;                                       /* IRQ Interrupt Request Acknowledge Bit */
    byte IRQF        :1;                                       /* IRQ Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} INTSCRSTR;
extern volatile INTSCRSTR _INTSCR;
#define INTSCR                          _INTSCR.Byte
#define INTSCR_MODE                     _INTSCR.Bits.MODE
#define INTSCR_IMASK                    _INTSCR.Bits.IMASK
#define INTSCR_ACK                      _INTSCR.Bits.ACK
#define INTSCR_IRQF                     _INTSCR.Bits.IRQF

#define INTSCR_MODE_MASK                1
#define INTSCR_IMASK_MASK               2
#define INTSCR_ACK_MASK                 4
#define INTSCR_IRQF_MASK                8


/*** CONFIG2 - Configuration Register 2; 0x0000001E ***/
typedef union {
  byte Byte;
  struct {
    byte SCIBDSRC    :1;                                       /* ESCI Baud Rate Clock Source Bit */
    byte OSCENINSTOP :1;                                       /* Oscillator Enable In Stop Mode Bit */
    byte TMBCLKSEL   :1;                                       /* Timebase Clock Select Bit */
    byte             :1; 
    byte MCLK0       :1;                                       /* MCLK Output Select Bit 0 */
    byte MCLK1       :1;                                       /* MCLK Output Select Bit 1 */
    byte MCLKSEL     :1;                                       /* MCLK Source Select Bit */
    byte             :1; 
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpMCLK :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CONFIG2STR;
extern volatile CONFIG2STR _CONFIG2;
#define CONFIG2                         _CONFIG2.Byte
#define CONFIG2_SCIBDSRC                _CONFIG2.Bits.SCIBDSRC
#define CONFIG2_OSCENINSTOP             _CONFIG2.Bits.OSCENINSTOP
#define CONFIG2_TMBCLKSEL               _CONFIG2.Bits.TMBCLKSEL
#define CONFIG2_MCLK0                   _CONFIG2.Bits.MCLK0
#define CONFIG2_MCLK1                   _CONFIG2.Bits.MCLK1
#define CONFIG2_MCLKSEL                 _CONFIG2.Bits.MCLKSEL
#define CONFIG2_MCLK                    _CONFIG2.MergedBits.grpMCLK

#define CONFIG2_SCIBDSRC_MASK           1
#define CONFIG2_OSCENINSTOP_MASK        2
#define CONFIG2_TMBCLKSEL_MASK          4
#define CONFIG2_MCLK0_MASK              16
#define CONFIG2_MCLK1_MASK              32
#define CONFIG2_MCLKSEL_MASK            64
#define CONFIG2_MCLK_MASK               48
#define CONFIG2_MCLK_BITNUM             4


/*** CONFIG1 - Configuration Register; 0x0000001F ***/
typedef union {
  byte Byte;
  struct {
    byte COPD        :1;                                       /* COP Disable Bit */
    byte STOP        :1;                                       /* STOP Instruction Enable Bit */
    byte SSREC       :1;                                       /* Short Stop Recovery Bit */
    byte LVI5OR3     :1;                                       /* LVI 5-V or 3-V Operating Mode Bit */
    byte LVIPWRD     :1;                                       /* LVI Power Disable Bit */
    byte LVIRSTD     :1;                                       /* LVI Reset Disable Bit */
    byte LVISTOP     :1;                                       /* LVI Enable in Stop Mode Bit */
    byte COPRS       :1;                                       /* COP Rate Select Bit */
  } Bits;
} CONFIG1STR;
extern volatile CONFIG1STR _CONFIG1;
#define CONFIG1                         _CONFIG1.Byte
#define CONFIG1_COPD                    _CONFIG1.Bits.COPD
#define CONFIG1_STOP                    _CONFIG1.Bits.STOP
#define CONFIG1_SSREC                   _CONFIG1.Bits.SSREC
#define CONFIG1_LVI5OR3                 _CONFIG1.Bits.LVI5OR3
#define CONFIG1_LVIPWRD                 _CONFIG1.Bits.LVIPWRD
#define CONFIG1_LVIRSTD                 _CONFIG1.Bits.LVIRSTD
#define CONFIG1_LVISTOP                 _CONFIG1.Bits.LVISTOP
#define CONFIG1_COPRS                   _CONFIG1.Bits.COPRS

#define CONFIG1_COPD_MASK               1
#define CONFIG1_STOP_MASK               2
#define CONFIG1_SSREC_MASK              4
#define CONFIG1_LVI5OR3_MASK            8
#define CONFIG1_LVIPWRD_MASK            16
#define CONFIG1_LVIRSTD_MASK            32
#define CONFIG1_LVISTOP_MASK            64
#define CONFIG1_COPRS_MASK              128


/*** T1SC - TIM1 Status and Control Register; 0x00000020 ***/
typedef union {
  byte Byte;
  struct {
    byte PS0         :1;                                       /* Prescaler Select Bit 0 */
    byte PS1         :1;                                       /* Prescaler Select Bit 1 */
    byte PS2         :1;                                       /* Prescaler Select Bit 2 */
    byte             :1; 
    byte TRST        :1;                                       /* TIM1 Reset Bit */
    byte TSTOP       :1;                                       /* TIM1 Stop Bit */
    byte TOIE        :1;                                       /* TIM1 Overflow Interrupt Enable Bit */
    byte TOF         :1;                                       /* TIM1 Overflow Flag Bit */
  } Bits;
  struct {
    byte grpPS   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} T1SCSTR;
extern volatile T1SCSTR _T1SC;
#define T1SC                            _T1SC.Byte
#define T1SC_PS0                        _T1SC.Bits.PS0
#define T1SC_PS1                        _T1SC.Bits.PS1
#define T1SC_PS2                        _T1SC.Bits.PS2
#define T1SC_TRST                       _T1SC.Bits.TRST
#define T1SC_TSTOP                      _T1SC.Bits.TSTOP
#define T1SC_TOIE                       _T1SC.Bits.TOIE
#define T1SC_TOF                        _T1SC.Bits.TOF
#define T1SC_PS                         _T1SC.MergedBits.grpPS

#define T1SC_PS0_MASK                   1
#define T1SC_PS1_MASK                   2
#define T1SC_PS2_MASK                   4
#define T1SC_TRST_MASK                  16
#define T1SC_TSTOP_MASK                 32
#define T1SC_TOIE_MASK                  64
#define T1SC_TOF_MASK                   128
#define T1SC_PS_MASK                    7
#define T1SC_PS_BITNUM                  0


/*** T1CNT - TIM1 Counter Register; 0x00000021 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T1CNTH - TIM1 Counter Register High; 0x00000021 ***/
    union {
      byte Byte;
    } T1CNTHSTR;
    #define T1CNTH                      _T1CNT.Overlap_STR.T1CNTHSTR.Byte
    

    /*** T1CNTL - TIM1 Counter Register Low; 0x00000022 ***/
    union {
      byte Byte;
    } T1CNTLSTR;
    #define T1CNTL                      _T1CNT.Overlap_STR.T1CNTLSTR.Byte
    
  } Overlap_STR;

} T1CNTSTR;
extern volatile T1CNTSTR _T1CNT;
#define T1CNT                           _T1CNT.Word


/*** T1MOD - TIM1 Counter Modulo Register; 0x00000023 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T1MODH - TIM1 Counter Modulo Register High; 0x00000023 ***/
    union {
      byte Byte;
    } T1MODHSTR;
    #define T1MODH                      _T1MOD.Overlap_STR.T1MODHSTR.Byte
    

    /*** T1MODL - TIM1 Counter Modulo Register Low; 0x00000024 ***/
    union {
      byte Byte;
    } T1MODLSTR;
    #define T1MODL                      _T1MOD.Overlap_STR.T1MODLSTR.Byte
    
  } Overlap_STR;

} T1MODSTR;
extern volatile T1MODSTR _T1MOD;
#define T1MOD                           _T1MOD.Word


/*** T1SC0 - TIM1 Channel 0 Status and Control Register; 0x00000025 ***/
typedef union {
  byte Byte;
  struct {
    byte CH0MAX      :1;                                       /* Channel 0 Maximum Duty Cycle Bit */
    byte TOV0        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS0A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS0B       :1;                                       /* Edge/Level Select Bit B */
    byte MS0A        :1;                                       /* Mode Select Bit A */
    byte MS0B        :1;                                       /* Mode Select Bit B */
    byte CH0IE       :1;                                       /* Channel 0 Interrupt Enable Bit */
    byte CH0F        :1;                                       /* Channel 0 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV  :1;
    byte grpELS0x :2;
    byte grpMS0x :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} T1SC0STR;
extern volatile T1SC0STR _T1SC0;
#define T1SC0                           _T1SC0.Byte
#define T1SC0_CH0MAX                    _T1SC0.Bits.CH0MAX
#define T1SC0_TOV0                      _T1SC0.Bits.TOV0
#define T1SC0_ELS0A                     _T1SC0.Bits.ELS0A
#define T1SC0_ELS0B                     _T1SC0.Bits.ELS0B
#define T1SC0_MS0A                      _T1SC0.Bits.MS0A
#define T1SC0_MS0B                      _T1SC0.Bits.MS0B
#define T1SC0_CH0IE                     _T1SC0.Bits.CH0IE
#define T1SC0_CH0F                      _T1SC0.Bits.CH0F
#define T1SC0_ELS0x                     _T1SC0.MergedBits.grpELS0x
#define T1SC0_MS0x                      _T1SC0.MergedBits.grpMS0x

#define T1SC0_CH0MAX_MASK               1
#define T1SC0_TOV0_MASK                 2
#define T1SC0_ELS0A_MASK                4
#define T1SC0_ELS0B_MASK                8
#define T1SC0_MS0A_MASK                 16
#define T1SC0_MS0B_MASK                 32
#define T1SC0_CH0IE_MASK                64
#define T1SC0_CH0F_MASK                 128
#define T1SC0_ELS0x_MASK                12
#define T1SC0_ELS0x_BITNUM              2
#define T1SC0_MS0x_MASK                 48
#define T1SC0_MS0x_BITNUM               4


/*** T1CH0 - TIM1 Channel 0 Register; 0x00000026 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T1CH0H - TIM1 Channel 0 Register High; 0x00000026 ***/
    union {
      byte Byte;
    } T1CH0HSTR;
    #define T1CH0H                      _T1CH0.Overlap_STR.T1CH0HSTR.Byte
    

    /*** T1CH0L - TIM1 Channel 0 Register Low; 0x00000027 ***/
    union {
      byte Byte;
    } T1CH0LSTR;
    #define T1CH0L                      _T1CH0.Overlap_STR.T1CH0LSTR.Byte
    
  } Overlap_STR;

} T1CH0STR;
extern volatile T1CH0STR _T1CH0;
#define T1CH0                           _T1CH0.Word


/*** T1SC1 - TIM1 Channel 1 Status and Control Register; 0x00000028 ***/
typedef union {
  byte Byte;
  struct {
    byte CH1MAX      :1;                                       /* Channel 1 Maximum Duty Cycle Bit */
    byte TOV1        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS1A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS1B       :1;                                       /* Edge/Level Select Bit B */
    byte MS1A        :1;                                       /* Mode Select Bit A */
    byte             :1; 
    byte CH1IE       :1;                                       /* Channel 1 Interrupt Enable Bit */
    byte CH1F        :1;                                       /* Channel 1 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_1 :1;
    byte grpELS1x :2;
    byte grpMS1x :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} T1SC1STR;
extern volatile T1SC1STR _T1SC1;
#define T1SC1                           _T1SC1.Byte
#define T1SC1_CH1MAX                    _T1SC1.Bits.CH1MAX
#define T1SC1_TOV1                      _T1SC1.Bits.TOV1
#define T1SC1_ELS1A                     _T1SC1.Bits.ELS1A
#define T1SC1_ELS1B                     _T1SC1.Bits.ELS1B
#define T1SC1_MS1A                      _T1SC1.Bits.MS1A
#define T1SC1_CH1IE                     _T1SC1.Bits.CH1IE
#define T1SC1_CH1F                      _T1SC1.Bits.CH1F
#define T1SC1_ELS1x                     _T1SC1.MergedBits.grpELS1x

#define T1SC1_CH1MAX_MASK               1
#define T1SC1_TOV1_MASK                 2
#define T1SC1_ELS1A_MASK                4
#define T1SC1_ELS1B_MASK                8
#define T1SC1_MS1A_MASK                 16
#define T1SC1_CH1IE_MASK                64
#define T1SC1_CH1F_MASK                 128
#define T1SC1_ELS1x_MASK                12
#define T1SC1_ELS1x_BITNUM              2


/*** T1CH1 - TIM1 Channel 1 Register; 0x00000029 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T1CH1H - TIM1 Channel 1 Register High; 0x00000029 ***/
    union {
      byte Byte;
    } T1CH1HSTR;
    #define T1CH1H                      _T1CH1.Overlap_STR.T1CH1HSTR.Byte
    

    /*** T1CH1L - TIM1 Channel 1 Register Low; 0x0000002A ***/
    union {
      byte Byte;
    } T1CH1LSTR;
    #define T1CH1L                      _T1CH1.Overlap_STR.T1CH1LSTR.Byte
    
  } Overlap_STR;

} T1CH1STR;
extern volatile T1CH1STR _T1CH1;
#define T1CH1                           _T1CH1.Word


/*** T2SC - TIM2 Status and Control Register; 0x0000002B ***/
typedef union {
  byte Byte;
  struct {
    byte PS0         :1;                                       /* Prescaler Select Bit 0 */
    byte PS1         :1;                                       /* Prescaler Select Bit 1 */
    byte PS2         :1;                                       /* Prescaler Select Bit 2 */
    byte             :1; 
    byte TRST        :1;                                       /* TIM2 Reset Bit */
    byte TSTOP       :1;                                       /* TIM2 Stop Bit */
    byte TOIE        :1;                                       /* TIM2 Overflow Interrupt Enable Bit */
    byte TOF         :1;                                       /* TIM2 Overflow Flag Bit */
  } Bits;
  struct {
    byte grpPS   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} T2SCSTR;
extern volatile T2SCSTR _T2SC;
#define T2SC                            _T2SC.Byte
#define T2SC_PS0                        _T2SC.Bits.PS0
#define T2SC_PS1                        _T2SC.Bits.PS1
#define T2SC_PS2                        _T2SC.Bits.PS2
#define T2SC_TRST                       _T2SC.Bits.TRST
#define T2SC_TSTOP                      _T2SC.Bits.TSTOP
#define T2SC_TOIE                       _T2SC.Bits.TOIE
#define T2SC_TOF                        _T2SC.Bits.TOF
#define T2SC_PS                         _T2SC.MergedBits.grpPS

#define T2SC_PS0_MASK                   1
#define T2SC_PS1_MASK                   2
#define T2SC_PS2_MASK                   4
#define T2SC_TRST_MASK                  16
#define T2SC_TSTOP_MASK                 32
#define T2SC_TOIE_MASK                  64
#define T2SC_TOF_MASK                   128
#define T2SC_PS_MASK                    7
#define T2SC_PS_BITNUM                  0


/*** T2CNT - TIM2 Counter Register; 0x0000002C ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T2CNTH - TIM2 Counter Register High; 0x0000002C ***/
    union {
      byte Byte;
    } T2CNTHSTR;
    #define T2CNTH                      _T2CNT.Overlap_STR.T2CNTHSTR.Byte
    

    /*** T2CNTL - TIM2 Counter Register Low; 0x0000002D ***/
    union {
      byte Byte;
    } T2CNTLSTR;
    #define T2CNTL                      _T2CNT.Overlap_STR.T2CNTLSTR.Byte
    
  } Overlap_STR;

} T2CNTSTR;
extern volatile T2CNTSTR _T2CNT;
#define T2CNT                           _T2CNT.Word


/*** T2MOD - TIM2 Counter Modulo Register; 0x0000002E ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T2MODH - TIM2 Counter Modulo Register High; 0x0000002E ***/
    union {
      byte Byte;
    } T2MODHSTR;
    #define T2MODH                      _T2MOD.Overlap_STR.T2MODHSTR.Byte
    

    /*** T2MODL - TIM2 Counter Modulo Register Low; 0x0000002F ***/
    union {
      byte Byte;
    } T2MODLSTR;
    #define T2MODL                      _T2MOD.Overlap_STR.T2MODLSTR.Byte
    
  } Overlap_STR;

} T2MODSTR;
extern volatile T2MODSTR _T2MOD;
#define T2MOD                           _T2MOD.Word


/*** T2SC0 - TIM2 Channel 0 Status and Control Register; 0x00000030 ***/
typedef union {
  byte Byte;
  struct {
    byte CH0MAX      :1;                                       /* Channel 0 Maximum Duty Cycle Bit */
    byte TOV0        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS0A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS0B       :1;                                       /* Edge/Level Select Bit B */
    byte MS0A        :1;                                       /* Mode Select Bit A */
    byte MS0B        :1;                                       /* Mode Select Bit B */
    byte CH0IE       :1;                                       /* Channel 0 Interrupt Enable Bit */
    byte CH0F        :1;                                       /* Channel 0 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV  :1;
    byte grpELS0x :2;
    byte grpMS0x :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} T2SC0STR;
extern volatile T2SC0STR _T2SC0;
#define T2SC0                           _T2SC0.Byte
#define T2SC0_CH0MAX                    _T2SC0.Bits.CH0MAX
#define T2SC0_TOV0                      _T2SC0.Bits.TOV0
#define T2SC0_ELS0A                     _T2SC0.Bits.ELS0A
#define T2SC0_ELS0B                     _T2SC0.Bits.ELS0B
#define T2SC0_MS0A                      _T2SC0.Bits.MS0A
#define T2SC0_MS0B                      _T2SC0.Bits.MS0B
#define T2SC0_CH0IE                     _T2SC0.Bits.CH0IE
#define T2SC0_CH0F                      _T2SC0.Bits.CH0F
#define T2SC0_ELS0x                     _T2SC0.MergedBits.grpELS0x
#define T2SC0_MS0x                      _T2SC0.MergedBits.grpMS0x

#define T2SC0_CH0MAX_MASK               1
#define T2SC0_TOV0_MASK                 2
#define T2SC0_ELS0A_MASK                4
#define T2SC0_ELS0B_MASK                8
#define T2SC0_MS0A_MASK                 16
#define T2SC0_MS0B_MASK                 32
#define T2SC0_CH0IE_MASK                64
#define T2SC0_CH0F_MASK                 128
#define T2SC0_ELS0x_MASK                12
#define T2SC0_ELS0x_BITNUM              2
#define T2SC0_MS0x_MASK                 48
#define T2SC0_MS0x_BITNUM               4


/*** T2CH0 - TIM2 Channel 0 Register; 0x00000031 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T2CH0H - TIM2 Channel 0 Register High; 0x00000031 ***/
    union {
      byte Byte;
    } T2CH0HSTR;
    #define T2CH0H                      _T2CH0.Overlap_STR.T2CH0HSTR.Byte
    

    /*** T2CH0L - TIM2 Channel 0 Register Low; 0x00000032 ***/
    union {
      byte Byte;
    } T2CH0LSTR;
    #define T2CH0L                      _T2CH0.Overlap_STR.T2CH0LSTR.Byte
    
  } Overlap_STR;

} T2CH0STR;
extern volatile T2CH0STR _T2CH0;
#define T2CH0                           _T2CH0.Word


/*** T2SC1 - TIM2 Channel 1 Status and Control Register; 0x00000033 ***/
typedef union {
  byte Byte;
  struct {
    byte CH1MAX      :1;                                       /* Channel 1 Maximum Duty Cycle Bit */
    byte TOV1        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS1A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS1B       :1;                                       /* Edge/Level Select Bit B */
    byte MS1A        :1;                                       /* Mode Select Bit A */
    byte             :1; 
    byte CH1IE       :1;                                       /* Channel 1 Interrupt Enable Bit */
    byte CH1F        :1;                                       /* Channel 1 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_1 :1;
    byte grpELS1x :2;
    byte grpMS1x :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} T2SC1STR;
extern volatile T2SC1STR _T2SC1;
#define T2SC1                           _T2SC1.Byte
#define T2SC1_CH1MAX                    _T2SC1.Bits.CH1MAX
#define T2SC1_TOV1                      _T2SC1.Bits.TOV1
#define T2SC1_ELS1A                     _T2SC1.Bits.ELS1A
#define T2SC1_ELS1B                     _T2SC1.Bits.ELS1B
#define T2SC1_MS1A                      _T2SC1.Bits.MS1A
#define T2SC1_CH1IE                     _T2SC1.Bits.CH1IE
#define T2SC1_CH1F                      _T2SC1.Bits.CH1F
#define T2SC1_ELS1x                     _T2SC1.MergedBits.grpELS1x

#define T2SC1_CH1MAX_MASK               1
#define T2SC1_TOV1_MASK                 2
#define T2SC1_ELS1A_MASK                4
#define T2SC1_ELS1B_MASK                8
#define T2SC1_MS1A_MASK                 16
#define T2SC1_CH1IE_MASK                64
#define T2SC1_CH1F_MASK                 128
#define T2SC1_ELS1x_MASK                12
#define T2SC1_ELS1x_BITNUM              2


/*** T2CH1 - TIM2 Channel 1 Register; 0x00000034 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T2CH1H - TIM2 Channel 1 Register High; 0x00000034 ***/
    union {
      byte Byte;
    } T2CH1HSTR;
    #define T2CH1H                      _T2CH1.Overlap_STR.T2CH1HSTR.Byte
    

    /*** T2CH1L - TIM2 Channel 1 Register Low; 0x00000035 ***/
    union {
      byte Byte;
    } T2CH1LSTR;
    #define T2CH1L                      _T2CH1.Overlap_STR.T2CH1LSTR.Byte
    
  } Overlap_STR;

} T2CH1STR;
extern volatile T2CH1STR _T2CH1;
#define T2CH1                           _T2CH1.Word


/*** PCTL - PLL Control Register; 0x00000036 ***/
typedef union {
  byte Byte;
  struct {
    byte VPR0        :1;                                       /* VCO Power-of-Two Range Select Bit 0 */
    byte VPR1        :1;                                       /* VCO Power-of-Two Range Select Bit 1 */
    byte             :1; 
    byte             :1; 
    byte BCS         :1;                                       /* Base Clock Select Bit */
    byte PLLON       :1;                                       /* PLL On Bit */
    byte PLLF        :1;                                       /* PLL Flag Bit */
    byte PLLIE       :1;                                       /* PLL Interrupt Enable Bit */
  } Bits;
  struct {
    byte grpVPR  :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} PCTLSTR;
extern volatile PCTLSTR _PCTL;
#define PCTL                            _PCTL.Byte
#define PCTL_VPR0                       _PCTL.Bits.VPR0
#define PCTL_VPR1                       _PCTL.Bits.VPR1
#define PCTL_BCS                        _PCTL.Bits.BCS
#define PCTL_PLLON                      _PCTL.Bits.PLLON
#define PCTL_PLLF                       _PCTL.Bits.PLLF
#define PCTL_PLLIE                      _PCTL.Bits.PLLIE
#define PCTL_VPR                        _PCTL.MergedBits.grpVPR

#define PCTL_VPR0_MASK                  1
#define PCTL_VPR1_MASK                  2
#define PCTL_BCS_MASK                   16
#define PCTL_PLLON_MASK                 32
#define PCTL_PLLF_MASK                  64
#define PCTL_PLLIE_MASK                 128
#define PCTL_VPR_MASK                   3
#define PCTL_VPR_BITNUM                 0


/*** PBWC - PLL Bandwidth Control Register; 0x00000037 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte ACQ         :1;                                       /* Acquisition Mode Bit */
    byte LOCK        :1;                                       /* Lock Indicator Bit */
    byte AUTO        :1;                                       /* Automatic Bandwidth Control Bit */
  } Bits;
} PBWCSTR;
extern volatile PBWCSTR _PBWC;
#define PBWC                            _PBWC.Byte
#define PBWC_ACQ                        _PBWC.Bits.ACQ
#define PBWC_LOCK                       _PBWC.Bits.LOCK
#define PBWC_AUTO                       _PBWC.Bits.AUTO

#define PBWC_ACQ_MASK                   32
#define PBWC_LOCK_MASK                  64
#define PBWC_AUTO_MASK                  128


/*** PMS - PLL Multiplier Select Register; 0x00000038 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PMSH - PLL Multiplier Select Register High; 0x00000038 ***/
    union {
      byte Byte;
      struct {
        byte MUL8        :1;                                       /* PLL Multiplier Select Bit 8 */
        byte MUL9        :1;                                       /* PLL Multiplier Select Bit 9 */
        byte MUL10       :1;                                       /* PLL Multiplier Select Bit 10 */
        byte MUL11       :1;                                       /* PLL Multiplier Select Bit 11 */
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
      } Bits;
      struct {
        byte grpMUL_8 :4;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
      } MergedBits;
    } PMSHSTR;
    #define PMSH                        _PMS.Overlap_STR.PMSHSTR.Byte
    #define PMSH_MUL8                   _PMS.Overlap_STR.PMSHSTR.Bits.MUL8
    #define PMSH_MUL9                   _PMS.Overlap_STR.PMSHSTR.Bits.MUL9
    #define PMSH_MUL10                  _PMS.Overlap_STR.PMSHSTR.Bits.MUL10
    #define PMSH_MUL11                  _PMS.Overlap_STR.PMSHSTR.Bits.MUL11
    #define PMSH_MUL_8                  _PMS.Overlap_STR.PMSHSTR.MergedBits.grpMUL_8
    #define PMSH_MUL                    PMSH_MUL_8
    
    #define PMSH_MUL8_MASK              1
    #define PMSH_MUL9_MASK              2
    #define PMSH_MUL10_MASK             4
    #define PMSH_MUL11_MASK             8
    #define PMSH_MUL_8_MASK             15
    #define PMSH_MUL_8_BITNUM           0
    

    /*** PMSL - PLL Multiplier Select Register Low; 0x00000039 ***/
    union {
      byte Byte;
      struct {
        byte MUL0        :1;                                       /* PLL Multiplier Select Bit 0 */
        byte MUL1        :1;                                       /* PLL Multiplier Select Bit 1 */
        byte MUL2        :1;                                       /* PLL Multiplier Select Bit 2 */
        byte MUL3        :1;                                       /* PLL Multiplier Select Bit 3 */
        byte MUL4        :1;                                       /* PLL Multiplier Select Bit 4 */
        byte MUL5        :1;                                       /* PLL Multiplier Select Bit 5 */
        byte MUL6        :1;                                       /* PLL Multiplier Select Bit 6 */
        byte MUL7        :1;                                       /* PLL Multiplier Select Bit 7 */
      } Bits;
    } PMSLSTR;
    #define PMSL                        _PMS.Overlap_STR.PMSLSTR.Byte
    #define PMSL_MUL0                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL0
    #define PMSL_MUL1                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL1
    #define PMSL_MUL2                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL2
    #define PMSL_MUL3                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL3
    #define PMSL_MUL4                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL4
    #define PMSL_MUL5                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL5
    #define PMSL_MUL6                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL6
    #define PMSL_MUL7                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL7
    
    #define PMSL_MUL0_MASK              1
    #define PMSL_MUL1_MASK              2
    #define PMSL_MUL2_MASK              4
    #define PMSL_MUL3_MASK              8
    #define PMSL_MUL4_MASK              16
    #define PMSL_MUL5_MASK              32
    #define PMSL_MUL6_MASK              64
    #define PMSL_MUL7_MASK              128
    
  } Overlap_STR;

} PMSSTR;
extern volatile PMSSTR _PMS;
#define PMS                             _PMS.Word


/*** PMRS - PLL VCO Range Select Register; 0x0000003A ***/
typedef union {
  byte Byte;
  struct {
    byte VRS0        :1;                                       /* PLL VCO Range Select Bit 0 */
    byte VRS1        :1;                                       /* PLL VCO Range Select Bit 1 */
    byte VRS2        :1;                                       /* PLL VCO Range Select Bit 2 */
    byte VRS3        :1;                                       /* PLL VCO Range Select Bit 3 */
    byte VRS4        :1;                                       /* PLL VCO Range Select Bit 4 */
    byte VRS5        :1;                                       /* PLL VCO Range Select Bit 5 */
    byte VRS6        :1;                                       /* PLL VCO Range Select Bit 6 */
    byte VRS7        :1;                                       /* PLL VCO Range Select Bit 7 */
  } Bits;
} PMRSSTR;
extern volatile PMRSSTR _PMRS;
#define PMRS                            _PMRS.Byte
#define PMRS_VRS0                       _PMRS.Bits.VRS0
#define PMRS_VRS1                       _PMRS.Bits.VRS1
#define PMRS_VRS2                       _PMRS.Bits.VRS2
#define PMRS_VRS3                       _PMRS.Bits.VRS3
#define PMRS_VRS4                       _PMRS.Bits.VRS4
#define PMRS_VRS5                       _PMRS.Bits.VRS5
#define PMRS_VRS6                       _PMRS.Bits.VRS6
#define PMRS_VRS7                       _PMRS.Bits.VRS7

#define PMRS_VRS0_MASK                  1
#define PMRS_VRS1_MASK                  2
#define PMRS_VRS2_MASK                  4
#define PMRS_VRS3_MASK                  8
#define PMRS_VRS4_MASK                  16
#define PMRS_VRS5_MASK                  32
#define PMRS_VRS6_MASK                  64
#define PMRS_VRS7_MASK                  128


/*** ADSCR - ADC Status and Control Register; 0x0000003C ***/
typedef union {
  byte Byte;
  struct {
    byte ADCH0       :1;                                       /* ADC Channel Select Bit 0 */
    byte ADCH1       :1;                                       /* ADC Channel Select Bit 1 */
    byte ADCH2       :1;                                       /* ADC Channel Select Bit 2 */
    byte ADCH3       :1;                                       /* ADC Channel Select Bit 3 */
    byte ADCH4       :1;                                       /* ADC Channel Select Bit 4 */
    byte ADCO        :1;                                       /* ADC Continuous Conversion Bit */
    byte AIEN        :1;                                       /* ADC Interrupt Enable Bit */
    byte COCO        :1;                                       /* Conversions Complete Bit */
  } Bits;
  struct {
    byte grpADCH :5;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} ADSCRSTR;
extern volatile ADSCRSTR _ADSCR;
#define ADSCR                           _ADSCR.Byte
#define ADSCR_ADCH0                     _ADSCR.Bits.ADCH0
#define ADSCR_ADCH1                     _ADSCR.Bits.ADCH1
#define ADSCR_ADCH2                     _ADSCR.Bits.ADCH2
#define ADSCR_ADCH3                     _ADSCR.Bits.ADCH3
#define ADSCR_ADCH4                     _ADSCR.Bits.ADCH4
#define ADSCR_ADCO                      _ADSCR.Bits.ADCO
#define ADSCR_AIEN                      _ADSCR.Bits.AIEN
#define ADSCR_COCO                      _ADSCR.Bits.COCO
#define ADSCR_ADCH                      _ADSCR.MergedBits.grpADCH

#define ADSCR_ADCH0_MASK                1
#define ADSCR_ADCH1_MASK                2
#define ADSCR_ADCH2_MASK                4
#define ADSCR_ADCH3_MASK                8
#define ADSCR_ADCH4_MASK                16
#define ADSCR_ADCO_MASK                 32
#define ADSCR_AIEN_MASK                 64
#define ADSCR_COCO_MASK                 128
#define ADSCR_ADCH_MASK                 31
#define ADSCR_ADCH_BITNUM               0


/*** ADR - ADC Data Register; 0x0000003D ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ADRH - ADC Data Register High; 0x0000003D ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* ADC Data Bit 8 */
        byte BIT9        :1;                                       /* ADC Data Bit 9 */
        byte BIT10       :1;                                       /* ADC Data Bit 10 */
        byte BIT11       :1;                                       /* ADC Data Bit 11 */
        byte BIT12       :1;                                       /* ADC Data Bit 12 */
        byte BIT13       :1;                                       /* ADC Data Bit 13 */
        byte BIT14       :1;                                       /* ADC Data Bit 14 */
        byte BIT15       :1;                                       /* ADC Data Bit 15 */
      } Bits;
    } ADRHSTR;
    #define ADRH                        _ADR.Overlap_STR.ADRHSTR.Byte
    #define ADRH_BIT8                   _ADR.Overlap_STR.ADRHSTR.Bits.BIT8
    #define ADRH_BIT9                   _ADR.Overlap_STR.ADRHSTR.Bits.BIT9
    #define ADRH_BIT10                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT10
    #define ADRH_BIT11                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT11
    #define ADRH_BIT12                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT12
    #define ADRH_BIT13                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT13
    #define ADRH_BIT14                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT14
    #define ADRH_BIT15                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT15
    
    #define ADRH_BIT8_MASK              1
    #define ADRH_BIT9_MASK              2
    #define ADRH_BIT10_MASK             4
    #define ADRH_BIT11_MASK             8
    #define ADRH_BIT12_MASK             16
    #define ADRH_BIT13_MASK             32
    #define ADRH_BIT14_MASK             64
    #define ADRH_BIT15_MASK             128
    

    /*** ADRL - ADC Data Register Low; 0x0000003E ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* ADC Data Bit 0 */
        byte BIT1        :1;                                       /* ADC Data Bit 1 */
        byte BIT2        :1;                                       /* ADC Data Bit 2 */
        byte BIT3        :1;                                       /* ADC Data Bit 3 */
        byte BIT4        :1;                                       /* ADC Data Bit 4 */
        byte BIT5        :1;                                       /* ADC Data Bit 5 */
        byte BIT6        :1;                                       /* ADC Data Bit 6 */
        byte BIT7        :1;                                       /* ADC Data Bit 7 */
      } Bits;
    } ADRLSTR;
    #define ADRL                        _ADR.Overlap_STR.ADRLSTR.Byte
    #define ADRL_BIT0                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT0
    #define ADRL_BIT1                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT1
    #define ADRL_BIT2                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT2
    #define ADRL_BIT3                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT3
    #define ADRL_BIT4                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT4
    #define ADRL_BIT5                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT5
    #define ADRL_BIT6                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT6
    #define ADRL_BIT7                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT7
    
    #define ADRL_BIT0_MASK              1
    #define ADRL_BIT1_MASK              2
    #define ADRL_BIT2_MASK              4
    #define ADRL_BIT3_MASK              8
    #define ADRL_BIT4_MASK              16
    #define ADRL_BIT5_MASK              32
    #define ADRL_BIT6_MASK              64
    #define ADRL_BIT7_MASK              128
    
  } Overlap_STR;

} ADRSTR;
extern volatile ADRSTR _ADR;
#define ADR                             _ADR.Word


/*** ADCLK - ADC Input Clock Register; 0x0000003F ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte MODE0       :1;                                       /* Modes of Result Justification Bit 0 */
    byte MODE1       :1;                                       /* Modes of Result Justification Bit 1 */
    byte ADICLK      :1;                                       /* ADC Input Clock Register Bit */
    byte ADIV0       :1;                                       /* ADC Clock Prescaler Bit 0 */
    byte ADIV1       :1;                                       /* ADC Clock Prescaler Bit 1 */
    byte ADIV2       :1;                                       /* ADC Clock Prescaler Bit 2 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpMODE :2;
    byte         :1;
    byte grpADIV :3;
  } MergedBits;
} ADCLKSTR;
extern volatile ADCLKSTR _ADCLK;
#define ADCLK                           _ADCLK.Byte
#define ADCLK_MODE0                     _ADCLK.Bits.MODE0
#define ADCLK_MODE1                     _ADCLK.Bits.MODE1
#define ADCLK_ADICLK                    _ADCLK.Bits.ADICLK
#define ADCLK_ADIV0                     _ADCLK.Bits.ADIV0
#define ADCLK_ADIV1                     _ADCLK.Bits.ADIV1
#define ADCLK_ADIV2                     _ADCLK.Bits.ADIV2
#define ADCLK_MODE                      _ADCLK.MergedBits.grpMODE
#define ADCLK_ADIV                      _ADCLK.MergedBits.grpADIV

#define ADCLK_MODE0_MASK                4
#define ADCLK_MODE1_MASK                8
#define ADCLK_ADICLK_MASK               16
#define ADCLK_ADIV0_MASK                32
#define ADCLK_ADIV1_MASK                64
#define ADCLK_ADIV2_MASK                128
#define ADCLK_MODE_MASK                 12
#define ADCLK_MODE_BITNUM               2
#define ADCLK_ADIV_MASK                 224
#define ADCLK_ADIV_BITNUM               5


/*** PTF - Port F Data Register; 0x00000440 ***/
typedef union {
  byte Byte;
  struct {
    byte PTF0        :1;                                       /* Port F Data Bit 0 */
    byte PTF1        :1;                                       /* Port F Data Bit 1 */
    byte PTF2        :1;                                       /* Port F Data Bit 2 */
    byte PTF3        :1;                                       /* Port F Data Bit 3 */
    byte PTF4        :1;                                       /* Port F Data Bit 4 */
    byte PTF5        :1;                                       /* Port F Data Bit 5 */
    byte PTF6        :1;                                       /* Port F Data Bit 6 */
    byte PTF7        :1;                                       /* Port F Data Bit 7 */
  } Bits;
} PTFSTR;
extern volatile PTFSTR _PTF;
#define PTF                             _PTF.Byte
#define PTF_PTF0                        _PTF.Bits.PTF0
#define PTF_PTF1                        _PTF.Bits.PTF1
#define PTF_PTF2                        _PTF.Bits.PTF2
#define PTF_PTF3                        _PTF.Bits.PTF3
#define PTF_PTF4                        _PTF.Bits.PTF4
#define PTF_PTF5                        _PTF.Bits.PTF5
#define PTF_PTF6                        _PTF.Bits.PTF6
#define PTF_PTF7                        _PTF.Bits.PTF7

#define PTF_PTF0_MASK                   1
#define PTF_PTF1_MASK                   2
#define PTF_PTF2_MASK                   4
#define PTF_PTF3_MASK                   8
#define PTF_PTF4_MASK                   16
#define PTF_PTF5_MASK                   32
#define PTF_PTF6_MASK                   64
#define PTF_PTF7_MASK                   128


/*** PTG - Port G Data Register; 0x00000441 ***/
typedef union {
  byte Byte;
  struct {
    byte PTG0        :1;                                       /* Port G Data Bit 0 */
    byte PTG1        :1;                                       /* Port G Data Bit 1 */
    byte PTG2        :1;                                       /* Port G Data Bit 2 */
    byte PTG3        :1;                                       /* Port G Data Bit 3 */
    byte PTG4        :1;                                       /* Port G Data Bit 4 */
    byte PTG5        :1;                                       /* Port G Data Bit 5 */
    byte PTG6        :1;                                       /* Port G Data Bit 6 */
    byte PTG7        :1;                                       /* Port G Data Bit 7 */
  } Bits;
} PTGSTR;
extern volatile PTGSTR _PTG;
#define PTG                             _PTG.Byte
#define PTG_PTG0                        _PTG.Bits.PTG0
#define PTG_PTG1                        _PTG.Bits.PTG1
#define PTG_PTG2                        _PTG.Bits.PTG2
#define PTG_PTG3                        _PTG.Bits.PTG3
#define PTG_PTG4                        _PTG.Bits.PTG4
#define PTG_PTG5                        _PTG.Bits.PTG5
#define PTG_PTG6                        _PTG.Bits.PTG6
#define PTG_PTG7                        _PTG.Bits.PTG7

#define PTG_PTG0_MASK                   1
#define PTG_PTG1_MASK                   2
#define PTG_PTG2_MASK                   4
#define PTG_PTG3_MASK                   8
#define PTG_PTG4_MASK                   16
#define PTG_PTG5_MASK                   32
#define PTG_PTG6_MASK                   64
#define PTG_PTG7_MASK                   128


/*** DDRF - Data Direction Register F; 0x00000444 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRF0       :1;                                       /* Data Direction Register F Bit 0 */
    byte DDRF1       :1;                                       /* Data Direction Register F Bit 1 */
    byte DDRF2       :1;                                       /* Data Direction Register F Bit 2 */
    byte DDRF3       :1;                                       /* Data Direction Register F Bit 3 */
    byte DDRF4       :1;                                       /* Data Direction Register F Bit 4 */
    byte DDRF5       :1;                                       /* Data Direction Register F Bit 5 */
    byte DDRF6       :1;                                       /* Data Direction Register F Bit 6 */
    byte DDRF7       :1;                                       /* Data Direction Register F Bit 7 */
  } Bits;
} DDRFSTR;
extern volatile DDRFSTR _DDRF;
#define DDRF                            _DDRF.Byte
#define DDRF_DDRF0                      _DDRF.Bits.DDRF0
#define DDRF_DDRF1                      _DDRF.Bits.DDRF1
#define DDRF_DDRF2                      _DDRF.Bits.DDRF2
#define DDRF_DDRF3                      _DDRF.Bits.DDRF3
#define DDRF_DDRF4                      _DDRF.Bits.DDRF4
#define DDRF_DDRF5                      _DDRF.Bits.DDRF5
#define DDRF_DDRF6                      _DDRF.Bits.DDRF6
#define DDRF_DDRF7                      _DDRF.Bits.DDRF7

#define DDRF_DDRF0_MASK                 1
#define DDRF_DDRF1_MASK                 2
#define DDRF_DDRF2_MASK                 4
#define DDRF_DDRF3_MASK                 8
#define DDRF_DDRF4_MASK                 16
#define DDRF_DDRF5_MASK                 32
#define DDRF_DDRF6_MASK                 64
#define DDRF_DDRF7_MASK                 128


/*** DDRG - Data Direction Register G; 0x00000445 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRG0       :1;                                       /* Data Direction Register G Bit 0 */
    byte DDRG1       :1;                                       /* Data Direction Register G Bit 1 */
    byte DDRG2       :1;                                       /* Data Direction Register G Bit 2 */
    byte DDRG3       :1;                                       /* Data Direction Register G Bit 3 */
    byte DDRG4       :1;                                       /* Data Direction Register G Bit 4 */
    byte DDRG5       :1;                                       /* Data Direction Register G Bit 5 */
    byte DDRG6       :1;                                       /* Data Direction Register G Bit 6 */
    byte DDRG7       :1;                                       /* Data Direction Register G Bit 7 */
  } Bits;
} DDRGSTR;
extern volatile DDRGSTR _DDRG;
#define DDRG                            _DDRG.Byte
#define DDRG_DDRG0                      _DDRG.Bits.DDRG0
#define DDRG_DDRG1                      _DDRG.Bits.DDRG1
#define DDRG_DDRG2                      _DDRG.Bits.DDRG2
#define DDRG_DDRG3                      _DDRG.Bits.DDRG3
#define DDRG_DDRG4                      _DDRG.Bits.DDRG4
#define DDRG_DDRG5                      _DDRG.Bits.DDRG5
#define DDRG_DDRG6                      _DDRG.Bits.DDRG6
#define DDRG_DDRG7                      _DDRG.Bits.DDRG7

#define DDRG_DDRG0_MASK                 1
#define DDRG_DDRG1_MASK                 2
#define DDRG_DDRG2_MASK                 4
#define DDRG_DDRG3_MASK                 8
#define DDRG_DDRG4_MASK                 16
#define DDRG_DDRG5_MASK                 32
#define DDRG_DDRG6_MASK                 64
#define DDRG_DDRG7_MASK                 128


/*** INTKBIPR - Keyboard Interrupt Polarity Register; 0x00000448 ***/
typedef union {
  byte Byte;
  struct {
    byte KBIP0       :1;                                       /* Keyboard Interrupt Polarity Bit 0 */
    byte KBIP1       :1;                                       /* Keyboard Interrupt Polarity Bit 1 */
    byte KBIP2       :1;                                       /* Keyboard Interrupt Polarity Bit 2 */
    byte KBIP3       :1;                                       /* Keyboard Interrupt Polarity Bit 3 */
    byte KBIP4       :1;                                       /* Keyboard Interrupt Polarity Bit 4 */
    byte KBIP5       :1;                                       /* Keyboard Interrupt Polarity Bit 5 */
    byte KBIP6       :1;                                       /* Keyboard Interrupt Polarity Bit 6 */
    byte KBIP7       :1;                                       /* Keyboard Interrupt Polarity Bit 7 */
  } Bits;
} INTKBIPRSTR;
extern volatile INTKBIPRSTR _INTKBIPR;
#define INTKBIPR                        _INTKBIPR.Byte
#define INTKBIPR_KBIP0                  _INTKBIPR.Bits.KBIP0
#define INTKBIPR_KBIP1                  _INTKBIPR.Bits.KBIP1
#define INTKBIPR_KBIP2                  _INTKBIPR.Bits.KBIP2
#define INTKBIPR_KBIP3                  _INTKBIPR.Bits.KBIP3
#define INTKBIPR_KBIP4                  _INTKBIPR.Bits.KBIP4
#define INTKBIPR_KBIP5                  _INTKBIPR.Bits.KBIP5
#define INTKBIPR_KBIP6                  _INTKBIPR.Bits.KBIP6
#define INTKBIPR_KBIP7                  _INTKBIPR.Bits.KBIP7

#define INTKBIPR_KBIP0_MASK             1
#define INTKBIPR_KBIP1_MASK             2
#define INTKBIPR_KBIP2_MASK             4
#define INTKBIPR_KBIP3_MASK             8
#define INTKBIPR_KBIP4_MASK             16
#define INTKBIPR_KBIP5_MASK             32
#define INTKBIPR_KBIP6_MASK             64
#define INTKBIPR_KBIP7_MASK             128


/*** T2SC2 - TIM2 Channel 2 Status and Control Register; 0x00000456 ***/
typedef union {
  byte Byte;
  struct {
    byte CH2MAX      :1;                                       /* Channel 2 Maximum Duty Cycle Bit */
    byte TOV2        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS2A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS2B       :1;                                       /* Edge/Level Select Bit B */
    byte MS2A        :1;                                       /* Mode Select Bit A */
    byte MS2B        :1;                                       /* Mode Select Bit B */
    byte CH2IE       :1;                                       /* Channel 2 Interrupt Enable Bit */
    byte CH2F        :1;                                       /* Channel 2 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_2 :1;
    byte grpELS2x :2;
    byte grpMS2x :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} T2SC2STR;
extern volatile T2SC2STR _T2SC2;
#define T2SC2                           _T2SC2.Byte
#define T2SC2_CH2MAX                    _T2SC2.Bits.CH2MAX
#define T2SC2_TOV2                      _T2SC2.Bits.TOV2
#define T2SC2_ELS2A                     _T2SC2.Bits.ELS2A
#define T2SC2_ELS2B                     _T2SC2.Bits.ELS2B
#define T2SC2_MS2A                      _T2SC2.Bits.MS2A
#define T2SC2_MS2B                      _T2SC2.Bits.MS2B
#define T2SC2_CH2IE                     _T2SC2.Bits.CH2IE
#define T2SC2_CH2F                      _T2SC2.Bits.CH2F
#define T2SC2_ELS2x                     _T2SC2.MergedBits.grpELS2x
#define T2SC2_MS2x                      _T2SC2.MergedBits.grpMS2x

#define T2SC2_CH2MAX_MASK               1
#define T2SC2_TOV2_MASK                 2
#define T2SC2_ELS2A_MASK                4
#define T2SC2_ELS2B_MASK                8
#define T2SC2_MS2A_MASK                 16
#define T2SC2_MS2B_MASK                 32
#define T2SC2_CH2IE_MASK                64
#define T2SC2_CH2F_MASK                 128
#define T2SC2_ELS2x_MASK                12
#define T2SC2_ELS2x_BITNUM              2
#define T2SC2_MS2x_MASK                 48
#define T2SC2_MS2x_BITNUM               4


/*** T2CH2 - TIM2 Channel 2 Register; 0x00000457 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T2CH2H - TIM2 Channel 2 Register High; 0x00000457 ***/
    union {
      byte Byte;
    } T2CH2HSTR;
    #define T2CH2H                      _T2CH2.Overlap_STR.T2CH2HSTR.Byte
    

    /*** T2CH2L - TIM2 Channel 2 Register Low; 0x00000458 ***/
    union {
      byte Byte;
    } T2CH2LSTR;
    #define T2CH2L                      _T2CH2.Overlap_STR.T2CH2LSTR.Byte
    
  } Overlap_STR;

} T2CH2STR;
extern volatile T2CH2STR _T2CH2;
#define T2CH2                           _T2CH2.Word


/*** T2SC3 - TIM2 Channel 3 Status and Control Register; 0x00000459 ***/
typedef union {
  byte Byte;
  struct {
    byte CH3MAX      :1;                                       /* Channel 3 Maximum Duty Cycle Bit */
    byte TOV3        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS3A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS3B       :1;                                       /* Edge/Level Select Bit B */
    byte MS3A        :1;                                       /* Mode Select Bit A */
    byte             :1; 
    byte CH3IE       :1;                                       /* Channel 3 Interrupt Enable Bit */
    byte CH3F        :1;                                       /* Channel 3 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_3 :1;
    byte grpELS3x :2;
    byte grpMS3x :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} T2SC3STR;
extern volatile T2SC3STR _T2SC3;
#define T2SC3                           _T2SC3.Byte
#define T2SC3_CH3MAX                    _T2SC3.Bits.CH3MAX
#define T2SC3_TOV3                      _T2SC3.Bits.TOV3
#define T2SC3_ELS3A                     _T2SC3.Bits.ELS3A
#define T2SC3_ELS3B                     _T2SC3.Bits.ELS3B
#define T2SC3_MS3A                      _T2SC3.Bits.MS3A
#define T2SC3_CH3IE                     _T2SC3.Bits.CH3IE
#define T2SC3_CH3F                      _T2SC3.Bits.CH3F
#define T2SC3_ELS3x                     _T2SC3.MergedBits.grpELS3x

#define T2SC3_CH3MAX_MASK               1
#define T2SC3_TOV3_MASK                 2
#define T2SC3_ELS3A_MASK                4
#define T2SC3_ELS3B_MASK                8
#define T2SC3_MS3A_MASK                 16
#define T2SC3_CH3IE_MASK                64
#define T2SC3_CH3F_MASK                 128
#define T2SC3_ELS3x_MASK                12
#define T2SC3_ELS3x_BITNUM              2


/*** T2CH3 - TIM2 Channel 3 Register; 0x0000045A ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T2CH3H - TIM2 Channel 3 Register High; 0x0000045A ***/
    union {
      byte Byte;
    } T2CH3HSTR;
    #define T2CH3H                      _T2CH3.Overlap_STR.T2CH3HSTR.Byte
    

    /*** T2CH3L - TIM2 Channel 3 Register Low; 0x0000045B ***/
    union {
      byte Byte;
    } T2CH3LSTR;
    #define T2CH3L                      _T2CH3.Overlap_STR.T2CH3LSTR.Byte
    
  } Overlap_STR;

} T2CH3STR;
extern volatile T2CH3STR _T2CH3;
#define T2CH3                           _T2CH3.Word


/*** T2SC4 - TIM2 Channel 4 Status and Control Register; 0x0000045C ***/
typedef union {
  byte Byte;
  struct {
    byte CH4MAX      :1;                                       /* Channel 4 Maximum Duty Cycle Bit */
    byte TOV4        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS4A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS4B       :1;                                       /* Edge/Level Select Bit B */
    byte MS4A        :1;                                       /* Mode Select Bit A */
    byte MS4B        :1;                                       /* Mode Select Bit B */
    byte CH4IE       :1;                                       /* Channel 4 Interrupt Enable Bit */
    byte CH4F        :1;                                       /* Channel 4 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_4 :1;
    byte grpELS4x :2;
    byte grpMS4x :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} T2SC4STR;
extern volatile T2SC4STR _T2SC4;
#define T2SC4                           _T2SC4.Byte
#define T2SC4_CH4MAX                    _T2SC4.Bits.CH4MAX
#define T2SC4_TOV4                      _T2SC4.Bits.TOV4
#define T2SC4_ELS4A                     _T2SC4.Bits.ELS4A
#define T2SC4_ELS4B                     _T2SC4.Bits.ELS4B
#define T2SC4_MS4A                      _T2SC4.Bits.MS4A
#define T2SC4_MS4B                      _T2SC4.Bits.MS4B
#define T2SC4_CH4IE                     _T2SC4.Bits.CH4IE
#define T2SC4_CH4F                      _T2SC4.Bits.CH4F
#define T2SC4_ELS4x                     _T2SC4.MergedBits.grpELS4x
#define T2SC4_MS4x                      _T2SC4.MergedBits.grpMS4x

#define T2SC4_CH4MAX_MASK               1
#define T2SC4_TOV4_MASK                 2
#define T2SC4_ELS4A_MASK                4
#define T2SC4_ELS4B_MASK                8
#define T2SC4_MS4A_MASK                 16
#define T2SC4_MS4B_MASK                 32
#define T2SC4_CH4IE_MASK                64
#define T2SC4_CH4F_MASK                 128
#define T2SC4_ELS4x_MASK                12
#define T2SC4_ELS4x_BITNUM              2
#define T2SC4_MS4x_MASK                 48
#define T2SC4_MS4x_BITNUM               4


/*** T2CH4 - TIM2 Channel 4 Register; 0x0000045D ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T2CH4H - TIM2 Channel 4 Register High; 0x0000045D ***/
    union {
      byte Byte;
    } T2CH4HSTR;
    #define T2CH4H                      _T2CH4.Overlap_STR.T2CH4HSTR.Byte
    

    /*** T2CH4L - TIM2 Channel 4 Register Low; 0x0000045E ***/
    union {
      byte Byte;
    } T2CH4LSTR;
    #define T2CH4L                      _T2CH4.Overlap_STR.T2CH4LSTR.Byte
    
  } Overlap_STR;

} T2CH4STR;
extern volatile T2CH4STR _T2CH4;
#define T2CH4                           _T2CH4.Word


/*** T2SC5 - TIM2 Channel 5 Status and Control Register; 0x0000045F ***/
typedef union {
  byte Byte;
  struct {
    byte CH5MAX      :1;                                       /* Channel 5 Maximum Duty Cycle Bit */
    byte TOV5        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS5A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS5B       :1;                                       /* Edge/Level Select Bit B */
    byte MS5A        :1;                                       /* Mode Select Bit A */
    byte             :1; 
    byte CH5IE       :1;                                       /* Channel 5 Interrupt Enable Bit */
    byte CH5F        :1;                                       /* Channel 5 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_5 :1;
    byte grpELS5x :2;
    byte grpMS5x :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} T2SC5STR;
extern volatile T2SC5STR _T2SC5;
#define T2SC5                           _T2SC5.Byte
#define T2SC5_CH5MAX                    _T2SC5.Bits.CH5MAX
#define T2SC5_TOV5                      _T2SC5.Bits.TOV5
#define T2SC5_ELS5A                     _T2SC5.Bits.ELS5A
#define T2SC5_ELS5B                     _T2SC5.Bits.ELS5B
#define T2SC5_MS5A                      _T2SC5.Bits.MS5A
#define T2SC5_CH5IE                     _T2SC5.Bits.CH5IE
#define T2SC5_CH5F                      _T2SC5.Bits.CH5F
#define T2SC5_ELS5x                     _T2SC5.MergedBits.grpELS5x

#define T2SC5_CH5MAX_MASK               1
#define T2SC5_TOV5_MASK                 2
#define T2SC5_ELS5A_MASK                4
#define T2SC5_ELS5B_MASK                8
#define T2SC5_MS5A_MASK                 16
#define T2SC5_CH5IE_MASK                64
#define T2SC5_CH5F_MASK                 128
#define T2SC5_ELS5x_MASK                12
#define T2SC5_ELS5x_BITNUM              2


/*** T2CH5 - TIM2 Channel 5 Register; 0x00000460 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T2CH5H - TIM2 Channel 5 Register High; 0x00000460 ***/
    union {
      byte Byte;
    } T2CH5HSTR;
    #define T2CH5H                      _T2CH5.Overlap_STR.T2CH5HSTR.Byte
    

    /*** T2CH5L - TIM2 Channel 5 Register Low; 0x00000461 ***/
    union {
      byte Byte;
    } T2CH5LSTR;
    #define T2CH5L                      _T2CH5.Overlap_STR.T2CH5LSTR.Byte
    
  } Overlap_STR;

} T2CH5STR;
extern volatile T2CH5STR _T2CH5;
#define T2CH5                           _T2CH5.Word


/*** BSR - Break Status Register; 0x0000FE00 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte SBSW        :1;                                       /* SIM Break Stop/Wait */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} BSRSTR;
extern volatile BSRSTR _BSR;
#define BSR                             _BSR.Byte
#define BSR_SBSW                        _BSR.Bits.SBSW

#define BSR_SBSW_MASK                   2


/*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte LVI         :1;                                       /* Low-Voltage Inhibit Reset Bit */
    byte MODRST      :1;                                       /* Monitor Mode Entry Module Reset Bit */
    byte ILAD        :1;                                       /* Illegal Address Reset Bit */
    byte ILOP        :1;                                       /* Illegal Opcode Reset Bit */
    byte COP         :1;                                       /* Computer Operating Properly Reset Bit */
    byte PIN         :1;                                       /* External Reset Bit */
    byte POR         :1;                                       /* Power-On Reset Bit */
  } Bits;
} SRSRSTR;
extern volatile SRSRSTR _SRSR;
#define SRSR                            _SRSR.Byte
#define SRSR_LVI                        _SRSR.Bits.LVI
#define SRSR_MODRST                     _SRSR.Bits.MODRST
#define SRSR_ILAD                       _SRSR.Bits.ILAD
#define SRSR_ILOP                       _SRSR.Bits.ILOP
#define SRSR_COP                        _SRSR.Bits.COP
#define SRSR_PIN                        _SRSR.Bits.PIN
#define SRSR_POR                        _SRSR.Bits.POR

#define SRSR_LVI_MASK                   2
#define SRSR_MODRST_MASK                4
#define SRSR_ILAD_MASK                  8
#define SRSR_ILOP_MASK                  16
#define SRSR_COP_MASK                   32
#define SRSR_PIN_MASK                   64
#define SRSR_POR_MASK                   128


/*** SBFCR - SIM Break Flag Control Register; 0x0000FE03 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BCFE        :1;                                       /* Break Clear Flag Enable Bit */
  } Bits;
} SBFCRSTR;
extern volatile SBFCRSTR _SBFCR;
#define SBFCR                           _SBFCR.Byte
#define SBFCR_BCFE                      _SBFCR.Bits.BCFE

#define SBFCR_BCFE_MASK                 128


/*** INT1 - Interrupt Status Register 1; 0x0000FE04 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte IF1         :1;                                       /* Interrupt Status Bit 1 */
    byte IF2         :1;                                       /* Interrupt Status Bit 2 */
    byte IF3         :1;                                       /* Interrupt Status Bit 3 */
    byte IF4         :1;                                       /* Interrupt Status Bit 4 */
    byte IF5         :1;                                       /* Interrupt Status Bit 5 */
    byte IF6         :1;                                       /* Interrupt Status Bit 6 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpIF_1 :6;
  } MergedBits;
} INT1STR;
extern volatile INT1STR _INT1;
#define INT1                            _INT1.Byte
#define INT1_IF1                        _INT1.Bits.IF1
#define INT1_IF2                        _INT1.Bits.IF2
#define INT1_IF3                        _INT1.Bits.IF3
#define INT1_IF4                        _INT1.Bits.IF4
#define INT1_IF5                        _INT1.Bits.IF5
#define INT1_IF6                        _INT1.Bits.IF6
#define INT1_IF_1                       _INT1.MergedBits.grpIF_1
#define INT1_IF                         INT1_IF_1

#define INT1_IF1_MASK                   4
#define INT1_IF2_MASK                   8
#define INT1_IF3_MASK                   16
#define INT1_IF4_MASK                   32
#define INT1_IF5_MASK                   64
#define INT1_IF6_MASK                   128
#define INT1_IF_1_MASK                  252
#define INT1_IF_1_BITNUM                2


/*** INT2 - Interrupt Status Register 2; 0x0000FE05 ***/
typedef union {
  byte Byte;
  struct {
    byte IF7         :1;                                       /* Interrupt Status Bit 7 */
    byte IF8         :1;                                       /* Interrupt Status Bit 8 */
    byte IF9         :1;                                       /* Interrupt Status Bit 9 */
    byte IF10        :1;                                       /* Interrupt Status Bit 10 */
    byte IF11        :1;                                       /* Interrupt Status Bit 11 */
    byte IF12        :1;                                       /* Interrupt Status Bit 12 */
    byte IF13        :1;                                       /* Interrupt Status Bit 13 */
    byte IF14        :1;                                       /* Interrupt Status Bit 14 */
  } Bits;
} INT2STR;
extern volatile INT2STR _INT2;
#define INT2                            _INT2.Byte
#define INT2_IF7                        _INT2.Bits.IF7
#define INT2_IF8                        _INT2.Bits.IF8
#define INT2_IF9                        _INT2.Bits.IF9
#define INT2_IF10                       _INT2.Bits.IF10
#define INT2_IF11                       _INT2.Bits.IF11
#define INT2_IF12                       _INT2.Bits.IF12
#define INT2_IF13                       _INT2.Bits.IF13
#define INT2_IF14                       _INT2.Bits.IF14

#define INT2_IF7_MASK                   1
#define INT2_IF8_MASK                   2
#define INT2_IF9_MASK                   4
#define INT2_IF10_MASK                  8
#define INT2_IF11_MASK                  16
#define INT2_IF12_MASK                  32
#define INT2_IF13_MASK                  64
#define INT2_IF14_MASK                  128


/*** INT3 - Interrupt Status Register 3; 0x0000FE06 ***/
typedef union {
  byte Byte;
  struct {
    byte IF15        :1;                                       /* Interrupt Status Bit 15 */
    byte IF16        :1;                                       /* Interrupt Status Bit 16 */
    byte IF17        :1;                                       /* Interrupt Status Bit 17 */
    byte IF18        :1;                                       /* Interrupt Status Bit 18 */
    byte IF19        :1;                                       /* Interrupt Status Bit 19 */
    byte IF20        :1;                                       /* Interrupt Status Bit 20 */
    byte IF21        :1;                                       /* Interrupt Status Bit 21 */
    byte IF22        :1;                                       /* Interrupt Status Bit 22 */
  } Bits;
} INT3STR;
extern volatile INT3STR _INT3;
#define INT3                            _INT3.Byte
#define INT3_IF15                       _INT3.Bits.IF15
#define INT3_IF16                       _INT3.Bits.IF16
#define INT3_IF17                       _INT3.Bits.IF17
#define INT3_IF18                       _INT3.Bits.IF18
#define INT3_IF19                       _INT3.Bits.IF19
#define INT3_IF20                       _INT3.Bits.IF20
#define INT3_IF21                       _INT3.Bits.IF21
#define INT3_IF22                       _INT3.Bits.IF22

#define INT3_IF15_MASK                  1
#define INT3_IF16_MASK                  2
#define INT3_IF17_MASK                  4
#define INT3_IF18_MASK                  8
#define INT3_IF19_MASK                  16
#define INT3_IF20_MASK                  32
#define INT3_IF21_MASK                  64
#define INT3_IF22_MASK                  128


/*** INT4 - Interrupt Status Register 4; 0x0000FE07 ***/
typedef union {
  byte Byte;
  struct {
    byte IF23        :1;                                       /* Interrupt Status Bit 23 */
    byte IF24        :1;                                       /* Interrupt Status Bit 24 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpIF_23 :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} INT4STR;
extern volatile INT4STR _INT4;
#define INT4                            _INT4.Byte
#define INT4_IF23                       _INT4.Bits.IF23
#define INT4_IF24                       _INT4.Bits.IF24
#define INT4_IF_23                      _INT4.MergedBits.grpIF_23
#define INT4_IF                         INT4_IF_23

#define INT4_IF23_MASK                  1
#define INT4_IF24_MASK                  2
#define INT4_IF_23_MASK                 3
#define INT4_IF_23_BITNUM               0


/*** FL2CR - FLASH 2 Control Register; 0x0000FE08 ***/
typedef union {
  byte Byte;
  struct {
    byte PGM         :1;                                       /* Program Control Bit */
    byte ERASE       :1;                                       /* Erase Control Bit */
    byte MASS        :1;                                       /* Mass Erase Control Bit */
    byte HVEN        :1;                                       /* High-Voltage Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} FL2CRSTR;
extern volatile FL2CRSTR _FL2CR;
#define FL2CR                           _FL2CR.Byte
#define FL2CR_PGM                       _FL2CR.Bits.PGM
#define FL2CR_ERASE                     _FL2CR.Bits.ERASE
#define FL2CR_MASS                      _FL2CR.Bits.MASS
#define FL2CR_HVEN                      _FL2CR.Bits.HVEN

#define FL2CR_PGM_MASK                  1
#define FL2CR_ERASE_MASK                2
#define FL2CR_MASS_MASK                 4
#define FL2CR_HVEN_MASK                 8


/*** BRK - Break Address Register; 0x0000FE09 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** BRKH - Break Address Register High; 0x0000FE09 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Break Address Register Bit 8 */
        byte BIT9        :1;                                       /* Break Address Register Bit 9 */
        byte BIT10       :1;                                       /* Break Address Register Bit 10 */
        byte BIT11       :1;                                       /* Break Address Register Bit 11 */
        byte BIT12       :1;                                       /* Break Address Register Bit 12 */
        byte BIT13       :1;                                       /* Break Address Register Bit 13 */
        byte BIT14       :1;                                       /* Break Address Register Bit 14 */
        byte BIT15       :1;                                       /* Break Address Register Bit 15 */
      } Bits;
    } BRKHSTR;
    #define BRKH                        _BRK.Overlap_STR.BRKHSTR.Byte
    #define BRKH_BIT8                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT8
    #define BRKH_BIT9                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT9
    #define BRKH_BIT10                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT10
    #define BRKH_BIT11                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT11
    #define BRKH_BIT12                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT12
    #define BRKH_BIT13                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT13
    #define BRKH_BIT14                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT14
    #define BRKH_BIT15                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT15
    
    #define BRKH_BIT8_MASK              1
    #define BRKH_BIT9_MASK              2
    #define BRKH_BIT10_MASK             4
    #define BRKH_BIT11_MASK             8
    #define BRKH_BIT12_MASK             16
    #define BRKH_BIT13_MASK             32
    #define BRKH_BIT14_MASK             64
    #define BRKH_BIT15_MASK             128
    

    /*** BRKL - Break Address Register Low; 0x0000FE0A ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Break Address Register Bit 0 */
        byte BIT1        :1;                                       /* Break Address Register Bit 1 */
        byte BIT2        :1;                                       /* Break Address Register Bit 2 */
        byte BIT3        :1;                                       /* Break Address Register Bit 3 */
        byte BIT4        :1;                                       /* Break Address Register Bit 4 */
        byte BIT5        :1;                                       /* Break Address Register Bit 5 */
        byte BIT6        :1;                                       /* Break Address Register Bit 6 */
        byte BIT7        :1;                                       /* Break Address Register Bit 7 */
      } Bits;
    } BRKLSTR;
    #define BRKL                        _BRK.Overlap_STR.BRKLSTR.Byte
    #define BRKL_BIT0                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT0
    #define BRKL_BIT1                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT1
    #define BRKL_BIT2                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT2
    #define BRKL_BIT3                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT3
    #define BRKL_BIT4                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT4
    #define BRKL_BIT5                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT5
    #define BRKL_BIT6                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT6
    #define BRKL_BIT7                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT7
    
    #define BRKL_BIT0_MASK              1
    #define BRKL_BIT1_MASK              2
    #define BRKL_BIT2_MASK              4
    #define BRKL_BIT3_MASK              8
    #define BRKL_BIT4_MASK              16
    #define BRKL_BIT5_MASK              32
    #define BRKL_BIT6_MASK              64
    #define BRKL_BIT7_MASK              128
    
  } Overlap_STR;

} BRKSTR;
extern volatile BRKSTR _BRK;
#define BRK                             _BRK.Word


/*** BRKSCR - Break Status and Control Register; 0x0000FE0B ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BRKA        :1;                                       /* Break Active Bit */
    byte BRKE        :1;                                       /* Break Enable Bit */
  } Bits;
} BRKSCRSTR;
extern volatile BRKSCRSTR _BRKSCR;
#define BRKSCR                          _BRKSCR.Byte
#define BRKSCR_BRKA                     _BRKSCR.Bits.BRKA
#define BRKSCR_BRKE                     _BRKSCR.Bits.BRKE

#define BRKSCR_BRKA_MASK                64
#define BRKSCR_BRKE_MASK                128


/*** LVISR - LVI Status Register; 0x0000FE0C ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte LVIOUT      :1;                                       /* LVI Output Bit */
  } Bits;
} LVISRSTR;
extern volatile LVISRSTR _LVISR;
#define LVISR                           _LVISR.Byte
#define LVISR_LVIOUT                    _LVISR.Bits.LVIOUT

#define LVISR_LVIOUT_MASK               128


/*** FL1BPR - FLASH 1 Block Protect Register; 0x0000FF80 ***/
typedef union {
  byte Byte;
  struct {
    byte BPR0        :1;                                       /* Block Protect Register Bit 0 */
    byte BPR1        :1;                                       /* Block Protect Register Bit 1 */
    byte BPR2        :1;                                       /* Block Protect Register Bit 2 */
    byte BPR3        :1;                                       /* Block Protect Register Bit 3 */
    byte BPR4        :1;                                       /* Block Protect Register Bit 4 */
    byte BPR5        :1;                                       /* Block Protect Register Bit 5 */
    byte BPR6        :1;                                       /* Block Protect Register Bit 6 */
    byte BPR7        :1;                                       /* Block Protect Register Bit 7 */
  } Bits;
} FL1BPRSTR;
/* Tip for register initialization in the user code:  const byte FL1BPR_INIT @0x0000FF80 = <FL1BPR_INITVAL>; */
#define _FL1BPR (*(const FL1BPRSTR * __far)0x0000FF80)
#define FL1BPR                          _FL1BPR.Byte
#define FL1BPR_BPR0                     _FL1BPR.Bits.BPR0
#define FL1BPR_BPR1                     _FL1BPR.Bits.BPR1
#define FL1BPR_BPR2                     _FL1BPR.Bits.BPR2
#define FL1BPR_BPR3                     _FL1BPR.Bits.BPR3
#define FL1BPR_BPR4                     _FL1BPR.Bits.BPR4
#define FL1BPR_BPR5                     _FL1BPR.Bits.BPR5
#define FL1BPR_BPR6                     _FL1BPR.Bits.BPR6
#define FL1BPR_BPR7                     _FL1BPR.Bits.BPR7

#define FL1BPR_BPR0_MASK                1
#define FL1BPR_BPR1_MASK                2
#define FL1BPR_BPR2_MASK                4
#define FL1BPR_BPR3_MASK                8
#define FL1BPR_BPR4_MASK                16
#define FL1BPR_BPR5_MASK                32
#define FL1BPR_BPR6_MASK                64
#define FL1BPR_BPR7_MASK                128


/*** FL2BPR - FLASH 2 Block Protect Register; 0x0000FF81 ***/
typedef union {
  byte Byte;
  struct {
    byte BPR0        :1;                                       /* Block Protect Register Bit 0 */
    byte BPR1        :1;                                       /* Block Protect Register Bit 1 */
    byte BPR2        :1;                                       /* Block Protect Register Bit 2 */
    byte BPR3        :1;                                       /* Block Protect Register Bit 3 */
    byte BPR4        :1;                                       /* Block Protect Register Bit 4 */
    byte BPR5        :1;                                       /* Block Protect Register Bit 5 */
    byte BPR6        :1;                                       /* Block Protect Register Bit 6 */
    byte BPR7        :1;                                       /* Block Protect Register Bit 7 */
  } Bits;
} FL2BPRSTR;
extern volatile FL2BPRSTR _FL2BPR;
#define FL2BPR                          _FL2BPR.Byte
#define FL2BPR_BPR0                     _FL2BPR.Bits.BPR0
#define FL2BPR_BPR1                     _FL2BPR.Bits.BPR1
#define FL2BPR_BPR2                     _FL2BPR.Bits.BPR2
#define FL2BPR_BPR3                     _FL2BPR.Bits.BPR3
#define FL2BPR_BPR4                     _FL2BPR.Bits.BPR4
#define FL2BPR_BPR5                     _FL2BPR.Bits.BPR5
#define FL2BPR_BPR6                     _FL2BPR.Bits.BPR6
#define FL2BPR_BPR7                     _FL2BPR.Bits.BPR7

#define FL2BPR_BPR0_MASK                1
#define FL2BPR_BPR1_MASK                2
#define FL2BPR_BPR2_MASK                4
#define FL2BPR_BPR3_MASK                8
#define FL2BPR_BPR4_MASK                16
#define FL2BPR_BPR5_MASK                32
#define FL2BPR_BPR6_MASK                64
#define FL2BPR_BPR7_MASK                128


/*** FL1CR - FLASH 1 Control Register; 0x0000FF88 ***/
typedef union {
  byte Byte;
  struct {
    byte PGM         :1;                                       /* Program Control Bit */
    byte ERASE       :1;                                       /* Erase Control Bit */
    byte MASS        :1;                                       /* Mass Erase Control Bit */
    byte HVEN        :1;                                       /* High-Voltage Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} FL1CRSTR;
extern volatile FL1CRSTR _FL1CR;
#define FL1CR                           _FL1CR.Byte
#define FL1CR_PGM                       _FL1CR.Bits.PGM
#define FL1CR_ERASE                     _FL1CR.Bits.ERASE
#define FL1CR_MASS                      _FL1CR.Bits.MASS
#define FL1CR_HVEN                      _FL1CR.Bits.HVEN

#define FL1CR_PGM_MASK                  1
#define FL1CR_ERASE_MASK                2
#define FL1CR_MASS_MASK                 4
#define FL1CR_HVEN_MASK                 8


/*** COPCTL - COP Control Register; 0x0000FFFF ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Bit 0 */
    byte BIT1        :1;                                       /* Bit 1 */
    byte BIT2        :1;                                       /* Bit 2 */
    byte BIT3        :1;                                       /* Bit 3 */
    byte BIT4        :1;                                       /* Bit 4 */
    byte BIT5        :1;                                       /* Bit 5 */
    byte BIT6        :1;                                       /* Bit 6 */
    byte BIT7        :1;                                       /* Bit 7 */
  } Bits;
} COPCTLSTR;
extern volatile COPCTLSTR _COPCTL;
#define COPCTL                          _COPCTL.Byte
#define COPCTL_BIT0                     _COPCTL.Bits.BIT0
#define COPCTL_BIT1                     _COPCTL.Bits.BIT1
#define COPCTL_BIT2                     _COPCTL.Bits.BIT2
#define COPCTL_BIT3                     _COPCTL.Bits.BIT3
#define COPCTL_BIT4                     _COPCTL.Bits.BIT4
#define COPCTL_BIT5                     _COPCTL.Bits.BIT5
#define COPCTL_BIT6                     _COPCTL.Bits.BIT6
#define COPCTL_BIT7                     _COPCTL.Bits.BIT7

#define COPCTL_BIT0_MASK                1
#define COPCTL_BIT1_MASK                2
#define COPCTL_BIT2_MASK                4
#define COPCTL_BIT3_MASK                8
#define COPCTL_BIT4_MASK                16
#define COPCTL_BIT5_MASK                32
#define COPCTL_BIT6_MASK                64
#define COPCTL_BIT7_MASK                128



/***********************************************/
/**   D E P R E C I A T E D   S Y M B O L S   **/
/***********************************************/
/* ---------------------------------------------------------------------------------------------------
Exceptions in bit names of timer status and control registers
due to backward compatibility with previous releases  */
#define T1SC0_CHxMAX _T1SC0.Bits.CH0MAX
#define T1SC0_TOVx _T1SC0.Bits.TOV0
#define T1SC0_ELSxA _T1SC0.Bits.ELS0A
#define T1SC0_ELSxB _T1SC0.Bits.ELS0B
#define T1SC0_MSxA _T1SC0.Bits.MS0A
#define T1SC0_MSxB _T1SC0.Bits.MS0B
#define T1SC0_CHxIE _T1SC0.Bits.CH0IE
#define T1SC0_CHxF _T1SC0.Bits.CH0F

#define T1SC1_CHxMAX _T1SC1.Bits.CH1MAX
#define T1SC1_TOVx _T1SC1.Bits.TOV1
#define T1SC1_ELSxA _T1SC1.Bits.ELS1A
#define T1SC1_ELSxB _T1SC1.Bits.ELS1B
#define T1SC1_MSxA _T1SC1.Bits.MS1A
#define T1SC1_CHxIE _T1SC1.Bits.CH1IE
#define T1SC1_CHxF _T1SC1.Bits.CH1F

#define T2SC0_CHxMAX _T2SC0.Bits.CH0MAX
#define T2SC0_TOVx _T2SC0.Bits.TOV0
#define T2SC0_ELSxA _T2SC0.Bits.ELS0A
#define T2SC0_ELSxB _T2SC0.Bits.ELS0B
#define T2SC0_MSxA _T2SC0.Bits.MS0A
#define T2SC0_MSxB _T2SC0.Bits.MS0B
#define T2SC0_CHxIE _T2SC0.Bits.CH0IE
#define T2SC0_CHxF _T2SC0.Bits.CH0F

#define T2SC1_CHxMAX _T2SC1.Bits.CH1MAX
#define T2SC1_TOVx _T2SC1.Bits.TOV1
#define T2SC1_ELSxA _T2SC1.Bits.ELS1A
#define T2SC1_ELSxB _T2SC1.Bits.ELS1B
#define T2SC1_MSxA _T2SC1.Bits.MS1A
#define T2SC1_CHxIE _T2SC1.Bits.CH1IE
#define T2SC1_CHxF _T2SC1.Bits.CH1F

#define T2SC2_CHxMAX _T2SC2.Bits.CH2MAX
#define T2SC2_TOVx _T2SC2.Bits.TOV2
#define T2SC2_ELSxA _T2SC2.Bits.ELS2A
#define T2SC2_ELSxB _T2SC2.Bits.ELS2B
#define T2SC2_MSxA _T2SC2.Bits.MS2A
#define T2SC2_CHxIE _T2SC2.Bits.CH2IE
#define T2SC2_CHxF _T2SC2.Bits.CH2F

#define T2SC3_CHxMAX _T2SC3.Bits.CH3MAX
#define T2SC3_TOVx _T2SC3.Bits.TOV3
#define T2SC3_ELSxA _T2SC3.Bits.ELS3A
#define T2SC3_ELSxB _T2SC3.Bits.ELS3B
#define T2SC3_MSxA _T2SC3.Bits.MS3A
#define T2SC3_CHxIE _T2SC3.Bits.CH3IE
#define T2SC3_CHxF _T2SC3.Bits.CH3F

#define T2SC4_CHxMAX _T2SC4.Bits.CH4MAX
#define T2SC4_TOVx _T2SC4.Bits.TOV4
#define T2SC4_ELSxA _T2SC4.Bits.ELS4A
#define T2SC4_ELSxB _T2SC4.Bits.ELS4B
#define T2SC4_MSxA _T2SC4.Bits.MS4A
#define T2SC4_CHxIE _T2SC4.Bits.CH4IE
#define T2SC4_CHxF _T2SC4.Bits.CH4F

#define T2SC5_CHxMAX _T2SC5.Bits.CH5MAX
#define T2SC5_TOVx _T2SC5.Bits.TOV5
#define T2SC5_ELSxA _T2SC5.Bits.ELS5A
#define T2SC5_ELSxB _T2SC5.Bits.ELS5B
#define T2SC5_MSxA _T2SC5.Bits.MS5A
#define T2SC5_CHxIE _T2SC5.Bits.CH5IE
#define T2SC5_CHxF _T2SC5.Bits.CH5F

/* --------------------------------------------------------------------------- */
/* The following symbols were removed, because they were invalid or irrelevant */
/* --------------------------------------------------------------------------- */


/* **** 12.12.2007 14:50:18 */

#define SCIACTL_AOVFL                    SCIACTL_AROVFL
#define SCIACTL_AOVFL_MASK               SCIACTL_AROVFL_MASK


/* **** 11.9.2009 12:42:36 */

#define T1CH_ARR                         This_symb_has_been_depreciated
#define T2CH_ARR                         This_symb_has_been_depreciated
#endif
