/* Based on CPU DB MC68HC908LB8, version 2.87.182 (RegistersPrg V2.30) */
/*
** ###################################################################
**     Filename  : mc68hc908lb8.h
**     Processor : MC68HC908LB8CDWE
**     FileFormat: V2.30
**     DataSheet : MC68HC908LB8 Rev. 1 8/2005
**     Compiler  : CodeWarrior compiler
**     Date/Time : 11.9.2009, 14:09
**     Abstract  :
**         This header implements the mapping of I/O devices.
**
**     Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved.
**     
**     http      : www.freescale.com
**     mail      : support@freescale.com
**
**     CPU Registers Revisions:
**               - none
**
**     File-Format-Revisions:
**      - 14.11.2005, V2.00 :
**               - Deprecated symbols added for backward compatibility (section at the end of this file)
**      - 15.11.2005, V2.01 :
**               - Changes have not affected this file (because they are related to another family)
**      - 17.12.2005, V2.02 :
**               - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778
**      - 16.01.2006, V2.03 :
**               - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920.
**               - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const")
**      - 08.03.2006, V2.04 :
**               - Support for bit(s) names duplicated with any register name in .h header files
**      - 24.03.2006, V2.05 :
**               - Changes have not affected this file (because they are related to another family)
**      - 26.04.2006, V2.06 :
**               - Absolute assembly supported (depreciated symbols are not defined)
**      - 27.04.2006, V2.07 :
**               - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA).
**      - 07.06.2006, V2.08 :
**               - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM.
**      - 03.07.2006, V2.09 :
**               - Flash commands constants supported
**      - 27.10.2006, V2.10 :
**               - __RESET_WATCHDOG improved formating and re-definition
**      - 23.11.2006, V2.11 :
**               - Changes have not affected this file (because they are related to another family)
**      - 22.01.2007, V2.12 :
**               - Changes have not affected this file (because they are related to another family)
**      - 01.03.2007, V2.13 :
**               - Flash commands constants values converted to HEX format
**      - 02.03.2007, V2.14 :
**               - Interrupt vector numbers added into .H, see VectorNumber_*
**      - 26.03.2007, V2.15 :
**               - Changes have not affected this file (because they are related to another family)
**      - 10.05.2007, V2.16 :
**               - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ)
**      - 05.06.2007, V2.17 :
**               - Changes have not affected this file (because they are related to another family)
**      - 19.07.2007, V2.18 :
**               - Improved number of blanked lines inside register structures
**      - 06.08.2007, V2.19 :
**               - CPUDB revisions generated ahead of the file-format revisions.
**      - 11.09.2007, V2.20 :
**               - Added comment about initialization of unbonded pins.
**      - 02.01.2008, V2.21 :
**               - Changes have not affected this file (because they are related to another family)
**      - 13.02.2008, V2.22 :
**               - Changes have not affected this file (because they are related to another family)
**      - 20.02.2008, V2.23 :
**               - Changes have not affected this file (because they are related to another family)
**      - 03.07.2008, V2.24 :
**               - Added support for bits with name starting with number (like "1HZ")
**      - 28.11.2008, V2.25 :
**               - StandBy RAM array declaration for ANSI-C added
**      - 1.12.2008, V2.26 :
**               - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map.
**      - 17.3.2009, V2.27 :
**               - Merged bit-group is not generated, if the name matches with another bit name in the register
**      - 6.4.2009, V2.28 :
**               - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB
**      - 3.8.2009, V2.29 :
**               - If there is just one bits group matching register name, single bits are not generated
**      - 10.9.2009, V2.30 :
**               - Fixed generation of registers arrays.
**
**     Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific
**     derivative device. To avoid extra current drain from floating input pins, the user’s reset
**     initialization routine in the application program must either enable on-chip pull-up devices
**     or change the direction of unconnected pins to outputs so the pins do not float.
** ###################################################################
*/

#ifndef _MC68HC908LB8_H
#define _MC68HC908LB8_H

/* Types definition */
typedef unsigned char byte;
typedef unsigned int word;
typedef unsigned long dword;
typedef unsigned long dlong[2];

/* Watchdog reset macro */
#ifndef __RESET_WATCHDOG
#ifdef _lint
  #define __RESET_WATCHDOG()  /* empty */
#else
  #define __RESET_WATCHDOG() {asm sta COPCTL;}
#endif
#endif /* __RESET_WATCHDOG */

#define REG_BASE 0x0000                /* Base address for the I/O register block */


#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */

/**************** interrupt vector numbers ****************/
#define VectorNumber_ADC                16
#define VectorNumber_KBI                15
#define VectorNumber_Reserved2          14
#define VectorNumber_Reserved3          13
#define VectorNumber_Reserved4          12
#define VectorNumber_Reserved5          11
#define VectorNumber_Reserved6          10
#define VectorNumber_SHTDWN             9
#define VectorNumber_PWMINT             8
#define VectorNumber_FAULT              7
#define VectorNumber_TIMOvr             6
#define VectorNumber_TIMCH1             5
#define VectorNumber_TIMCH0             4
#define VectorNumber_Reserved13         3
#define VectorNumber_IRQ                2
#define VectorNumber_SWI                1
#define VectorNumber_RESET              0

/**************** interrupt vector table ****************/
#define INT_ADC                         0x0000FFDE
#define INT_KBI                         0x0000FFE0
#define Reserved2                       0x0000FFE2
#define Reserved3                       0x0000FFE4
#define Reserved4                       0x0000FFE6
#define Reserved5                       0x0000FFE8
#define Reserved6                       0x0000FFEA
#define INT_SHTDWN                      0x0000FFEC
#define INT_PWMINT                      0x0000FFEE
#define INT_FAULT                       0x0000FFF0
#define INT_TIMOvr                      0x0000FFF2
#define INT_TIMCH1                      0x0000FFF4
#define INT_TIMCH0                      0x0000FFF6
#define Reserved13                      0x0000FFF8
#define INT_IRQ                         0x0000FFFA
#define INT_SWI                         0x0000FFFC
#define INT_RESET                       0x0000FFFE

/**************** registers I/O map ****************/

/*** PTA - Port A Data Register; 0x00000000 ***/
typedef union {
  byte Byte;
  struct {
    byte PTA0        :1;                                       /* Port A Data Bit 0 */
    byte PTA1        :1;                                       /* Port A Data Bit 1 */
    byte PTA2        :1;                                       /* Port A Data Bit 2 */
    byte PTA3        :1;                                       /* Port A Data Bit 3 */
    byte PTA4        :1;                                       /* Port A Data Bit 4 */
    byte PTA5        :1;                                       /* Port A Data Bit 5 */
    byte PTA6        :1;                                       /* Port A Data Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpPTA  :7;
    byte         :1;
  } MergedBits;
} PTASTR;
extern volatile PTASTR _PTA;
#define PTA                             _PTA.Byte
#define PTA_PTA0                        _PTA.Bits.PTA0
#define PTA_PTA1                        _PTA.Bits.PTA1
#define PTA_PTA2                        _PTA.Bits.PTA2
#define PTA_PTA3                        _PTA.Bits.PTA3
#define PTA_PTA4                        _PTA.Bits.PTA4
#define PTA_PTA5                        _PTA.Bits.PTA5
#define PTA_PTA6                        _PTA.Bits.PTA6
#define PTA_PTA                         _PTA.MergedBits.grpPTA

#define PTA_PTA0_MASK                   1
#define PTA_PTA1_MASK                   2
#define PTA_PTA2_MASK                   4
#define PTA_PTA3_MASK                   8
#define PTA_PTA4_MASK                   16
#define PTA_PTA5_MASK                   32
#define PTA_PTA6_MASK                   64
#define PTA_PTA_MASK                    127
#define PTA_PTA_BITNUM                  0


/*** PTB - Port B Data Register; 0x00000001 ***/
typedef union {
  byte Byte;
  struct {
    byte PTB0        :1;                                       /* Port B Data Bit 0 */
    byte PTB1        :1;                                       /* Port B Data Bit 1 */
    byte PTB2        :1;                                       /* Port B Data Bit 2 */
    byte PTB3        :1;                                       /* Port B Data Bit 3 */
    byte PTB4        :1;                                       /* Port B Data Bit 4 */
    byte PTB5        :1;                                       /* Port B Data Bit 5 */
    byte PTB6        :1;                                       /* Port B Data Bit 6 */
    byte PTB7        :1;                                       /* Port B Data Bit 7 */
  } Bits;
} PTBSTR;
extern volatile PTBSTR _PTB;
#define PTB                             _PTB.Byte
#define PTB_PTB0                        _PTB.Bits.PTB0
#define PTB_PTB1                        _PTB.Bits.PTB1
#define PTB_PTB2                        _PTB.Bits.PTB2
#define PTB_PTB3                        _PTB.Bits.PTB3
#define PTB_PTB4                        _PTB.Bits.PTB4
#define PTB_PTB5                        _PTB.Bits.PTB5
#define PTB_PTB6                        _PTB.Bits.PTB6
#define PTB_PTB7                        _PTB.Bits.PTB7

#define PTB_PTB0_MASK                   1
#define PTB_PTB1_MASK                   2
#define PTB_PTB2_MASK                   4
#define PTB_PTB3_MASK                   8
#define PTB_PTB4_MASK                   16
#define PTB_PTB5_MASK                   32
#define PTB_PTB6_MASK                   64
#define PTB_PTB7_MASK                   128


/*** PTC - Port C Data Register; 0x00000002 ***/
typedef union {
  byte Byte;
  struct {
    byte PTC0        :1;                                       /* Port C Data Bit 0 */
    byte PTC1        :1;                                       /* Port C Data Bit 1 */
    byte PTC2        :1;                                       /* Port C Data Bit 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpPTC  :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} PTCSTR;
extern volatile PTCSTR _PTC;
#define PTC                             _PTC.Byte
#define PTC_PTC0                        _PTC.Bits.PTC0
#define PTC_PTC1                        _PTC.Bits.PTC1
#define PTC_PTC2                        _PTC.Bits.PTC2
#define PTC_PTC                         _PTC.MergedBits.grpPTC

#define PTC_PTC0_MASK                   1
#define PTC_PTC1_MASK                   2
#define PTC_PTC2_MASK                   4
#define PTC_PTC_MASK                    7
#define PTC_PTC_BITNUM                  0


/*** DDRA - Data Direction Register A; 0x00000004 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRA0       :1;                                       /* Data Direction Register A Bit 0 */
    byte DDRA1       :1;                                       /* Data Direction Register A Bit 1 */
    byte DDRA2       :1;                                       /* Data Direction Register A Bit 2 */
    byte DDRA3       :1;                                       /* Data Direction Register A Bit 3 */
    byte DDRA4       :1;                                       /* Data Direction Register A Bit 4 */
    byte DDRA5       :1;                                       /* Data Direction Register A Bit 5 */
    byte DDRA6       :1;                                       /* Data Direction Register A Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpDDRA :7;
    byte         :1;
  } MergedBits;
} DDRASTR;
extern volatile DDRASTR _DDRA;
#define DDRA                            _DDRA.Byte
#define DDRA_DDRA0                      _DDRA.Bits.DDRA0
#define DDRA_DDRA1                      _DDRA.Bits.DDRA1
#define DDRA_DDRA2                      _DDRA.Bits.DDRA2
#define DDRA_DDRA3                      _DDRA.Bits.DDRA3
#define DDRA_DDRA4                      _DDRA.Bits.DDRA4
#define DDRA_DDRA5                      _DDRA.Bits.DDRA5
#define DDRA_DDRA6                      _DDRA.Bits.DDRA6
#define DDRA_DDRA                       _DDRA.MergedBits.grpDDRA

#define DDRA_DDRA0_MASK                 1
#define DDRA_DDRA1_MASK                 2
#define DDRA_DDRA2_MASK                 4
#define DDRA_DDRA3_MASK                 8
#define DDRA_DDRA4_MASK                 16
#define DDRA_DDRA5_MASK                 32
#define DDRA_DDRA6_MASK                 64
#define DDRA_DDRA_MASK                  127
#define DDRA_DDRA_BITNUM                0


/*** DDRB - Data Direction Register B; 0x00000005 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRB0       :1;                                       /* Data Direction Register B Bit 0 */
    byte DDRB1       :1;                                       /* Data Direction Register B Bit 1 */
    byte DDRB2       :1;                                       /* Data Direction Register B Bit 2 */
    byte DDRB3       :1;                                       /* Data Direction Register B Bit 3 */
    byte DDRB4       :1;                                       /* Data Direction Register B Bit 4 */
    byte DDRB5       :1;                                       /* Data Direction Register B Bit 5 */
    byte DDRB6       :1;                                       /* Data Direction Register B Bit 6 */
    byte DDRB7       :1;                                       /* Data Direction Register B Bit 7 */
  } Bits;
} DDRBSTR;
extern volatile DDRBSTR _DDRB;
#define DDRB                            _DDRB.Byte
#define DDRB_DDRB0                      _DDRB.Bits.DDRB0
#define DDRB_DDRB1                      _DDRB.Bits.DDRB1
#define DDRB_DDRB2                      _DDRB.Bits.DDRB2
#define DDRB_DDRB3                      _DDRB.Bits.DDRB3
#define DDRB_DDRB4                      _DDRB.Bits.DDRB4
#define DDRB_DDRB5                      _DDRB.Bits.DDRB5
#define DDRB_DDRB6                      _DDRB.Bits.DDRB6
#define DDRB_DDRB7                      _DDRB.Bits.DDRB7

#define DDRB_DDRB0_MASK                 1
#define DDRB_DDRB1_MASK                 2
#define DDRB_DDRB2_MASK                 4
#define DDRB_DDRB3_MASK                 8
#define DDRB_DDRB4_MASK                 16
#define DDRB_DDRB5_MASK                 32
#define DDRB_DDRB6_MASK                 64
#define DDRB_DDRB7_MASK                 128


/*** DDRC - Data Direction Register C; 0x00000006 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRC0       :1;                                       /* Data Direction Register C Bit 0 */
    byte DDRC1       :1;                                       /* Data Direction Register C Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDDRC :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DDRCSTR;
extern volatile DDRCSTR _DDRC;
#define DDRC                            _DDRC.Byte
#define DDRC_DDRC0                      _DDRC.Bits.DDRC0
#define DDRC_DDRC1                      _DDRC.Bits.DDRC1
#define DDRC_DDRC                       _DDRC.MergedBits.grpDDRC

#define DDRC_DDRC0_MASK                 1
#define DDRC_DDRC1_MASK                 2
#define DDRC_DDRC_MASK                  3
#define DDRC_DDRC_BITNUM                0


/*** PTAPUE - Port A Input Pullup Enable Register; 0x0000000D ***/
typedef union {
  byte Byte;
  struct {
    byte PTA0PUE     :1;                                       /* Pull-Up Enable bit 0, Port A */
    byte PTA1PUE     :1;                                       /* Pull-Up Enable bit 1, Port A */
    byte PTA2PUE     :1;                                       /* Pull-Up Enable bit 2, Port A */
    byte PTA3PUE     :1;                                       /* Pull-Up Enable bit 3, Port A */
    byte PTA4PUE     :1;                                       /* Pull-Up Enable bit 4, Port A */
    byte PTA5PUE     :1;                                       /* Pull-Up Enable bit 5, Port A */
    byte PTA6PUE     :1;                                       /* Pull-Up Enable bit 6, Port A */
    byte             :1; 
  } Bits;
} PTAPUESTR;
extern volatile PTAPUESTR _PTAPUE;
#define PTAPUE                          _PTAPUE.Byte
#define PTAPUE_PTA0PUE                  _PTAPUE.Bits.PTA0PUE
#define PTAPUE_PTA1PUE                  _PTAPUE.Bits.PTA1PUE
#define PTAPUE_PTA2PUE                  _PTAPUE.Bits.PTA2PUE
#define PTAPUE_PTA3PUE                  _PTAPUE.Bits.PTA3PUE
#define PTAPUE_PTA4PUE                  _PTAPUE.Bits.PTA4PUE
#define PTAPUE_PTA5PUE                  _PTAPUE.Bits.PTA5PUE
#define PTAPUE_PTA6PUE                  _PTAPUE.Bits.PTA6PUE

#define PTAPUE_PTA0PUE_MASK             1
#define PTAPUE_PTA1PUE_MASK             2
#define PTAPUE_PTA2PUE_MASK             4
#define PTAPUE_PTA3PUE_MASK             8
#define PTAPUE_PTA4PUE_MASK             16
#define PTAPUE_PTA5PUE_MASK             32
#define PTAPUE_PTA6PUE_MASK             64


/*** PTCPUE - Port C Input Pullup Enable Register; 0x0000000E ***/
typedef union {
  byte Byte;
  struct {
    byte PTCPUE0     :1;                                       /* Pull-Up Enable bit 0, Port C */
    byte PTCPUE1     :1;                                       /* Pull-Up Enable bit 1, Port C */
    byte PTCPUE2     :1;                                       /* Pull-Up Enable bit 2, Port C */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte OSC2EN      :1;                                       /* Enable PTC1 on OSC2 Pin */
  } Bits;
  struct {
    byte grpPTCPUE :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} PTCPUESTR;
extern volatile PTCPUESTR _PTCPUE;
#define PTCPUE                          _PTCPUE.Byte
#define PTCPUE_PTCPUE0                  _PTCPUE.Bits.PTCPUE0
#define PTCPUE_PTCPUE1                  _PTCPUE.Bits.PTCPUE1
#define PTCPUE_PTCPUE2                  _PTCPUE.Bits.PTCPUE2
#define PTCPUE_OSC2EN                   _PTCPUE.Bits.OSC2EN
#define PTCPUE_PTCPUE                   _PTCPUE.MergedBits.grpPTCPUE

#define PTCPUE_PTCPUE0_MASK             1
#define PTCPUE_PTCPUE1_MASK             2
#define PTCPUE_PTCPUE2_MASK             4
#define PTCPUE_OSC2EN_MASK              128
#define PTCPUE_PTCPUE_MASK              7
#define PTCPUE_PTCPUE_BITNUM            0


/*** INTKBSCR - Keyboard Status and Control Register; 0x0000001A ***/
typedef union {
  byte Byte;
  struct {
    byte MODEK       :1;                                       /* Keyboard Triggering Sensitivity Bit */
    byte IMASKK      :1;                                       /* Keyboard Interrupt Mask Bit */
    byte ACKK        :1;                                       /* Keyboard Acknowledge Bit */
    byte KEYF        :1;                                       /* Keyboard Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} INTKBSCRSTR;
extern volatile INTKBSCRSTR _INTKBSCR;
#define INTKBSCR                        _INTKBSCR.Byte
#define INTKBSCR_MODEK                  _INTKBSCR.Bits.MODEK
#define INTKBSCR_IMASKK                 _INTKBSCR.Bits.IMASKK
#define INTKBSCR_ACKK                   _INTKBSCR.Bits.ACKK
#define INTKBSCR_KEYF                   _INTKBSCR.Bits.KEYF

#define INTKBSCR_MODEK_MASK             1
#define INTKBSCR_IMASKK_MASK            2
#define INTKBSCR_ACKK_MASK              4
#define INTKBSCR_KEYF_MASK              8


/*** INTKBIER - Keyboard Interrrupt Enable Register KBIER; 0x0000001B ***/
typedef union {
  byte Byte;
  struct {
    byte KBIE0       :1;                                       /* Keyboard Interrupt Enable Bit 0 */
    byte KBIE1       :1;                                       /* Keyboard Interrupt Enable Bit 1 */
    byte KBIE2       :1;                                       /* Keyboard Interrupt Enable Bit 2 */
    byte KBIE3       :1;                                       /* Keyboard Interrupt Enable Bit 3 */
    byte KBIE4       :1;                                       /* Keyboard Interrupt Enable Bit 4 */
    byte KBIE5       :1;                                       /* Keyboard Interrupt Enable Bit 5 */
    byte KBIE6       :1;                                       /* Keyboard Interrupt Enable Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpKBIE :7;
    byte         :1;
  } MergedBits;
} INTKBIERSTR;
extern volatile INTKBIERSTR _INTKBIER;
#define INTKBIER                        _INTKBIER.Byte
#define INTKBIER_KBIE0                  _INTKBIER.Bits.KBIE0
#define INTKBIER_KBIE1                  _INTKBIER.Bits.KBIE1
#define INTKBIER_KBIE2                  _INTKBIER.Bits.KBIE2
#define INTKBIER_KBIE3                  _INTKBIER.Bits.KBIE3
#define INTKBIER_KBIE4                  _INTKBIER.Bits.KBIE4
#define INTKBIER_KBIE5                  _INTKBIER.Bits.KBIE5
#define INTKBIER_KBIE6                  _INTKBIER.Bits.KBIE6
#define INTKBIER_KBIE                   _INTKBIER.MergedBits.grpKBIE

#define INTKBIER_KBIE0_MASK             1
#define INTKBIER_KBIE1_MASK             2
#define INTKBIER_KBIE2_MASK             4
#define INTKBIER_KBIE3_MASK             8
#define INTKBIER_KBIE4_MASK             16
#define INTKBIER_KBIE5_MASK             32
#define INTKBIER_KBIE6_MASK             64
#define INTKBIER_KBIE_MASK              127
#define INTKBIER_KBIE_BITNUM            0


/*** INTSCR - IRQ Status and Control Register; 0x0000001D ***/
typedef union {
  byte Byte;
  struct {
    byte MODE        :1;                                       /* IRQ Edge/Level Select Bit */
    byte IMASK       :1;                                       /* IRQ Interrupt Mask Bit */
    byte ACK         :1;                                       /* IRQ Interrupt Request Acknowledge Bit */
    byte IRQF        :1;                                       /* IRQ Flag */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} INTSCRSTR;
extern volatile INTSCRSTR _INTSCR;
#define INTSCR                          _INTSCR.Byte
#define INTSCR_MODE                     _INTSCR.Bits.MODE
#define INTSCR_IMASK                    _INTSCR.Bits.IMASK
#define INTSCR_ACK                      _INTSCR.Bits.ACK
#define INTSCR_IRQF                     _INTSCR.Bits.IRQF

#define INTSCR_MODE_MASK                1
#define INTSCR_IMASK_MASK               2
#define INTSCR_ACK_MASK                 4
#define INTSCR_IRQF_MASK                8


/*** CONFIG2 - Configuration Register 2; 0x0000001E ***/
typedef union {
  byte Byte;
  struct {
    byte RSTEN       :1;                                       /* RST Pin Function Selection */
    byte             :1; 
    byte             :1; 
    byte OSCOPT0     :1;                                       /* Selection Bit 0 for Oscillator Option */
    byte OSCOPT1     :1;                                       /* Selection Bit 1 for Oscillator Option */
    byte             :1; 
    byte IRQEN       :1;                                       /* IRQ Pin Function Selection Bit */
    byte IRQPUD      :1;                                       /* IRQ Pin Pull-Up Control Bit */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpOSCOPT :2;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CONFIG2STR;
extern volatile CONFIG2STR _CONFIG2;
#define CONFIG2                         _CONFIG2.Byte
#define CONFIG2_RSTEN                   _CONFIG2.Bits.RSTEN
#define CONFIG2_OSCOPT0                 _CONFIG2.Bits.OSCOPT0
#define CONFIG2_OSCOPT1                 _CONFIG2.Bits.OSCOPT1
#define CONFIG2_IRQEN                   _CONFIG2.Bits.IRQEN
#define CONFIG2_IRQPUD                  _CONFIG2.Bits.IRQPUD
#define CONFIG2_OSCOPT                  _CONFIG2.MergedBits.grpOSCOPT

#define CONFIG2_RSTEN_MASK              1
#define CONFIG2_OSCOPT0_MASK            8
#define CONFIG2_OSCOPT1_MASK            16
#define CONFIG2_IRQEN_MASK              64
#define CONFIG2_IRQPUD_MASK             128
#define CONFIG2_OSCOPT_MASK             24
#define CONFIG2_OSCOPT_BITNUM           3


/*** CONFIG1 - Configuration Register 1; 0x0000001F ***/
typedef union {
  byte Byte;
  struct {
    byte COPD        :1;                                       /* COP Disable Bit */
    byte STOP        :1;                                       /* STOP Instruction Enable Bit */
    byte SSREC       :1;                                       /* Short Stop Recovery Bit */
    byte             :1; 
    byte LVIPWRD     :1;                                       /* LVI Power Disable Bit */
    byte LVIRSTD     :1;                                       /* LVI Reset Disable Bit */
    byte LVISTOP     :1;                                       /* LVI Enable in Stop Mode Bit */
    byte COPRS       :1;                                       /* COP Reset Period Selection Bit */
  } Bits;
} CONFIG1STR;
extern volatile CONFIG1STR _CONFIG1;
#define CONFIG1                         _CONFIG1.Byte
#define CONFIG1_COPD                    _CONFIG1.Bits.COPD
#define CONFIG1_STOP                    _CONFIG1.Bits.STOP
#define CONFIG1_SSREC                   _CONFIG1.Bits.SSREC
#define CONFIG1_LVIPWRD                 _CONFIG1.Bits.LVIPWRD
#define CONFIG1_LVIRSTD                 _CONFIG1.Bits.LVIRSTD
#define CONFIG1_LVISTOP                 _CONFIG1.Bits.LVISTOP
#define CONFIG1_COPRS                   _CONFIG1.Bits.COPRS

#define CONFIG1_COPD_MASK               1
#define CONFIG1_STOP_MASK               2
#define CONFIG1_SSREC_MASK              4
#define CONFIG1_LVIPWRD_MASK            16
#define CONFIG1_LVIRSTD_MASK            32
#define CONFIG1_LVISTOP_MASK            64
#define CONFIG1_COPRS_MASK              128


/*** TSC - TIM Status and Control Register TSC; 0x00000020 ***/
typedef union {
  byte Byte;
  struct {
    byte PS0         :1;                                       /* Prescaler Select Bit 0 */
    byte PS1         :1;                                       /* Prescaler Select Bit 1 */
    byte PS2         :1;                                       /* Prescaler Select Bit 2 */
    byte             :1; 
    byte TRST        :1;                                       /* TIM Reset Bit */
    byte TSTOP       :1;                                       /* TIM Stop Bit */
    byte TOIE        :1;                                       /* TIM Overflow Interrupt Enable Bit */
    byte TOF         :1;                                       /* TIM Overflow Flag Bit */
  } Bits;
  struct {
    byte grpPS   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TSCSTR;
extern volatile TSCSTR _TSC;
#define TSC                             _TSC.Byte
#define TSC_PS0                         _TSC.Bits.PS0
#define TSC_PS1                         _TSC.Bits.PS1
#define TSC_PS2                         _TSC.Bits.PS2
#define TSC_TRST                        _TSC.Bits.TRST
#define TSC_TSTOP                       _TSC.Bits.TSTOP
#define TSC_TOIE                        _TSC.Bits.TOIE
#define TSC_TOF                         _TSC.Bits.TOF
#define TSC_PS                          _TSC.MergedBits.grpPS

#define TSC_PS0_MASK                    1
#define TSC_PS1_MASK                    2
#define TSC_PS2_MASK                    4
#define TSC_TRST_MASK                   16
#define TSC_TSTOP_MASK                  32
#define TSC_TOIE_MASK                   64
#define TSC_TOF_MASK                    128
#define TSC_PS_MASK                     7
#define TSC_PS_BITNUM                   0


/*** TCNT - TIM Counter Register; 0x00000021 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TCNTH - TIM Counter Register High; 0x00000021 ***/
    union {
      byte Byte;
    } TCNTHSTR;
    #define TCNTH                       _TCNT.Overlap_STR.TCNTHSTR.Byte
    

    /*** TCNTL - TIM Counter Register Low; 0x00000022 ***/
    union {
      byte Byte;
    } TCNTLSTR;
    #define TCNTL                       _TCNT.Overlap_STR.TCNTLSTR.Byte
    
  } Overlap_STR;

} TCNTSTR;
extern volatile TCNTSTR _TCNT;
#define TCNT                            _TCNT.Word


/*** TMOD - TIM Counter Modulo Register; 0x00000023 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TMODH - TIM Counter Modulo Register High; 0x00000023 ***/
    union {
      byte Byte;
    } TMODHSTR;
    #define TMODH                       _TMOD.Overlap_STR.TMODHSTR.Byte
    

    /*** TMODL - TIM Counter Modulo Register Low; 0x00000024 ***/
    union {
      byte Byte;
    } TMODLSTR;
    #define TMODL                       _TMOD.Overlap_STR.TMODLSTR.Byte
    
  } Overlap_STR;

} TMODSTR;
extern volatile TMODSTR _TMOD;
#define TMOD                            _TMOD.Word


/*** TSC0 - TIM Channel 0 Status and Control Register; 0x00000025 ***/
typedef union {
  byte Byte;
  struct {
    byte CH0MAX      :1;                                       /* Channel 0 Maximum Duty Cycle Bit */
    byte TOV0        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS0A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS0B       :1;                                       /* Edge/Level Select Bit B */
    byte MS0A        :1;                                       /* Mode Select Bit A */
    byte MS0B        :1;                                       /* Mode Select Bit B */
    byte CH0IE       :1;                                       /* Channel 0 Interrupt Enable Bit */
    byte CH0F        :1;                                       /* Channel 0 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV  :1;
    byte grpELS0x :2;
    byte grpMS0x :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} TSC0STR;
extern volatile TSC0STR _TSC0;
#define TSC0                            _TSC0.Byte
#define TSC0_CH0MAX                     _TSC0.Bits.CH0MAX
#define TSC0_TOV0                       _TSC0.Bits.TOV0
#define TSC0_ELS0A                      _TSC0.Bits.ELS0A
#define TSC0_ELS0B                      _TSC0.Bits.ELS0B
#define TSC0_MS0A                       _TSC0.Bits.MS0A
#define TSC0_MS0B                       _TSC0.Bits.MS0B
#define TSC0_CH0IE                      _TSC0.Bits.CH0IE
#define TSC0_CH0F                       _TSC0.Bits.CH0F
#define TSC0_ELS0x                      _TSC0.MergedBits.grpELS0x
#define TSC0_MS0x                       _TSC0.MergedBits.grpMS0x

#define TSC0_CH0MAX_MASK                1
#define TSC0_TOV0_MASK                  2
#define TSC0_ELS0A_MASK                 4
#define TSC0_ELS0B_MASK                 8
#define TSC0_MS0A_MASK                  16
#define TSC0_MS0B_MASK                  32
#define TSC0_CH0IE_MASK                 64
#define TSC0_CH0F_MASK                  128
#define TSC0_ELS0x_MASK                 12
#define TSC0_ELS0x_BITNUM               2
#define TSC0_MS0x_MASK                  48
#define TSC0_MS0x_BITNUM                4


/*** TCH0 - TIM Channel 0 Register; 0x00000026 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TCH0H - TIM Channel 0 Register High; 0x00000026 ***/
    union {
      byte Byte;
    } TCH0HSTR;
    #define TCH0H                       _TCH0.Overlap_STR.TCH0HSTR.Byte
    

    /*** TCH0L - TIM Channel 0 Register Low; 0x00000027 ***/
    union {
      byte Byte;
    } TCH0LSTR;
    #define TCH0L                       _TCH0.Overlap_STR.TCH0LSTR.Byte
    
  } Overlap_STR;

} TCH0STR;
extern volatile TCH0STR _TCH0;
#define TCH0                            _TCH0.Word


/*** TSC1 - TIM Channel 1 Status and Control Register; 0x00000028 ***/
typedef union {
  byte Byte;
  struct {
    byte CH1MAX      :1;                                       /* Channel 1 Maximum Duty Cycle Bit */
    byte TOV1        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS1A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS1B       :1;                                       /* Edge/Level Select Bit B */
    byte MS1A        :1;                                       /* Mode Select Bit A */
    byte             :1; 
    byte CH1IE       :1;                                       /* Channel 1 Interrupt Enable Bit */
    byte CH1F        :1;                                       /* Channel 1 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_1 :1;
    byte grpELS1x :2;
    byte grpMS1x :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TSC1STR;
extern volatile TSC1STR _TSC1;
#define TSC1                            _TSC1.Byte
#define TSC1_CH1MAX                     _TSC1.Bits.CH1MAX
#define TSC1_TOV1                       _TSC1.Bits.TOV1
#define TSC1_ELS1A                      _TSC1.Bits.ELS1A
#define TSC1_ELS1B                      _TSC1.Bits.ELS1B
#define TSC1_MS1A                       _TSC1.Bits.MS1A
#define TSC1_CH1IE                      _TSC1.Bits.CH1IE
#define TSC1_CH1F                       _TSC1.Bits.CH1F
#define TSC1_ELS1x                      _TSC1.MergedBits.grpELS1x

#define TSC1_CH1MAX_MASK                1
#define TSC1_TOV1_MASK                  2
#define TSC1_ELS1A_MASK                 4
#define TSC1_ELS1B_MASK                 8
#define TSC1_MS1A_MASK                  16
#define TSC1_CH1IE_MASK                 64
#define TSC1_CH1F_MASK                  128
#define TSC1_ELS1x_MASK                 12
#define TSC1_ELS1x_BITNUM               2


/*** TCH1 - TIM Channel 1 Register; 0x00000029 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TCH1H - TIM Channel 1 Register High; 0x00000029 ***/
    union {
      byte Byte;
    } TCH1HSTR;
    #define TCH1H                       _TCH1.Overlap_STR.TCH1HSTR.Byte
    

    /*** TCH1L - TIM Channel 1 Register Low; 0x0000002A ***/
    union {
      byte Byte;
    } TCH1LSTR;
    #define TCH1L                       _TCH1.Overlap_STR.TCH1LSTR.Byte
    
  } Overlap_STR;

} TCH1STR;
extern volatile TCH1STR _TCH1;
#define TCH1                            _TCH1.Word


/*** OSCSTAT - Oscillator Status Register; 0x00000036 ***/
typedef union {
  byte Byte;
  struct {
    byte ECGST       :1;                                       /* External Clock Status Bit */
    byte ECGON       :1;                                       /* External Clock Generator On Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} OSCSTATSTR;
extern volatile OSCSTATSTR _OSCSTAT;
#define OSCSTAT                         _OSCSTAT.Byte
#define OSCSTAT_ECGST                   _OSCSTAT.Bits.ECGST
#define OSCSTAT_ECGON                   _OSCSTAT.Bits.ECGON

#define OSCSTAT_ECGST_MASK              1
#define OSCSTAT_ECGON_MASK              2


/*** OSCTRIM - Oscillator Trim Register; 0x00000038 ***/
typedef union {
  byte Byte;
  struct {
    byte TRIM0       :1;                                       /* Internal Oscillator Trim Factor Bit 0 */
    byte TRIM1       :1;                                       /* Internal Oscillator Trim Factor Bit 1 */
    byte TRIM2       :1;                                       /* Internal Oscillator Trim Factor Bit 2 */
    byte TRIM3       :1;                                       /* Internal Oscillator Trim Factor Bit 3 */
    byte TRIM4       :1;                                       /* Internal Oscillator Trim Factor Bit 4 */
    byte TRIM5       :1;                                       /* Internal Oscillator Trim Factor Bit 5 */
    byte TRIM6       :1;                                       /* Internal Oscillator Trim Factor Bit 6 */
    byte TRIM7       :1;                                       /* Internal Oscillator Trim Factor Bit 7 */
  } Bits;
} OSCTRIMSTR;
extern volatile OSCTRIMSTR _OSCTRIM;
#define OSCTRIM                         _OSCTRIM.Byte
#define OSCTRIM_TRIM0                   _OSCTRIM.Bits.TRIM0
#define OSCTRIM_TRIM1                   _OSCTRIM.Bits.TRIM1
#define OSCTRIM_TRIM2                   _OSCTRIM.Bits.TRIM2
#define OSCTRIM_TRIM3                   _OSCTRIM.Bits.TRIM3
#define OSCTRIM_TRIM4                   _OSCTRIM.Bits.TRIM4
#define OSCTRIM_TRIM5                   _OSCTRIM.Bits.TRIM5
#define OSCTRIM_TRIM6                   _OSCTRIM.Bits.TRIM6
#define OSCTRIM_TRIM7                   _OSCTRIM.Bits.TRIM7

#define OSCTRIM_TRIM0_MASK              1
#define OSCTRIM_TRIM1_MASK              2
#define OSCTRIM_TRIM2_MASK              4
#define OSCTRIM_TRIM3_MASK              8
#define OSCTRIM_TRIM4_MASK              16
#define OSCTRIM_TRIM5_MASK              32
#define OSCTRIM_TRIM6_MASK              64
#define OSCTRIM_TRIM7_MASK              128


/*** OACCR - Operational Amplifier Control Register; 0x00000039 ***/
typedef union {
  byte Byte;
  struct {
    byte OACE        :1;                                       /* Op Amp/Comparator Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte OACM        :1;                                       /* Op Amp/Comparator Mode Select Bit */
  } Bits;
} OACCRSTR;
extern volatile OACCRSTR _OACCR;
#define OACCR                           _OACCR.Byte
#define OACCR_OACE                      _OACCR.Bits.OACE
#define OACCR_OACM                      _OACCR.Bits.OACM

#define OACCR_OACE_MASK                 1
#define OACCR_OACM_MASK                 128


/*** ADSCR - ADC Status and Control Register; 0x0000003C ***/
typedef union {
  byte Byte;
  struct {
    byte ADCH0       :1;                                       /* ADC Channel Select Bit 0 */
    byte ADCH1       :1;                                       /* ADC Channel Select Bit 1 */
    byte ADCH2       :1;                                       /* ADC Channel Select Bit 2 */
    byte ADCH3       :1;                                       /* ADC Channel Select Bit 3 */
    byte ADCH4       :1;                                       /* ADC Channel Select Bit 4 */
    byte ADCO        :1;                                       /* ADC Continuous Conversion Bit */
    byte AIEN        :1;                                       /* ADC Interrupt Enable Bit */
    byte COCO        :1;                                       /* Conversions Complete Bit */
  } Bits;
  struct {
    byte grpADCH :5;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} ADSCRSTR;
extern volatile ADSCRSTR _ADSCR;
#define ADSCR                           _ADSCR.Byte
#define ADSCR_ADCH0                     _ADSCR.Bits.ADCH0
#define ADSCR_ADCH1                     _ADSCR.Bits.ADCH1
#define ADSCR_ADCH2                     _ADSCR.Bits.ADCH2
#define ADSCR_ADCH3                     _ADSCR.Bits.ADCH3
#define ADSCR_ADCH4                     _ADSCR.Bits.ADCH4
#define ADSCR_ADCO                      _ADSCR.Bits.ADCO
#define ADSCR_AIEN                      _ADSCR.Bits.AIEN
#define ADSCR_COCO                      _ADSCR.Bits.COCO
#define ADSCR_ADCH                      _ADSCR.MergedBits.grpADCH

#define ADSCR_ADCH0_MASK                1
#define ADSCR_ADCH1_MASK                2
#define ADSCR_ADCH2_MASK                4
#define ADSCR_ADCH3_MASK                8
#define ADSCR_ADCH4_MASK                16
#define ADSCR_ADCO_MASK                 32
#define ADSCR_AIEN_MASK                 64
#define ADSCR_COCO_MASK                 128
#define ADSCR_ADCH_MASK                 31
#define ADSCR_ADCH_BITNUM               0


/*** ADR - ADC Data Register; 0x0000003E ***/
typedef union {
  byte Byte;
  struct {
    byte AD0         :1;                                       /* ADC Data Bit 0 */
    byte AD1         :1;                                       /* ADC Data Bit 1 */
    byte AD2         :1;                                       /* ADC Data Bit 2 */
    byte AD3         :1;                                       /* ADC Data Bit 3 */
    byte AD4         :1;                                       /* ADC Data Bit 4 */
    byte AD5         :1;                                       /* ADC Data Bit 5 */
    byte AD6         :1;                                       /* ADC Data Bit 6 */
    byte AD7         :1;                                       /* ADC Data Bit 7 */
  } Bits;
} ADRSTR;
extern volatile ADRSTR _ADR;
#define ADR                             _ADR.Byte
#define ADR_AD0                         _ADR.Bits.AD0
#define ADR_AD1                         _ADR.Bits.AD1
#define ADR_AD2                         _ADR.Bits.AD2
#define ADR_AD3                         _ADR.Bits.AD3
#define ADR_AD4                         _ADR.Bits.AD4
#define ADR_AD5                         _ADR.Bits.AD5
#define ADR_AD6                         _ADR.Bits.AD6
#define ADR_AD7                         _ADR.Bits.AD7

#define ADR_AD0_MASK                    1
#define ADR_AD1_MASK                    2
#define ADR_AD2_MASK                    4
#define ADR_AD3_MASK                    8
#define ADR_AD4_MASK                    16
#define ADR_AD5_MASK                    32
#define ADR_AD6_MASK                    64
#define ADR_AD7_MASK                    128


/*** ADCLK - ADC Input Clock Register; 0x0000003F ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte ADIV0       :1;                                       /* ADC Clock Prescaler Bit 0 */
    byte ADIV1       :1;                                       /* ADC Clock Prescaler Bit 1 */
    byte ADIV2       :1;                                       /* ADC Clock Prescaler Bit 2 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpADIV :3;
  } MergedBits;
} ADCLKSTR;
extern volatile ADCLKSTR _ADCLK;
#define ADCLK                           _ADCLK.Byte
#define ADCLK_ADIV0                     _ADCLK.Bits.ADIV0
#define ADCLK_ADIV1                     _ADCLK.Bits.ADIV1
#define ADCLK_ADIV2                     _ADCLK.Bits.ADIV2
#define ADCLK_ADIV                      _ADCLK.MergedBits.grpADIV

#define ADCLK_ADIV0_MASK                32
#define ADCLK_ADIV1_MASK                64
#define ADCLK_ADIV2_MASK                128
#define ADCLK_ADIV_MASK                 224
#define ADCLK_ADIV_BITNUM               5


/*** PCTL1 - PWM Control Register 1; 0x00000040 ***/
typedef union {
  byte Byte;
  struct {
    byte PWMEN       :1;                                       /* PWM Module Enable Bit */
    byte LDOK        :1;                                       /* Load OK Bit */
    byte             :1; 
    byte             :1; 
    byte PWMF        :1;                                       /* PWM Reload Flag */
    byte PWMINT      :1;                                       /* PWM Interrupt Enable Bit */
    byte FPOS        :1;                                       /* Fault Pin Position Bit */
    byte             :1; 
  } Bits;
} PCTL1STR;
extern volatile PCTL1STR _PCTL1;
#define PCTL1                           _PCTL1.Byte
#define PCTL1_PWMEN                     _PCTL1.Bits.PWMEN
#define PCTL1_LDOK                      _PCTL1.Bits.LDOK
#define PCTL1_PWMF                      _PCTL1.Bits.PWMF
#define PCTL1_PWMINT                    _PCTL1.Bits.PWMINT
#define PCTL1_FPOS                      _PCTL1.Bits.FPOS

#define PCTL1_PWMEN_MASK                1
#define PCTL1_LDOK_MASK                 2
#define PCTL1_PWMF_MASK                 16
#define PCTL1_PWMINT_MASK               32
#define PCTL1_FPOS_MASK                 64


/*** PCTL2 - PWM Control Register 2; 0x00000041 ***/
typedef union {
  byte Byte;
  struct {
    byte PRSC0       :1;                                       /* PWM Prescaler Bit 0 */
    byte PRSC1       :1;                                       /* PWM Prescaler Bit 1 */
    byte POL0        :1;                                       /* Polarity Bit for PWM0 */
    byte POL1        :1;                                       /* Polarity Bit for PWM1 */
    byte DIS0        :1;                                       /* Software Disable Bit for PWM0 */
    byte DIS1        :1;                                       /* Software Disable Bit for PWM1 */
    byte LDFQ0       :1;                                       /* PWM Load Frequency Bit 0 */
    byte LDFQ1       :1;                                       /* PWM Load Frequency Bit 1 */
  } Bits;
  struct {
    byte grpPRSC :2;
    byte grpPOL  :2;
    byte grpDIS  :2;
    byte grpLDFQ :2;
  } MergedBits;
} PCTL2STR;
extern volatile PCTL2STR _PCTL2;
#define PCTL2                           _PCTL2.Byte
#define PCTL2_PRSC0                     _PCTL2.Bits.PRSC0
#define PCTL2_PRSC1                     _PCTL2.Bits.PRSC1
#define PCTL2_POL0                      _PCTL2.Bits.POL0
#define PCTL2_POL1                      _PCTL2.Bits.POL1
#define PCTL2_DIS0                      _PCTL2.Bits.DIS0
#define PCTL2_DIS1                      _PCTL2.Bits.DIS1
#define PCTL2_LDFQ0                     _PCTL2.Bits.LDFQ0
#define PCTL2_LDFQ1                     _PCTL2.Bits.LDFQ1
#define PCTL2_PRSC                      _PCTL2.MergedBits.grpPRSC
#define PCTL2_POL                       _PCTL2.MergedBits.grpPOL
#define PCTL2_DIS                       _PCTL2.MergedBits.grpDIS
#define PCTL2_LDFQ                      _PCTL2.MergedBits.grpLDFQ

#define PCTL2_PRSC0_MASK                1
#define PCTL2_PRSC1_MASK                2
#define PCTL2_POL0_MASK                 4
#define PCTL2_POL1_MASK                 8
#define PCTL2_DIS0_MASK                 16
#define PCTL2_DIS1_MASK                 32
#define PCTL2_LDFQ0_MASK                64
#define PCTL2_LDFQ1_MASK                128
#define PCTL2_PRSC_MASK                 3
#define PCTL2_PRSC_BITNUM               0
#define PCTL2_POL_MASK                  12
#define PCTL2_POL_BITNUM                2
#define PCTL2_DIS_MASK                  48
#define PCTL2_DIS_BITNUM                4
#define PCTL2_LDFQ_MASK                 192
#define PCTL2_LDFQ_BITNUM               6


/*** FCR - Fault Control Register; 0x00000042 ***/
typedef union {
  byte Byte;
  struct {
    byte FMODE       :1;                                       /* Fault Mode Selection for Fault Pin Bit (automatic versus manual mode) */
    byte FINT        :1;                                       /* Fault Interrupt Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} FCRSTR;
extern volatile FCRSTR _FCR;
#define FCR                             _FCR.Byte
#define FCR_FMODE                       _FCR.Bits.FMODE
#define FCR_FINT                        _FCR.Bits.FINT

#define FCR_FMODE_MASK                  1
#define FCR_FINT_MASK                   2


/*** FSR - Fault Status Register; 0x00000043 ***/
typedef union {
  byte Byte;
  struct {
    byte FFLAG       :1;                                       /* Fault Event Flag */
    byte FPIN        :1;                                       /* State of Fault Pin Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} FSRSTR;
extern volatile FSRSTR _FSR;
#define FSR                             _FSR.Byte
#define FSR_FFLAG                       _FSR.Bits.FFLAG
#define FSR_FPIN                        _FSR.Bits.FPIN

#define FSR_FFLAG_MASK                  1
#define FSR_FPIN_MASK                   2


/*** FCR2 - Fault Control Register 2; 0x00000044 ***/
typedef union {
  byte Byte;
  struct {
    byte FTACK       :1;                                       /* Fault Acknowledge Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} FCR2STR;
extern volatile FCR2STR _FCR2;
#define FCR2                            _FCR2.Byte
#define FCR2_FTACK                      _FCR2.Bits.FTACK

#define FCR2_FTACK_MASK                 1


/*** PCNT - PWM Counter Register; 0x00000045 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PCNTH - PWM Counter Register High; 0x00000045 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* PWM Counter Bit 8 */
        byte BIT9        :1;                                       /* PWM Counter Bit 9 */
        byte BIT10       :1;                                       /* PWM Counter Bit 10 */
        byte BIT11       :1;                                       /* PWM Counter Bit 11 */
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
      } Bits;
      struct {
        byte grpBIT_8 :4;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
      } MergedBits;
    } PCNTHSTR;
    #define PCNTH                       _PCNT.Overlap_STR.PCNTHSTR.Byte
    #define PCNTH_BIT8                  _PCNT.Overlap_STR.PCNTHSTR.Bits.BIT8
    #define PCNTH_BIT9                  _PCNT.Overlap_STR.PCNTHSTR.Bits.BIT9
    #define PCNTH_BIT10                 _PCNT.Overlap_STR.PCNTHSTR.Bits.BIT10
    #define PCNTH_BIT11                 _PCNT.Overlap_STR.PCNTHSTR.Bits.BIT11
    #define PCNTH_BIT_8                 _PCNT.Overlap_STR.PCNTHSTR.MergedBits.grpBIT_8
    #define PCNTH_BIT                   PCNTH_BIT_8
    
    #define PCNTH_BIT8_MASK             1
    #define PCNTH_BIT9_MASK             2
    #define PCNTH_BIT10_MASK            4
    #define PCNTH_BIT11_MASK            8
    #define PCNTH_BIT_8_MASK            15
    #define PCNTH_BIT_8_BITNUM          0
    

    /*** PCNTL - PWM Counter Register Low; 0x00000046 ***/
    union {
      byte Byte;
    } PCNTLSTR;
    #define PCNTL                       _PCNT.Overlap_STR.PCNTLSTR.Byte
    
  } Overlap_STR;

} PCNTSTR;
extern volatile PCNTSTR _PCNT;
#define PCNT                            _PCNT.Word


/*** PMOD - PWM Counter Modulo Register; 0x00000047 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PMODH - PWM Counter Modulo Register High; 0x00000047 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* PWM Counter Modulo Bit 8 */
        byte BIT9        :1;                                       /* PWM Counter Modulo Bit 9 */
        byte BIT10       :1;                                       /* PWM Counter Modulo Bit 10 */
        byte BIT11       :1;                                       /* PWM Counter Modulo Bit 11 */
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
      } Bits;
      struct {
        byte grpBIT_8 :4;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
      } MergedBits;
    } PMODHSTR;
    #define PMODH                       _PMOD.Overlap_STR.PMODHSTR.Byte
    #define PMODH_BIT8                  _PMOD.Overlap_STR.PMODHSTR.Bits.BIT8
    #define PMODH_BIT9                  _PMOD.Overlap_STR.PMODHSTR.Bits.BIT9
    #define PMODH_BIT10                 _PMOD.Overlap_STR.PMODHSTR.Bits.BIT10
    #define PMODH_BIT11                 _PMOD.Overlap_STR.PMODHSTR.Bits.BIT11
    #define PMODH_BIT_8                 _PMOD.Overlap_STR.PMODHSTR.MergedBits.grpBIT_8
    #define PMODH_BIT                   PMODH_BIT_8
    
    #define PMODH_BIT8_MASK             1
    #define PMODH_BIT9_MASK             2
    #define PMODH_BIT10_MASK            4
    #define PMODH_BIT11_MASK            8
    #define PMODH_BIT_8_MASK            15
    #define PMODH_BIT_8_BITNUM          0
    

    /*** PMODL - PWM Counter Modulo Register Low; 0x00000048 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* PWM Counter Modulo Bit 0 */
        byte BIT1        :1;                                       /* PWM Counter Modulo Bit 1 */
        byte BIT2        :1;                                       /* PWM Counter Modulo Bit 2 */
        byte BIT3        :1;                                       /* PWM Counter Modulo Bit 3 */
        byte BIT4        :1;                                       /* PWM Counter Modulo Bit 4 */
        byte BIT5        :1;                                       /* PWM Counter Modulo Bit 5 */
        byte BIT6        :1;                                       /* PWM Counter Modulo Bit 6 */
        byte BIT7        :1;                                       /* PWM Counter Modulo Bit 7 */
      } Bits;
    } PMODLSTR;
    #define PMODL                       _PMOD.Overlap_STR.PMODLSTR.Byte
    #define PMODL_BIT0                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT0
    #define PMODL_BIT1                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT1
    #define PMODL_BIT2                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT2
    #define PMODL_BIT3                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT3
    #define PMODL_BIT4                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT4
    #define PMODL_BIT5                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT5
    #define PMODL_BIT6                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT6
    #define PMODL_BIT7                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT7
    
    #define PMODL_BIT0_MASK             1
    #define PMODL_BIT1_MASK             2
    #define PMODL_BIT2_MASK             4
    #define PMODL_BIT3_MASK             8
    #define PMODL_BIT4_MASK             16
    #define PMODL_BIT5_MASK             32
    #define PMODL_BIT6_MASK             64
    #define PMODL_BIT7_MASK             128
    
  } Overlap_STR;

} PMODSTR;
extern volatile PMODSTR _PMOD;
#define PMOD                            _PMOD.Word


/*** PVAL0 - PWM0 Value Registers; 0x00000049 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PVAL0H - PWM0 Value Registers High; 0x00000049 ***/
    union {
      byte Byte;
    } PVAL0HSTR;
    #define PVAL0H                      _PVAL0.Overlap_STR.PVAL0HSTR.Byte
    

    /*** PVAL0L - PWM0 Value Registers Low; 0x0000004A ***/
    union {
      byte Byte;
    } PVAL0LSTR;
    #define PVAL0L                      _PVAL0.Overlap_STR.PVAL0LSTR.Byte
    
  } Overlap_STR;

} PVAL0STR;
extern volatile PVAL0STR _PVAL0;
#define PVAL0                           _PVAL0.Word
/* PVAL_ARR: Access 2 PVALx registers in an array */
#define PVAL_ARR                        ((volatile word * __far) &PVAL0)


/*** PVAL1 - PWM1 Value Registers; 0x0000004B ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PVAL1H - PWM1 Value Registers High; 0x0000004B ***/
    union {
      byte Byte;
    } PVAL1HSTR;
    #define PVAL1H                      _PVAL1.Overlap_STR.PVAL1HSTR.Byte
    

    /*** PVAL1L - PWM1 Value Registers Low; 0x0000004C ***/
    union {
      byte Byte;
    } PVAL1LSTR;
    #define PVAL1L                      _PVAL1.Overlap_STR.PVAL1LSTR.Byte
    
  } Overlap_STR;

} PVAL1STR;
extern volatile PVAL1STR _PVAL1;
#define PVAL1                           _PVAL1.Word


/*** DISMAP - PWM Disable Mapping Write-Once Register; 0x0000004D ***/
typedef union {
  byte Byte;
  struct {
    byte MAP0        :1;                                       /* Disable Map for PWM0 Bit */
    byte MAP1        :1;                                       /* Disable Map for PWM1 Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpMAP  :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DISMAPSTR;
extern volatile DISMAPSTR _DISMAP;
#define DISMAP                          _DISMAP.Byte
#define DISMAP_MAP0                     _DISMAP.Bits.MAP0
#define DISMAP_MAP1                     _DISMAP.Bits.MAP1
#define DISMAP_MAP                      _DISMAP.MergedBits.grpMAP

#define DISMAP_MAP0_MASK                1
#define DISMAP_MAP1_MASK                2
#define DISMAP_MAP_MASK                 3
#define DISMAP_MAP_BITNUM               0


/*** HRPCTRL - HRP Control Register; 0x00000051 ***/
typedef union {
  byte Byte;
  struct {
    byte HRPEN       :1;                                       /* HRP Enable */
    byte HRPMODE     :1;                                       /* Mode Select */
    byte SHTEN       :1;                                       /* Shutdown Pin Enable */
    byte SHTIE       :1;                                       /* SHTDWN Interrupt Enable */
    byte SHTIF       :1;                                       /* SHTDWN Interrupt Flag */
    byte HRPOE       :1;                                       /* HRP Output Enable */
    byte SHTLVL      :1;                                       /* SHTDWN Pin Level */
    byte             :1; 
  } Bits;
} HRPCTRLSTR;
extern volatile HRPCTRLSTR _HRPCTRL;
#define HRPCTRL                         _HRPCTRL.Byte
#define HRPCTRL_HRPEN                   _HRPCTRL.Bits.HRPEN
#define HRPCTRL_HRPMODE                 _HRPCTRL.Bits.HRPMODE
#define HRPCTRL_SHTEN                   _HRPCTRL.Bits.SHTEN
#define HRPCTRL_SHTIE                   _HRPCTRL.Bits.SHTIE
#define HRPCTRL_SHTIF                   _HRPCTRL.Bits.SHTIF
#define HRPCTRL_HRPOE                   _HRPCTRL.Bits.HRPOE
#define HRPCTRL_SHTLVL                  _HRPCTRL.Bits.SHTLVL

#define HRPCTRL_HRPEN_MASK              1
#define HRPCTRL_HRPMODE_MASK            2
#define HRPCTRL_SHTEN_MASK              4
#define HRPCTRL_SHTIE_MASK              8
#define HRPCTRL_SHTIF_MASK              16
#define HRPCTRL_HRPOE_MASK              32
#define HRPCTRL_SHTLVL_MASK             64


/*** HRPDC - HRP Duty Cycle Registers; 0x00000052 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** HRPDCH - HRP Duty Cycle Registers High; 0x00000052 ***/
    union {
      byte Byte;
    } HRPDCHSTR;
    #define HRPDCH                      _HRPDC.Overlap_STR.HRPDCHSTR.Byte
    

    /*** HRPDCL - HRP Duty Cycle Registers Low; 0x00000053 ***/
    union {
      byte Byte;
      struct {
        byte STEP0       :1;                                       /* Dithering Step Value Bit 0 */
        byte STEP1       :1;                                       /* Dithering Step Value Bit 1 */
        byte STEP2       :1;                                       /* Dithering Step Value Bit 2 */
        byte STEP3       :1;                                       /* Dithering Step Value Bit 3 */
        byte STEP4       :1;                                       /* Dithering Step Value Bit 4 */
        byte DC0         :1;                                       /* Duty Cycle Value Bit 0 */
        byte DC1         :1;                                       /* Duty Cycle Value Bit 1 */
        byte DC2         :1;                                       /* Duty Cycle Value Bit 2 */
      } Bits;
      struct {
        byte grpSTEP :5;
        byte grpDC :3;
      } MergedBits;
    } HRPDCLSTR;
    #define HRPDCL                      _HRPDC.Overlap_STR.HRPDCLSTR.Byte
    #define HRPDCL_STEP0                _HRPDC.Overlap_STR.HRPDCLSTR.Bits.STEP0
    #define HRPDCL_STEP1                _HRPDC.Overlap_STR.HRPDCLSTR.Bits.STEP1
    #define HRPDCL_STEP2                _HRPDC.Overlap_STR.HRPDCLSTR.Bits.STEP2
    #define HRPDCL_STEP3                _HRPDC.Overlap_STR.HRPDCLSTR.Bits.STEP3
    #define HRPDCL_STEP4                _HRPDC.Overlap_STR.HRPDCLSTR.Bits.STEP4
    #define HRPDCL_DC0                  _HRPDC.Overlap_STR.HRPDCLSTR.Bits.DC0
    #define HRPDCL_DC1                  _HRPDC.Overlap_STR.HRPDCLSTR.Bits.DC1
    #define HRPDCL_DC2                  _HRPDC.Overlap_STR.HRPDCLSTR.Bits.DC2
    #define HRPDCL_STEP                 _HRPDC.Overlap_STR.HRPDCLSTR.MergedBits.grpSTEP
    #define HRPDCL_DC                   _HRPDC.Overlap_STR.HRPDCLSTR.MergedBits.grpDC
    
    #define HRPDCL_STEP0_MASK           1
    #define HRPDCL_STEP1_MASK           2
    #define HRPDCL_STEP2_MASK           4
    #define HRPDCL_STEP3_MASK           8
    #define HRPDCL_STEP4_MASK           16
    #define HRPDCL_DC0_MASK             32
    #define HRPDCL_DC1_MASK             64
    #define HRPDCL_DC2_MASK             128
    #define HRPDCL_STEP_MASK            31
    #define HRPDCL_STEP_BITNUM          0
    #define HRPDCL_DC_MASK              224
    #define HRPDCL_DC_BITNUM            5
    
  } Overlap_STR;

} HRPDCSTR;
extern volatile HRPDCSTR _HRPDC;
#define HRPDC                           _HRPDC.Word


/*** HRPPER - HRP Period Registers; 0x00000054 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** HRPPERH - HRP Period Registers High; 0x00000054 ***/
    union {
      byte Byte;
    } HRPPERHSTR;
    #define HRPPERH                     _HRPPER.Overlap_STR.HRPPERHSTR.Byte
    

    /*** HRPPERL - HRP Period Registers Low; 0x00000055 ***/
    union {
      byte Byte;
      struct {
        byte STEP0       :1;                                       /* Dithering Step Value Bit 0 */
        byte STEP1       :1;                                       /* Dithering Step Value Bit 1 */
        byte STEP2       :1;                                       /* Dithering Step Value Bit 2 */
        byte STEP3       :1;                                       /* Dithering Step Value Bit 3 */
        byte STEP4       :1;                                       /* Dithering Step Value Bit 4 */
        byte P0          :1;                                       /* Period Value Bit 0 */
        byte P1          :1;                                       /* Period Value Bit 1 */
        byte P2          :1;                                       /* Period Value Bit 2 */
      } Bits;
      struct {
        byte grpSTEP :5;
        byte grpP :3;
      } MergedBits;
    } HRPPERLSTR;
    #define HRPPERL                     _HRPPER.Overlap_STR.HRPPERLSTR.Byte
    #define HRPPERL_STEP0               _HRPPER.Overlap_STR.HRPPERLSTR.Bits.STEP0
    #define HRPPERL_STEP1               _HRPPER.Overlap_STR.HRPPERLSTR.Bits.STEP1
    #define HRPPERL_STEP2               _HRPPER.Overlap_STR.HRPPERLSTR.Bits.STEP2
    #define HRPPERL_STEP3               _HRPPER.Overlap_STR.HRPPERLSTR.Bits.STEP3
    #define HRPPERL_STEP4               _HRPPER.Overlap_STR.HRPPERLSTR.Bits.STEP4
    #define HRPPERL_P0                  _HRPPER.Overlap_STR.HRPPERLSTR.Bits.P0
    #define HRPPERL_P1                  _HRPPER.Overlap_STR.HRPPERLSTR.Bits.P1
    #define HRPPERL_P2                  _HRPPER.Overlap_STR.HRPPERLSTR.Bits.P2
    #define HRPPERL_STEP                _HRPPER.Overlap_STR.HRPPERLSTR.MergedBits.grpSTEP
    #define HRPPERL_P                   _HRPPER.Overlap_STR.HRPPERLSTR.MergedBits.grpP
    
    #define HRPPERL_STEP0_MASK          1
    #define HRPPERL_STEP1_MASK          2
    #define HRPPERL_STEP2_MASK          4
    #define HRPPERL_STEP3_MASK          8
    #define HRPPERL_STEP4_MASK          16
    #define HRPPERL_P0_MASK             32
    #define HRPPERL_P1_MASK             64
    #define HRPPERL_P2_MASK             128
    #define HRPPERL_STEP_MASK           31
    #define HRPPERL_STEP_BITNUM         0
    #define HRPPERL_P_MASK              224
    #define HRPPERL_P_BITNUM            5
    
  } Overlap_STR;

} HRPPERSTR;
extern volatile HRPPERSTR _HRPPER;
#define HRPPER                          _HRPPER.Word


/*** HRPDT - HRP Dead Time Register; 0x00000056 ***/
typedef union {
  byte Byte;
  struct {
    byte DT0         :1;                                       /* HRP Dead Time Bit 0 */
    byte DT1         :1;                                       /* HRP Dead Time Bit 1 */
    byte DT2         :1;                                       /* HRP Dead Time Bit 2 */
    byte DT3         :1;                                       /* HRP Dead Time Bit 3 */
    byte DT4         :1;                                       /* HRP Dead Time Bit 4 */
    byte DT5         :1;                                       /* HRP Dead Time Bit 5 */
    byte DT6         :1;                                       /* HRP Dead Time Bit 6 */
    byte DT7         :1;                                       /* HRP Dead Time Bit 7 */
  } Bits;
} HRPDTSTR;
extern volatile HRPDTSTR _HRPDT;
#define HRPDT                           _HRPDT.Byte
#define HRPDT_DT0                       _HRPDT.Bits.DT0
#define HRPDT_DT1                       _HRPDT.Bits.DT1
#define HRPDT_DT2                       _HRPDT.Bits.DT2
#define HRPDT_DT3                       _HRPDT.Bits.DT3
#define HRPDT_DT4                       _HRPDT.Bits.DT4
#define HRPDT_DT5                       _HRPDT.Bits.DT5
#define HRPDT_DT6                       _HRPDT.Bits.DT6
#define HRPDT_DT7                       _HRPDT.Bits.DT7

#define HRPDT_DT0_MASK                  1
#define HRPDT_DT1_MASK                  2
#define HRPDT_DT2_MASK                  4
#define HRPDT_DT3_MASK                  8
#define HRPDT_DT4_MASK                  16
#define HRPDT_DT5_MASK                  32
#define HRPDT_DT6_MASK                  64
#define HRPDT_DT7_MASK                  128


/*** HRPTB - HRP Timebase Register; 0x00000057 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** HRPTBH - HRP Timebase Register High; 0x00000057 ***/
    union {
      byte Byte;
      struct {
        byte TB8         :1;                                       /* HRP Timebase Bit 8 */
        byte TB9         :1;                                       /* HRP Timebase Bit 9 */
        byte TB10        :1;                                       /* HRP Timebase Bit 10 */
        byte TB11        :1;                                       /* HRP Timebase Bit 11 */
        byte TB12        :1;                                       /* HRP Timebase Bit 12 */
        byte TB13        :1;                                       /* HRP Timebase Bit 13 */
        byte TB14        :1;                                       /* HRP Timebase Bit 14 */
        byte TB15        :1;                                       /* HRP Timebase Bit 15 */
      } Bits;
    } HRPTBHSTR;
    #define HRPTBH                      _HRPTB.Overlap_STR.HRPTBHSTR.Byte
    #define HRPTBH_TB8                  _HRPTB.Overlap_STR.HRPTBHSTR.Bits.TB8
    #define HRPTBH_TB9                  _HRPTB.Overlap_STR.HRPTBHSTR.Bits.TB9
    #define HRPTBH_TB10                 _HRPTB.Overlap_STR.HRPTBHSTR.Bits.TB10
    #define HRPTBH_TB11                 _HRPTB.Overlap_STR.HRPTBHSTR.Bits.TB11
    #define HRPTBH_TB12                 _HRPTB.Overlap_STR.HRPTBHSTR.Bits.TB12
    #define HRPTBH_TB13                 _HRPTB.Overlap_STR.HRPTBHSTR.Bits.TB13
    #define HRPTBH_TB14                 _HRPTB.Overlap_STR.HRPTBHSTR.Bits.TB14
    #define HRPTBH_TB15                 _HRPTB.Overlap_STR.HRPTBHSTR.Bits.TB15
    
    #define HRPTBH_TB8_MASK             1
    #define HRPTBH_TB9_MASK             2
    #define HRPTBH_TB10_MASK            4
    #define HRPTBH_TB11_MASK            8
    #define HRPTBH_TB12_MASK            16
    #define HRPTBH_TB13_MASK            32
    #define HRPTBH_TB14_MASK            64
    #define HRPTBH_TB15_MASK            128
    

    /*** HRPTBL - HRP Timebase Register Low; 0x00000058 ***/
    union {
      byte Byte;
      struct {
        byte TB0         :1;                                       /* HRP Timebase Bit 0 */
        byte TB1         :1;                                       /* HRP Timebase Bit 1 */
        byte TB2         :1;                                       /* HRP Timebase Bit 2 */
        byte TB3         :1;                                       /* HRP Timebase Bit 3 */
        byte TB4         :1;                                       /* HRP Timebase Bit 4 */
        byte TB5         :1;                                       /* HRP Timebase Bit 5 */
        byte TB6         :1;                                       /* HRP Timebase Bit 6 */
        byte TB7         :1;                                       /* HRP Timebase Bit 7 */
      } Bits;
    } HRPTBLSTR;
    #define HRPTBL                      _HRPTB.Overlap_STR.HRPTBLSTR.Byte
    #define HRPTBL_TB0                  _HRPTB.Overlap_STR.HRPTBLSTR.Bits.TB0
    #define HRPTBL_TB1                  _HRPTB.Overlap_STR.HRPTBLSTR.Bits.TB1
    #define HRPTBL_TB2                  _HRPTB.Overlap_STR.HRPTBLSTR.Bits.TB2
    #define HRPTBL_TB3                  _HRPTB.Overlap_STR.HRPTBLSTR.Bits.TB3
    #define HRPTBL_TB4                  _HRPTB.Overlap_STR.HRPTBLSTR.Bits.TB4
    #define HRPTBL_TB5                  _HRPTB.Overlap_STR.HRPTBLSTR.Bits.TB5
    #define HRPTBL_TB6                  _HRPTB.Overlap_STR.HRPTBLSTR.Bits.TB6
    #define HRPTBL_TB7                  _HRPTB.Overlap_STR.HRPTBLSTR.Bits.TB7
    
    #define HRPTBL_TB0_MASK             1
    #define HRPTBL_TB1_MASK             2
    #define HRPTBL_TB2_MASK             4
    #define HRPTBL_TB3_MASK             8
    #define HRPTBL_TB4_MASK             16
    #define HRPTBL_TB5_MASK             32
    #define HRPTBL_TB6_MASK             64
    #define HRPTBL_TB7_MASK             128
    
  } Overlap_STR;

} HRPTBSTR;
extern volatile HRPTBSTR _HRPTB;
#define HRPTB                           _HRPTB.Word


/*** HRPDCR - Frequency Dithering Control Register; 0x00000059 ***/
typedef union {
  byte Byte;
  struct {
    byte SEL0        :1;                                       /* Dithering Step/Modulus Select Bit 0 */
    byte SEL1        :1;                                       /* Dithering Step/Modulus Select Bit 1 */
    byte SEL2        :1;                                       /* Dithering Step/Modulus Select Bit 2 */
    byte CLKSRC      :1;                                       /* Dithering Clock Source */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpSEL  :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} HRPDCRSTR;
extern volatile HRPDCRSTR _HRPDCR;
#define HRPDCR                          _HRPDCR.Byte
#define HRPDCR_SEL0                     _HRPDCR.Bits.SEL0
#define HRPDCR_SEL1                     _HRPDCR.Bits.SEL1
#define HRPDCR_SEL2                     _HRPDCR.Bits.SEL2
#define HRPDCR_CLKSRC                   _HRPDCR.Bits.CLKSRC
#define HRPDCR_SEL                      _HRPDCR.MergedBits.grpSEL

#define HRPDCR_SEL0_MASK                1
#define HRPDCR_SEL1_MASK                2
#define HRPDCR_SEL2_MASK                4
#define HRPDCR_CLKSRC_MASK              8
#define HRPDCR_SEL_MASK                 7
#define HRPDCR_SEL_BITNUM               0


/*** BSR - Break Status Register; 0x0000FE00 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte SBSW        :1;                                       /* SIM Break Stop/Wait */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} BSRSTR;
extern volatile BSRSTR _BSR;
#define BSR                             _BSR.Byte
#define BSR_SBSW                        _BSR.Bits.SBSW

#define BSR_SBSW_MASK                   2


/*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte LVI         :1;                                       /* Low-Voltage Inhibit Reset Bit */
    byte MODRST      :1;                                       /* Monitor Mode Entry Module Reset Bit */
    byte ILAD        :1;                                       /* Illegal Address Reset Bit */
    byte ILOP        :1;                                       /* Illegal Opcode Reset Bit */
    byte COP         :1;                                       /* Computer Operating Properly Reset Bit */
    byte PIN         :1;                                       /* External Reset Bit */
    byte POR         :1;                                       /* Power-On Reset Bit */
  } Bits;
} SRSRSTR;
extern volatile SRSRSTR _SRSR;
#define SRSR                            _SRSR.Byte
#define SRSR_LVI                        _SRSR.Bits.LVI
#define SRSR_MODRST                     _SRSR.Bits.MODRST
#define SRSR_ILAD                       _SRSR.Bits.ILAD
#define SRSR_ILOP                       _SRSR.Bits.ILOP
#define SRSR_COP                        _SRSR.Bits.COP
#define SRSR_PIN                        _SRSR.Bits.PIN
#define SRSR_POR                        _SRSR.Bits.POR

#define SRSR_LVI_MASK                   2
#define SRSR_MODRST_MASK                4
#define SRSR_ILAD_MASK                  8
#define SRSR_ILOP_MASK                  16
#define SRSR_COP_MASK                   32
#define SRSR_PIN_MASK                   64
#define SRSR_POR_MASK                   128


/*** BRKAR - Break Auxiliary Register; 0x0000FE02 ***/
typedef union {
  byte Byte;
  struct {
    byte BDCOP       :1;                                       /* Break Disable COP Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} BRKARSTR;
extern volatile BRKARSTR _BRKAR;
#define BRKAR                           _BRKAR.Byte
#define BRKAR_BDCOP                     _BRKAR.Bits.BDCOP

#define BRKAR_BDCOP_MASK                1


/*** BFCR - Break Flag Control Register; 0x0000FE03 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BCFE        :1;                                       /* Break Clear Flag Enable Bit */
  } Bits;
} BFCRSTR;
extern volatile BFCRSTR _BFCR;
#define BFCR                            _BFCR.Byte
#define BFCR_BCFE                       _BFCR.Bits.BCFE

#define BFCR_BCFE_MASK                  128


/*** FLCR - FLASH Control Register; 0x0000FE08 ***/
typedef union {
  byte Byte;
  struct {
    byte PGM         :1;                                       /* Program Control Bit */
    byte ERASE       :1;                                       /* Erase Control Bit */
    byte MASS        :1;                                       /* Mass Erase Control Bit */
    byte HVEN        :1;                                       /* High-Voltage Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} FLCRSTR;
extern volatile FLCRSTR _FLCR;
#define FLCR                            _FLCR.Byte
#define FLCR_PGM                        _FLCR.Bits.PGM
#define FLCR_ERASE                      _FLCR.Bits.ERASE
#define FLCR_MASS                       _FLCR.Bits.MASS
#define FLCR_HVEN                       _FLCR.Bits.HVEN

#define FLCR_PGM_MASK                   1
#define FLCR_ERASE_MASK                 2
#define FLCR_MASS_MASK                  4
#define FLCR_HVEN_MASK                  8


/*** BRK - Break Address Register; 0x0000FE09 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** BRKH - Break Address Register High; 0x0000FE09 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Break Address Register Bit 8 */
        byte BIT9        :1;                                       /* Break Address Register Bit 9 */
        byte BIT10       :1;                                       /* Break Address Register Bit 10 */
        byte BIT11       :1;                                       /* Break Address Register Bit 11 */
        byte BIT12       :1;                                       /* Break Address Register Bit 12 */
        byte BIT13       :1;                                       /* Break Address Register Bit 13 */
        byte BIT14       :1;                                       /* Break Address Register Bit 14 */
        byte BIT15       :1;                                       /* Break Address Register Bit 15 */
      } Bits;
    } BRKHSTR;
    #define BRKH                        _BRK.Overlap_STR.BRKHSTR.Byte
    #define BRKH_BIT8                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT8
    #define BRKH_BIT9                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT9
    #define BRKH_BIT10                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT10
    #define BRKH_BIT11                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT11
    #define BRKH_BIT12                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT12
    #define BRKH_BIT13                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT13
    #define BRKH_BIT14                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT14
    #define BRKH_BIT15                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT15
    
    #define BRKH_BIT8_MASK              1
    #define BRKH_BIT9_MASK              2
    #define BRKH_BIT10_MASK             4
    #define BRKH_BIT11_MASK             8
    #define BRKH_BIT12_MASK             16
    #define BRKH_BIT13_MASK             32
    #define BRKH_BIT14_MASK             64
    #define BRKH_BIT15_MASK             128
    

    /*** BRKL - Break Address Register Low; 0x0000FE0A ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Break Address Register Bit 0 */
        byte BIT1        :1;                                       /* Break Address Register Bit 1 */
        byte BIT2        :1;                                       /* Break Address Register Bit 2 */
        byte BIT3        :1;                                       /* Break Address Register Bit 3 */
        byte BIT4        :1;                                       /* Break Address Register Bit 4 */
        byte BIT5        :1;                                       /* Break Address Register Bit 5 */
        byte BIT6        :1;                                       /* Break Address Register Bit 6 */
        byte BIT7        :1;                                       /* Break Address Register Bit 7 */
      } Bits;
    } BRKLSTR;
    #define BRKL                        _BRK.Overlap_STR.BRKLSTR.Byte
    #define BRKL_BIT0                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT0
    #define BRKL_BIT1                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT1
    #define BRKL_BIT2                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT2
    #define BRKL_BIT3                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT3
    #define BRKL_BIT4                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT4
    #define BRKL_BIT5                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT5
    #define BRKL_BIT6                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT6
    #define BRKL_BIT7                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT7
    
    #define BRKL_BIT0_MASK              1
    #define BRKL_BIT1_MASK              2
    #define BRKL_BIT2_MASK              4
    #define BRKL_BIT3_MASK              8
    #define BRKL_BIT4_MASK              16
    #define BRKL_BIT5_MASK              32
    #define BRKL_BIT6_MASK              64
    #define BRKL_BIT7_MASK              128
    
  } Overlap_STR;

} BRKSTR;
extern volatile BRKSTR _BRK;
#define BRK                             _BRK.Word


/*** BRKSCR - Break Status and Control Register; 0x0000FE0B ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BRKA        :1;                                       /* Break Active Bit */
    byte BRKE        :1;                                       /* Break Enable Bit */
  } Bits;
} BRKSCRSTR;
extern volatile BRKSCRSTR _BRKSCR;
#define BRKSCR                          _BRKSCR.Byte
#define BRKSCR_BRKA                     _BRKSCR.Bits.BRKA
#define BRKSCR_BRKE                     _BRKSCR.Bits.BRKE

#define BRKSCR_BRKA_MASK                64
#define BRKSCR_BRKE_MASK                128


/*** LVISR - LVI Status Register; 0x0000FE0C ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte LVIOUT      :1;                                       /* LVI Output Bit */
  } Bits;
} LVISRSTR;
extern volatile LVISRSTR _LVISR;
#define LVISR                           _LVISR.Byte
#define LVISR_LVIOUT                    _LVISR.Bits.LVIOUT

#define LVISR_LVIOUT_MASK               128


/*** FLBPR - FLASH Block Protect Register; 0x0000FF7E ***/
typedef union {
  byte Byte;
  struct {
    byte BPR0        :1;                                       /* FLASH Block Protect Bit 0 */
    byte BPR1        :1;                                       /* FLASH Block Protect Bit 1 */
    byte BPR2        :1;                                       /* FLASH Block Protect Bit 2 */
    byte BPR3        :1;                                       /* FLASH Block Protect Bit 3 */
    byte BPR4        :1;                                       /* FLASH Block Protect Bit 4 */
    byte BPR5        :1;                                       /* FLASH Block Protect Bit 5 */
    byte BPR6        :1;                                       /* FLASH Block Protect Bit 6 */
    byte BPR7        :1;                                       /* FLASH Block Protect Bit 7 */
  } Bits;
} FLBPRSTR;
/* Tip for register initialization in the user code:  const byte FLBPR_INIT @0x0000FF7E = <FLBPR_INITVAL>; */
#define _FLBPR (*(const FLBPRSTR * __far)0x0000FF7E)
#define FLBPR                           _FLBPR.Byte
#define FLBPR_BPR0                      _FLBPR.Bits.BPR0
#define FLBPR_BPR1                      _FLBPR.Bits.BPR1
#define FLBPR_BPR2                      _FLBPR.Bits.BPR2
#define FLBPR_BPR3                      _FLBPR.Bits.BPR3
#define FLBPR_BPR4                      _FLBPR.Bits.BPR4
#define FLBPR_BPR5                      _FLBPR.Bits.BPR5
#define FLBPR_BPR6                      _FLBPR.Bits.BPR6
#define FLBPR_BPR7                      _FLBPR.Bits.BPR7

#define FLBPR_BPR0_MASK                 1
#define FLBPR_BPR1_MASK                 2
#define FLBPR_BPR2_MASK                 4
#define FLBPR_BPR3_MASK                 8
#define FLBPR_BPR4_MASK                 16
#define FLBPR_BPR5_MASK                 32
#define FLBPR_BPR6_MASK                 64
#define FLBPR_BPR7_MASK                 128


/*** NVOSCTRIM - Oscillator Trim Register (trimmed at the factory); 0x0000FFC0 ***/
typedef union {
  byte Byte;
  struct {
    byte TRIM0       :1;                                       /* Internal Oscillator Trim Factor Bit 0 */
    byte TRIM1       :1;                                       /* Internal Oscillator Trim Factor Bit 1 */
    byte TRIM2       :1;                                       /* Internal Oscillator Trim Factor Bit 2 */
    byte TRIM3       :1;                                       /* Internal Oscillator Trim Factor Bit 3 */
    byte TRIM4       :1;                                       /* Internal Oscillator Trim Factor Bit 4 */
    byte TRIM5       :1;                                       /* Internal Oscillator Trim Factor Bit 5 */
    byte TRIM6       :1;                                       /* Internal Oscillator Trim Factor Bit 6 */
    byte TRIM7       :1;                                       /* Internal Oscillator Trim Factor Bit 7 */
  } Bits;
} NVOSCTRIMSTR;
/* Tip for register initialization in the user code:  const byte NVOSCTRIM_INIT @0x0000FFC0 = <NVOSCTRIM_INITVAL>; */
#define _NVOSCTRIM (*(const NVOSCTRIMSTR * __far)0x0000FFC0)
#define NVOSCTRIM                       _NVOSCTRIM.Byte
#define NVOSCTRIM_TRIM0                 _NVOSCTRIM.Bits.TRIM0
#define NVOSCTRIM_TRIM1                 _NVOSCTRIM.Bits.TRIM1
#define NVOSCTRIM_TRIM2                 _NVOSCTRIM.Bits.TRIM2
#define NVOSCTRIM_TRIM3                 _NVOSCTRIM.Bits.TRIM3
#define NVOSCTRIM_TRIM4                 _NVOSCTRIM.Bits.TRIM4
#define NVOSCTRIM_TRIM5                 _NVOSCTRIM.Bits.TRIM5
#define NVOSCTRIM_TRIM6                 _NVOSCTRIM.Bits.TRIM6
#define NVOSCTRIM_TRIM7                 _NVOSCTRIM.Bits.TRIM7

#define NVOSCTRIM_TRIM0_MASK            1
#define NVOSCTRIM_TRIM1_MASK            2
#define NVOSCTRIM_TRIM2_MASK            4
#define NVOSCTRIM_TRIM3_MASK            8
#define NVOSCTRIM_TRIM4_MASK            16
#define NVOSCTRIM_TRIM5_MASK            32
#define NVOSCTRIM_TRIM6_MASK            64
#define NVOSCTRIM_TRIM7_MASK            128


/*** COPCTL - COP Control Register; 0x0000FFFF ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Bit 0 */
    byte BIT1        :1;                                       /* Bit 1 */
    byte BIT2        :1;                                       /* Bit 2 */
    byte BIT3        :1;                                       /* Bit 3 */
    byte BIT4        :1;                                       /* Bit 4 */
    byte BIT5        :1;                                       /* Bit 5 */
    byte BIT6        :1;                                       /* Bit 6 */
    byte BIT7        :1;                                       /* Bit 7 */
  } Bits;
} COPCTLSTR;
extern volatile COPCTLSTR _COPCTL;
#define COPCTL                          _COPCTL.Byte
#define COPCTL_BIT0                     _COPCTL.Bits.BIT0
#define COPCTL_BIT1                     _COPCTL.Bits.BIT1
#define COPCTL_BIT2                     _COPCTL.Bits.BIT2
#define COPCTL_BIT3                     _COPCTL.Bits.BIT3
#define COPCTL_BIT4                     _COPCTL.Bits.BIT4
#define COPCTL_BIT5                     _COPCTL.Bits.BIT5
#define COPCTL_BIT6                     _COPCTL.Bits.BIT6
#define COPCTL_BIT7                     _COPCTL.Bits.BIT7

#define COPCTL_BIT0_MASK                1
#define COPCTL_BIT1_MASK                2
#define COPCTL_BIT2_MASK                4
#define COPCTL_BIT3_MASK                8
#define COPCTL_BIT4_MASK                16
#define COPCTL_BIT5_MASK                32
#define COPCTL_BIT6_MASK                64
#define COPCTL_BIT7_MASK                128



/***********************************************/
/**   D E P R E C I A T E D   S Y M B O L S   **/
/***********************************************/
/* ---------------------------------------------------------------------------------------------------
Exceptions in bit names of timer status and control registers
due to backward compatibility with previous releases  */
#define TSC0_CHxMAX _TSC0.Bits.CH0MAX
#define TSC0_TOVx _TSC0.Bits.TOV0
#define TSC0_ELSxA _TSC0.Bits.ELS0A
#define TSC0_ELSxB _TSC0.Bits.ELS0B
#define TSC0_MSxA _TSC0.Bits.MS0A
#define TSC0_MSxB _TSC0.Bits.MS0B
#define TSC0_CHxIE _TSC0.Bits.CH0IE
#define TSC0_CHxF _TSC0.Bits.CH0F

#define TSC1_CHxMAX _TSC1.Bits.CH1MAX
#define TSC1_TOVx _TSC1.Bits.TOV1
#define TSC1_ELSxA _TSC1.Bits.ELS1A
#define TSC1_ELSxB _TSC1.Bits.ELS1B
#define TSC1_MSxA _TSC1.Bits.MS1A
#define TSC1_CHxIE _TSC1.Bits.CH1IE
#define TSC1_CHxF _TSC1.Bits.CH1F

/* --------------------------------------------------------------------------- */
/* The following symbols were removed, because they were invalid or irrelevant */
/* --------------------------------------------------------------------------- */


/* **** 11.9.2009 12:42:40 */

#define TCH_ARR                          This_symb_has_been_depreciated
#endif
