/* Based on CPU DB MC68HC908LD64, version 2.87.145 (RegistersPrg V2.30) */
/*
** ###################################################################
**     Filename  : mc68hc908ld64.h
**     Processor : MC68HC908LD64IFU
**     FileFormat: V2.30
**     DataSheet : MC68HC908LD64 Rev. 3.0 07/2004
**     Compiler  : CodeWarrior compiler
**     Date/Time : 11.9.2009, 14:09
**     Abstract  :
**         This header implements the mapping of I/O devices.
**
**     Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved.
**     
**     http      : www.freescale.com
**     mail      : support@freescale.com
**
**     CPU Registers Revisions:
**               - none
**
**     File-Format-Revisions:
**      - 14.11.2005, V2.00 :
**               - Deprecated symbols added for backward compatibility (section at the end of this file)
**      - 15.11.2005, V2.01 :
**               - Changes have not affected this file (because they are related to another family)
**      - 17.12.2005, V2.02 :
**               - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778
**      - 16.01.2006, V2.03 :
**               - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920.
**               - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const")
**      - 08.03.2006, V2.04 :
**               - Support for bit(s) names duplicated with any register name in .h header files
**      - 24.03.2006, V2.05 :
**               - Changes have not affected this file (because they are related to another family)
**      - 26.04.2006, V2.06 :
**               - Absolute assembly supported (depreciated symbols are not defined)
**      - 27.04.2006, V2.07 :
**               - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA).
**      - 07.06.2006, V2.08 :
**               - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM.
**      - 03.07.2006, V2.09 :
**               - Flash commands constants supported
**      - 27.10.2006, V2.10 :
**               - __RESET_WATCHDOG improved formating and re-definition
**      - 23.11.2006, V2.11 :
**               - Changes have not affected this file (because they are related to another family)
**      - 22.01.2007, V2.12 :
**               - Changes have not affected this file (because they are related to another family)
**      - 01.03.2007, V2.13 :
**               - Flash commands constants values converted to HEX format
**      - 02.03.2007, V2.14 :
**               - Interrupt vector numbers added into .H, see VectorNumber_*
**      - 26.03.2007, V2.15 :
**               - Changes have not affected this file (because they are related to another family)
**      - 10.05.2007, V2.16 :
**               - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ)
**      - 05.06.2007, V2.17 :
**               - Changes have not affected this file (because they are related to another family)
**      - 19.07.2007, V2.18 :
**               - Improved number of blanked lines inside register structures
**      - 06.08.2007, V2.19 :
**               - CPUDB revisions generated ahead of the file-format revisions.
**      - 11.09.2007, V2.20 :
**               - Added comment about initialization of unbonded pins.
**      - 02.01.2008, V2.21 :
**               - Changes have not affected this file (because they are related to another family)
**      - 13.02.2008, V2.22 :
**               - Changes have not affected this file (because they are related to another family)
**      - 20.02.2008, V2.23 :
**               - Changes have not affected this file (because they are related to another family)
**      - 03.07.2008, V2.24 :
**               - Added support for bits with name starting with number (like "1HZ")
**      - 28.11.2008, V2.25 :
**               - StandBy RAM array declaration for ANSI-C added
**      - 1.12.2008, V2.26 :
**               - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map.
**      - 17.3.2009, V2.27 :
**               - Merged bit-group is not generated, if the name matches with another bit name in the register
**      - 6.4.2009, V2.28 :
**               - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB
**      - 3.8.2009, V2.29 :
**               - If there is just one bits group matching register name, single bits are not generated
**      - 10.9.2009, V2.30 :
**               - Fixed generation of registers arrays.
**
**     Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific
**     derivative device. To avoid extra current drain from floating input pins, the user’s reset
**     initialization routine in the application program must either enable on-chip pull-up devices
**     or change the direction of unconnected pins to outputs so the pins do not float.
** ###################################################################
*/

#ifndef _MC68HC908LD64_H
#define _MC68HC908LD64_H

/* Types definition */
typedef unsigned char byte;
typedef unsigned int word;
typedef unsigned long dword;
typedef unsigned long dlong[2];

/* Watchdog reset macro */
#ifndef __RESET_WATCHDOG
#ifdef _lint
  #define __RESET_WATCHDOG()  /* empty */
#else
  #define __RESET_WATCHDOG() {asm sta COPCTL;}
#endif
#endif /* __RESET_WATCHDOG */

#define REG_BASE 0x0000                /* Base address for the I/O register block */


#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */

/**************** interrupt vector numbers ****************/
#define VectorNumber_CGMPLL             15
#define VectorNumber_KBI                14
#define VectorNumber_ADC                13
#define VectorNumber_OSD                12
#define VectorNumber_MMIIC              11
#define VectorNumber_Sync               10
#define VectorNumber_TIMOvr             9
#define VectorNumber_TIMCH1             8
#define VectorNumber_TIMCH0             7
#define VectorNumber_DDC12AB            6
#define VectorNumber_USB_Device         5
#define VectorNumber_USB_HUB_EP0        4
#define VectorNumber_USB_HUB_Timing     3
#define VectorNumber_IRQ                2
#define VectorNumber_SWI                1
#define VectorNumber_RESET              0

/**************** interrupt vector table ****************/
#define INT_CGMPLL                      0x0000FFE0
#define INT_KBI                         0x0000FFE2
#define INT_ADC                         0x0000FFE4
#define INT_OSD                         0x0000FFE6
#define INT_MMIIC                       0x0000FFE8
#define INT_Sync                        0x0000FFEA
#define INT_TIMOvr                      0x0000FFEC
#define INT_TIMCH1                      0x0000FFEE
#define INT_TIMCH0                      0x0000FFF0
#define INT_DDC12AB                     0x0000FFF2
#define INT_USB_Device                  0x0000FFF4
#define INT_USB_HUB_EP0                 0x0000FFF6
#define INT_USB_HUB_Timing              0x0000FFF8
#define INT_IRQ                         0x0000FFFA
#define INT_SWI                         0x0000FFFC
#define INT_RESET                       0x0000FFFE

/**************** registers I/O map ****************/

/*** PTA - Port A Data Register; 0x00000000 ***/
typedef union {
  byte Byte;
  struct {
    byte PTA0        :1;                                       /* Port A Data Bit 0 */
    byte PTA1        :1;                                       /* Port A Data Bit 1 */
    byte PTA2        :1;                                       /* Port A Data Bit 2 */
    byte PTA3        :1;                                       /* Port A Data Bit 3 */
    byte PTA4        :1;                                       /* Port A Data Bit 4 */
    byte PTA5        :1;                                       /* Port A Data Bit 5 */
    byte PTA6        :1;                                       /* Port A Data Bit 6 */
    byte PTA7        :1;                                       /* Port A Data Bit 7 */
  } Bits;
} PTASTR;
extern volatile PTASTR _PTA;
#define PTA                             _PTA.Byte
#define PTA_PTA0                        _PTA.Bits.PTA0
#define PTA_PTA1                        _PTA.Bits.PTA1
#define PTA_PTA2                        _PTA.Bits.PTA2
#define PTA_PTA3                        _PTA.Bits.PTA3
#define PTA_PTA4                        _PTA.Bits.PTA4
#define PTA_PTA5                        _PTA.Bits.PTA5
#define PTA_PTA6                        _PTA.Bits.PTA6
#define PTA_PTA7                        _PTA.Bits.PTA7

#define PTA_PTA0_MASK                   1
#define PTA_PTA1_MASK                   2
#define PTA_PTA2_MASK                   4
#define PTA_PTA3_MASK                   8
#define PTA_PTA4_MASK                   16
#define PTA_PTA5_MASK                   32
#define PTA_PTA6_MASK                   64
#define PTA_PTA7_MASK                   128


/*** PTB - Port B Data Register; 0x00000001 ***/
typedef union {
  byte Byte;
  struct {
    byte PTB0        :1;                                       /* Port B Data Bit 0 */
    byte PTB1        :1;                                       /* Port B Data Bit 1 */
    byte PTB2        :1;                                       /* Port B Data Bit 2 */
    byte PTB3        :1;                                       /* Port B Data Bit 3 */
    byte PTB4        :1;                                       /* Port B Data Bit 4 */
    byte PTB5        :1;                                       /* Port B Data Bit 5 */
    byte PTB6        :1;                                       /* Port B Data Bit 6 */
    byte PTB7        :1;                                       /* Port B Data Bit 7 */
  } Bits;
} PTBSTR;
extern volatile PTBSTR _PTB;
#define PTB                             _PTB.Byte
#define PTB_PTB0                        _PTB.Bits.PTB0
#define PTB_PTB1                        _PTB.Bits.PTB1
#define PTB_PTB2                        _PTB.Bits.PTB2
#define PTB_PTB3                        _PTB.Bits.PTB3
#define PTB_PTB4                        _PTB.Bits.PTB4
#define PTB_PTB5                        _PTB.Bits.PTB5
#define PTB_PTB6                        _PTB.Bits.PTB6
#define PTB_PTB7                        _PTB.Bits.PTB7

#define PTB_PTB0_MASK                   1
#define PTB_PTB1_MASK                   2
#define PTB_PTB2_MASK                   4
#define PTB_PTB3_MASK                   8
#define PTB_PTB4_MASK                   16
#define PTB_PTB5_MASK                   32
#define PTB_PTB6_MASK                   64
#define PTB_PTB7_MASK                   128


/*** PTC - Port C Data Register; 0x00000002 ***/
typedef union {
  byte Byte;
  struct {
    byte PTC0        :1;                                       /* Port C Data Bit 0 */
    byte PTC1        :1;                                       /* Port C Data Bit 1 */
    byte PTC2        :1;                                       /* Port C Data Bit 2 */
    byte PTC3        :1;                                       /* Port C Data Bit 3 */
    byte PTC4        :1;                                       /* Port C Data Bit 4 */
    byte PTC5        :1;                                       /* Port C Data Bit 5 */
    byte PTC6        :1;                                       /* Port C Data Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpPTC  :7;
    byte         :1;
  } MergedBits;
} PTCSTR;
extern volatile PTCSTR _PTC;
#define PTC                             _PTC.Byte
#define PTC_PTC0                        _PTC.Bits.PTC0
#define PTC_PTC1                        _PTC.Bits.PTC1
#define PTC_PTC2                        _PTC.Bits.PTC2
#define PTC_PTC3                        _PTC.Bits.PTC3
#define PTC_PTC4                        _PTC.Bits.PTC4
#define PTC_PTC5                        _PTC.Bits.PTC5
#define PTC_PTC6                        _PTC.Bits.PTC6
#define PTC_PTC                         _PTC.MergedBits.grpPTC

#define PTC_PTC0_MASK                   1
#define PTC_PTC1_MASK                   2
#define PTC_PTC2_MASK                   4
#define PTC_PTC3_MASK                   8
#define PTC_PTC4_MASK                   16
#define PTC_PTC5_MASK                   32
#define PTC_PTC6_MASK                   64
#define PTC_PTC_MASK                    127
#define PTC_PTC_BITNUM                  0


/*** PTD - Port D Data Register; 0x00000003 ***/
typedef union {
  byte Byte;
  struct {
    byte PTD0        :1;                                       /* Port D Data Bit 0 */
    byte PTD1        :1;                                       /* Port D Data Bit 1 */
    byte PTD2        :1;                                       /* Port D Data Bit 2 */
    byte PTD3        :1;                                       /* Port D Data Bit 3 */
    byte PTD4        :1;                                       /* Port D Data Bit 4 */
    byte PTD5        :1;                                       /* Port D Data Bit 5 */
    byte PTD6        :1;                                       /* Port D Data Bit 6 */
    byte PTD7        :1;                                       /* Port D Data Bit 7 */
  } Bits;
} PTDSTR;
extern volatile PTDSTR _PTD;
#define PTD                             _PTD.Byte
#define PTD_PTD0                        _PTD.Bits.PTD0
#define PTD_PTD1                        _PTD.Bits.PTD1
#define PTD_PTD2                        _PTD.Bits.PTD2
#define PTD_PTD3                        _PTD.Bits.PTD3
#define PTD_PTD4                        _PTD.Bits.PTD4
#define PTD_PTD5                        _PTD.Bits.PTD5
#define PTD_PTD6                        _PTD.Bits.PTD6
#define PTD_PTD7                        _PTD.Bits.PTD7

#define PTD_PTD0_MASK                   1
#define PTD_PTD1_MASK                   2
#define PTD_PTD2_MASK                   4
#define PTD_PTD3_MASK                   8
#define PTD_PTD4_MASK                   16
#define PTD_PTD5_MASK                   32
#define PTD_PTD6_MASK                   64
#define PTD_PTD7_MASK                   128


/*** DDRA - Data Direction Register A; 0x00000004 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRA0       :1;                                       /* Data Direction Register A Bit 0 */
    byte DDRA1       :1;                                       /* Data Direction Register A Bit 1 */
    byte DDRA2       :1;                                       /* Data Direction Register A Bit 2 */
    byte DDRA3       :1;                                       /* Data Direction Register A Bit 3 */
    byte DDRA4       :1;                                       /* Data Direction Register A Bit 4 */
    byte DDRA5       :1;                                       /* Data Direction Register A Bit 5 */
    byte DDRA6       :1;                                       /* Data Direction Register A Bit 6 */
    byte DDRA7       :1;                                       /* Data Direction Register A Bit 7 */
  } Bits;
} DDRASTR;
extern volatile DDRASTR _DDRA;
#define DDRA                            _DDRA.Byte
#define DDRA_DDRA0                      _DDRA.Bits.DDRA0
#define DDRA_DDRA1                      _DDRA.Bits.DDRA1
#define DDRA_DDRA2                      _DDRA.Bits.DDRA2
#define DDRA_DDRA3                      _DDRA.Bits.DDRA3
#define DDRA_DDRA4                      _DDRA.Bits.DDRA4
#define DDRA_DDRA5                      _DDRA.Bits.DDRA5
#define DDRA_DDRA6                      _DDRA.Bits.DDRA6
#define DDRA_DDRA7                      _DDRA.Bits.DDRA7

#define DDRA_DDRA0_MASK                 1
#define DDRA_DDRA1_MASK                 2
#define DDRA_DDRA2_MASK                 4
#define DDRA_DDRA3_MASK                 8
#define DDRA_DDRA4_MASK                 16
#define DDRA_DDRA5_MASK                 32
#define DDRA_DDRA6_MASK                 64
#define DDRA_DDRA7_MASK                 128


/*** DDRB - Data Direction Register B; 0x00000005 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRB0       :1;                                       /* Data Direction Register B Bit 0 */
    byte DDRB1       :1;                                       /* Data Direction Register B Bit 1 */
    byte DDRB2       :1;                                       /* Data Direction Register B Bit 2 */
    byte DDRB3       :1;                                       /* Data Direction Register B Bit 3 */
    byte DDRB4       :1;                                       /* Data Direction Register B Bit 4 */
    byte DDRB5       :1;                                       /* Data Direction Register B Bit 5 */
    byte DDRB6       :1;                                       /* Data Direction Register B Bit 6 */
    byte DDRB7       :1;                                       /* Data Direction Register B Bit 7 */
  } Bits;
} DDRBSTR;
extern volatile DDRBSTR _DDRB;
#define DDRB                            _DDRB.Byte
#define DDRB_DDRB0                      _DDRB.Bits.DDRB0
#define DDRB_DDRB1                      _DDRB.Bits.DDRB1
#define DDRB_DDRB2                      _DDRB.Bits.DDRB2
#define DDRB_DDRB3                      _DDRB.Bits.DDRB3
#define DDRB_DDRB4                      _DDRB.Bits.DDRB4
#define DDRB_DDRB5                      _DDRB.Bits.DDRB5
#define DDRB_DDRB6                      _DDRB.Bits.DDRB6
#define DDRB_DDRB7                      _DDRB.Bits.DDRB7

#define DDRB_DDRB0_MASK                 1
#define DDRB_DDRB1_MASK                 2
#define DDRB_DDRB2_MASK                 4
#define DDRB_DDRB3_MASK                 8
#define DDRB_DDRB4_MASK                 16
#define DDRB_DDRB5_MASK                 32
#define DDRB_DDRB6_MASK                 64
#define DDRB_DDRB7_MASK                 128


/*** DDRC - Data Direction Register C; 0x00000006 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRC0       :1;                                       /* Data Direction Register C Bit 0 */
    byte DDRC1       :1;                                       /* Data Direction Register C Bit 1 */
    byte DDRC2       :1;                                       /* Data Direction Register C Bit 2 */
    byte DDRC3       :1;                                       /* Data Direction Register C Bit 3 */
    byte DDRC4       :1;                                       /* Data Direction Register C Bit 4 */
    byte DDRC5       :1;                                       /* Data Direction Register C Bit 5 */
    byte DDRC6       :1;                                       /* Data Direction Register C Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpDDRC :7;
    byte         :1;
  } MergedBits;
} DDRCSTR;
extern volatile DDRCSTR _DDRC;
#define DDRC                            _DDRC.Byte
#define DDRC_DDRC0                      _DDRC.Bits.DDRC0
#define DDRC_DDRC1                      _DDRC.Bits.DDRC1
#define DDRC_DDRC2                      _DDRC.Bits.DDRC2
#define DDRC_DDRC3                      _DDRC.Bits.DDRC3
#define DDRC_DDRC4                      _DDRC.Bits.DDRC4
#define DDRC_DDRC5                      _DDRC.Bits.DDRC5
#define DDRC_DDRC6                      _DDRC.Bits.DDRC6
#define DDRC_DDRC                       _DDRC.MergedBits.grpDDRC

#define DDRC_DDRC0_MASK                 1
#define DDRC_DDRC1_MASK                 2
#define DDRC_DDRC2_MASK                 4
#define DDRC_DDRC3_MASK                 8
#define DDRC_DDRC4_MASK                 16
#define DDRC_DDRC5_MASK                 32
#define DDRC_DDRC6_MASK                 64
#define DDRC_DDRC_MASK                  127
#define DDRC_DDRC_BITNUM                0


/*** DDRD - Data Direction Register D; 0x00000007 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRD0       :1;                                       /* Data Direction Register D Bit 0 */
    byte DDRD1       :1;                                       /* Data Direction Register D Bit 1 */
    byte DDRD2       :1;                                       /* Data Direction Register D Bit 2 */
    byte DDRD3       :1;                                       /* Data Direction Register D Bit 3 */
    byte DDRD4       :1;                                       /* Data Direction Register D Bit 4 */
    byte DDRD5       :1;                                       /* Data Direction Register D Bit 5 */
    byte DDRD6       :1;                                       /* Data Direction Register D Bit 6 */
    byte DDRD7       :1;                                       /* Data Direction Register D Bit 7 */
  } Bits;
} DDRDSTR;
extern volatile DDRDSTR _DDRD;
#define DDRD                            _DDRD.Byte
#define DDRD_DDRD0                      _DDRD.Bits.DDRD0
#define DDRD_DDRD1                      _DDRD.Bits.DDRD1
#define DDRD_DDRD2                      _DDRD.Bits.DDRD2
#define DDRD_DDRD3                      _DDRD.Bits.DDRD3
#define DDRD_DDRD4                      _DDRD.Bits.DDRD4
#define DDRD_DDRD5                      _DDRD.Bits.DDRD5
#define DDRD_DDRD6                      _DDRD.Bits.DDRD6
#define DDRD_DDRD7                      _DDRD.Bits.DDRD7

#define DDRD_DDRD0_MASK                 1
#define DDRD_DDRD1_MASK                 2
#define DDRD_DDRD2_MASK                 4
#define DDRD_DDRD3_MASK                 8
#define DDRD_DDRD4_MASK                 16
#define DDRD_DDRD5_MASK                 32
#define DDRD_DDRD6_MASK                 64
#define DDRD_DDRD7_MASK                 128


/*** PTE - Port E Data Register; 0x00000008 ***/
typedef union {
  byte Byte;
  struct {
    byte PTE0        :1;                                       /* Port E Data Bit 0 */
    byte PTE1        :1;                                       /* Port E Data Bit 1 */
    byte PTE2        :1;                                       /* Port E Data Bit 2 */
    byte PTE3        :1;                                       /* Port E Data Bit 3 */
    byte PTE4        :1;                                       /* Port E Data Bit 4 */
    byte PTE5        :1;                                       /* Port E Data Bit 5 */
    byte PTE6        :1;                                       /* Port E Data Bit 6 */
    byte PTE7        :1;                                       /* Port E Data Bit 7 */
  } Bits;
} PTESTR;
extern volatile PTESTR _PTE;
#define PTE                             _PTE.Byte
#define PTE_PTE0                        _PTE.Bits.PTE0
#define PTE_PTE1                        _PTE.Bits.PTE1
#define PTE_PTE2                        _PTE.Bits.PTE2
#define PTE_PTE3                        _PTE.Bits.PTE3
#define PTE_PTE4                        _PTE.Bits.PTE4
#define PTE_PTE5                        _PTE.Bits.PTE5
#define PTE_PTE6                        _PTE.Bits.PTE6
#define PTE_PTE7                        _PTE.Bits.PTE7

#define PTE_PTE0_MASK                   1
#define PTE_PTE1_MASK                   2
#define PTE_PTE2_MASK                   4
#define PTE_PTE3_MASK                   8
#define PTE_PTE4_MASK                   16
#define PTE_PTE5_MASK                   32
#define PTE_PTE6_MASK                   64
#define PTE_PTE7_MASK                   128


/*** DDRE - Data Direction Register E; 0x00000009 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRE0       :1;                                       /* Data Direction Register E Bit 0 */
    byte DDRE1       :1;                                       /* Data Direction Register E Bit 1 */
    byte DDRE2       :1;                                       /* Data Direction Register E Bit 2 */
    byte DDRE3       :1;                                       /* Data Direction Register E Bit 3 */
    byte DDRE4       :1;                                       /* Data Direction Register E Bit 4 */
    byte DDRE5       :1;                                       /* Data Direction Register E Bit 5 */
    byte DDRE6       :1;                                       /* Data Direction Register E Bit 6 */
    byte DDRE7       :1;                                       /* Data Direction Register E Bit 7 */
  } Bits;
} DDRESTR;
extern volatile DDRESTR _DDRE;
#define DDRE                            _DDRE.Byte
#define DDRE_DDRE0                      _DDRE.Bits.DDRE0
#define DDRE_DDRE1                      _DDRE.Bits.DDRE1
#define DDRE_DDRE2                      _DDRE.Bits.DDRE2
#define DDRE_DDRE3                      _DDRE.Bits.DDRE3
#define DDRE_DDRE4                      _DDRE.Bits.DDRE4
#define DDRE_DDRE5                      _DDRE.Bits.DDRE5
#define DDRE_DDRE6                      _DDRE.Bits.DDRE6
#define DDRE_DDRE7                      _DDRE.Bits.DDRE7

#define DDRE_DDRE0_MASK                 1
#define DDRE_DDRE1_MASK                 2
#define DDRE_DDRE2_MASK                 4
#define DDRE_DDRE3_MASK                 8
#define DDRE_DDRE4_MASK                 16
#define DDRE_DDRE5_MASK                 32
#define DDRE_DDRE6_MASK                 64
#define DDRE_DDRE7_MASK                 128


/*** TSC - Timer Status & Control; 0x0000000A ***/
typedef union {
  byte Byte;
  struct {
    byte PS0         :1;                                       /* Prescaler Select Bit */
    byte PS1         :1;                                       /* Prescaler Select Bit */
    byte PS2         :1;                                       /* Prescaler Select Bit */
    byte             :1; 
    byte TRST        :1;                                       /* TIM Reset Bit */
    byte TSTOP       :1;                                       /* TIM Stop Bit */
    byte TOIE        :1;                                       /* TIM Overflow Interrupt Enable Bit */
    byte TOF         :1;                                       /* TIM Overflow Flag Bit */
  } Bits;
  struct {
    byte grpPS   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TSCSTR;
extern volatile TSCSTR _TSC;
#define TSC                             _TSC.Byte
#define TSC_PS0                         _TSC.Bits.PS0
#define TSC_PS1                         _TSC.Bits.PS1
#define TSC_PS2                         _TSC.Bits.PS2
#define TSC_TRST                        _TSC.Bits.TRST
#define TSC_TSTOP                       _TSC.Bits.TSTOP
#define TSC_TOIE                        _TSC.Bits.TOIE
#define TSC_TOF                         _TSC.Bits.TOF
#define TSC_PS                          _TSC.MergedBits.grpPS

#define TSC_PS0_MASK                    1
#define TSC_PS1_MASK                    2
#define TSC_PS2_MASK                    4
#define TSC_TRST_MASK                   16
#define TSC_TSTOP_MASK                  32
#define TSC_TOIE_MASK                   64
#define TSC_TOF_MASK                    128
#define TSC_PS_MASK                     7
#define TSC_PS_BITNUM                   0


/*** TCNT - TIM Counter Register; 0x0000000C ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TCNTH - TIM Counter Register; 0x0000000C ***/
    union {
      byte Byte;
    } TCNTHSTR;
    #define TCNTH                       _TCNT.Overlap_STR.TCNTHSTR.Byte
    

    /*** TCNTL - TIM Counter Register; 0x0000000D ***/
    union {
      byte Byte;
    } TCNTLSTR;
    #define TCNTL                       _TCNT.Overlap_STR.TCNTLSTR.Byte
    
  } Overlap_STR;

} TCNTSTR;
extern volatile TCNTSTR _TCNT;
#define TCNT                            _TCNT.Word


/*** TMOD - TIM Counter Modulo Register; 0x0000000E ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TMODH - TIM Counter Modulo Register; 0x0000000E ***/
    union {
      byte Byte;
    } TMODHSTR;
    #define TMODH                       _TMOD.Overlap_STR.TMODHSTR.Byte
    

    /*** TMODL - TIM Counter Modulo Register; 0x0000000F ***/
    union {
      byte Byte;
    } TMODLSTR;
    #define TMODL                       _TMOD.Overlap_STR.TMODLSTR.Byte
    
  } Overlap_STR;

} TMODSTR;
extern volatile TMODSTR _TMOD;
#define TMOD                            _TMOD.Word


/*** TSC0 - TIM Channel Status and Control Register 0; 0x00000010 ***/
typedef union {
  byte Byte;
  struct {
    byte CH0MAX      :1;                                       /* Channel 0 Maximum Duty Cycle Bit */
    byte TOV0        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS0A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS0B       :1;                                       /* Edge/Level Select Bit B */
    byte MS0A        :1;                                       /* Mode Select Bit A */
    byte MS0B        :1;                                       /* Mode Select Bit B */
    byte CH0IE       :1;                                       /* Channel 0 Interrupt Enable Bit */
    byte CH0F        :1;                                       /* Channel 0 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV  :1;
    byte grpELS0x :2;
    byte grpMS0x :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} TSC0STR;
extern volatile TSC0STR _TSC0;
#define TSC0                            _TSC0.Byte
#define TSC0_CH0MAX                     _TSC0.Bits.CH0MAX
#define TSC0_TOV0                       _TSC0.Bits.TOV0
#define TSC0_ELS0A                      _TSC0.Bits.ELS0A
#define TSC0_ELS0B                      _TSC0.Bits.ELS0B
#define TSC0_MS0A                       _TSC0.Bits.MS0A
#define TSC0_MS0B                       _TSC0.Bits.MS0B
#define TSC0_CH0IE                      _TSC0.Bits.CH0IE
#define TSC0_CH0F                       _TSC0.Bits.CH0F
#define TSC0_ELS0x                      _TSC0.MergedBits.grpELS0x
#define TSC0_MS0x                       _TSC0.MergedBits.grpMS0x

#define TSC0_CH0MAX_MASK                1
#define TSC0_TOV0_MASK                  2
#define TSC0_ELS0A_MASK                 4
#define TSC0_ELS0B_MASK                 8
#define TSC0_MS0A_MASK                  16
#define TSC0_MS0B_MASK                  32
#define TSC0_CH0IE_MASK                 64
#define TSC0_CH0F_MASK                  128
#define TSC0_ELS0x_MASK                 12
#define TSC0_ELS0x_BITNUM               2
#define TSC0_MS0x_MASK                  48
#define TSC0_MS0x_BITNUM                4


/*** TCH0 - TIM channel 0 register; 0x00000011 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TCH0H - TIM channel 0 register High; 0x00000011 ***/
    union {
      byte Byte;
    } TCH0HSTR;
    #define TCH0H                       _TCH0.Overlap_STR.TCH0HSTR.Byte
    

    /*** TCH0L - TIM channel 0 register Low; 0x00000012 ***/
    union {
      byte Byte;
    } TCH0LSTR;
    #define TCH0L                       _TCH0.Overlap_STR.TCH0LSTR.Byte
    
  } Overlap_STR;

} TCH0STR;
extern volatile TCH0STR _TCH0;
#define TCH0                            _TCH0.Word


/*** TSC1 - TIM Channel Status and Control Register 1; 0x00000013 ***/
typedef union {
  byte Byte;
  struct {
    byte CH1MAX      :1;                                       /* Channel 1 Maximum Duty Cycle Bit */
    byte TOV1        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS1A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS1B       :1;                                       /* Edge/Level Select Bit B */
    byte MS1A        :1;                                       /* Mode Select Bit A */
    byte             :1; 
    byte CH1IE       :1;                                       /* Channel 1 Interrupt Enable Bit */
    byte CH1F        :1;                                       /* Channel 1 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_1 :1;
    byte grpELS1x :2;
    byte grpMS1x :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TSC1STR;
extern volatile TSC1STR _TSC1;
#define TSC1                            _TSC1.Byte
#define TSC1_CH1MAX                     _TSC1.Bits.CH1MAX
#define TSC1_TOV1                       _TSC1.Bits.TOV1
#define TSC1_ELS1A                      _TSC1.Bits.ELS1A
#define TSC1_ELS1B                      _TSC1.Bits.ELS1B
#define TSC1_MS1A                       _TSC1.Bits.MS1A
#define TSC1_CH1IE                      _TSC1.Bits.CH1IE
#define TSC1_CH1F                       _TSC1.Bits.CH1F
#define TSC1_ELS1x                      _TSC1.MergedBits.grpELS1x

#define TSC1_CH1MAX_MASK                1
#define TSC1_TOV1_MASK                  2
#define TSC1_ELS1A_MASK                 4
#define TSC1_ELS1B_MASK                 8
#define TSC1_MS1A_MASK                  16
#define TSC1_CH1IE_MASK                 64
#define TSC1_CH1F_MASK                  128
#define TSC1_ELS1x_MASK                 12
#define TSC1_ELS1x_BITNUM               2


/*** TCH1 - TIM channel 1 register; 0x00000014 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TCH1H - TIM channel 1 register High; 0x00000014 ***/
    union {
      byte Byte;
    } TCH1HSTR;
    #define TCH1H                       _TCH1.Overlap_STR.TCH1HSTR.Byte
    

    /*** TCH1L - TIM channel 1 register Low; 0x00000015 ***/
    union {
      byte Byte;
    } TCH1LSTR;
    #define TCH1L                       _TCH1.Overlap_STR.TCH1LSTR.Byte
    
  } Overlap_STR;

} TCH1STR;
extern volatile TCH1STR _TCH1;
#define TCH1                            _TCH1.Word


/*** DDCMCR - DDC Master Control Register; 0x00000016 ***/
typedef union {
  byte Byte;
  struct {
    byte BR0         :1;                                       /* Baud Rate Select Bit 0 */
    byte BR1         :1;                                       /* Baud Rate Select Bit 1 */
    byte BR2         :1;                                       /* Baud Rate Select Bit 2 */
    byte MRW         :1;                                       /* Master Read/Write */
    byte MAST        :1;                                       /* Master Control Bit */
    byte BB          :1;                                       /* Bus Busy Flag */
    byte NAKIF       :1;                                       /* No Acknowledge Interrupt Flag */
    byte ALIF        :1;                                       /* DDC Arbitration Lost Interrupt Flag */
  } Bits;
  struct {
    byte grpBR   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DDCMCRSTR;
extern volatile DDCMCRSTR _DDCMCR;
#define DDCMCR                          _DDCMCR.Byte
#define DDCMCR_BR0                      _DDCMCR.Bits.BR0
#define DDCMCR_BR1                      _DDCMCR.Bits.BR1
#define DDCMCR_BR2                      _DDCMCR.Bits.BR2
#define DDCMCR_MRW                      _DDCMCR.Bits.MRW
#define DDCMCR_MAST                     _DDCMCR.Bits.MAST
#define DDCMCR_BB                       _DDCMCR.Bits.BB
#define DDCMCR_NAKIF                    _DDCMCR.Bits.NAKIF
#define DDCMCR_ALIF                     _DDCMCR.Bits.ALIF
#define DDCMCR_BR                       _DDCMCR.MergedBits.grpBR

#define DDCMCR_BR0_MASK                 1
#define DDCMCR_BR1_MASK                 2
#define DDCMCR_BR2_MASK                 4
#define DDCMCR_MRW_MASK                 8
#define DDCMCR_MAST_MASK                16
#define DDCMCR_BB_MASK                  32
#define DDCMCR_NAKIF_MASK               64
#define DDCMCR_ALIF_MASK                128
#define DDCMCR_BR_MASK                  7
#define DDCMCR_BR_BITNUM                0


/*** DDCADR - DDC Address Register; 0x00000017 ***/
typedef union {
  byte Byte;
  struct {
    byte EXTAD       :1;                                       /* DDC Expand Address */
    byte DAD1        :1;                                       /* DDC Address Bit 1 */
    byte DAD2        :1;                                       /* DDC Address Bit 2 */
    byte DAD3        :1;                                       /* DDC Address Bit 3 */
    byte DAD4        :1;                                       /* DDC Address Bit 4 */
    byte DAD5        :1;                                       /* DDC Address Bit 5 */
    byte DAD6        :1;                                       /* DDC Address Bit 6 */
    byte DAD7        :1;                                       /* DDC Address Bit 7 */
  } Bits;
  struct {
    byte         :1;
    byte grpDAD_1 :7;
  } MergedBits;
} DDCADRSTR;
extern volatile DDCADRSTR _DDCADR;
#define DDCADR                          _DDCADR.Byte
#define DDCADR_EXTAD                    _DDCADR.Bits.EXTAD
#define DDCADR_DAD1                     _DDCADR.Bits.DAD1
#define DDCADR_DAD2                     _DDCADR.Bits.DAD2
#define DDCADR_DAD3                     _DDCADR.Bits.DAD3
#define DDCADR_DAD4                     _DDCADR.Bits.DAD4
#define DDCADR_DAD5                     _DDCADR.Bits.DAD5
#define DDCADR_DAD6                     _DDCADR.Bits.DAD6
#define DDCADR_DAD7                     _DDCADR.Bits.DAD7
#define DDCADR_DAD_1                    _DDCADR.MergedBits.grpDAD_1
#define DDCADR_DAD                      DDCADR_DAD_1

#define DDCADR_EXTAD_MASK               1
#define DDCADR_DAD1_MASK                2
#define DDCADR_DAD2_MASK                4
#define DDCADR_DAD3_MASK                8
#define DDCADR_DAD4_MASK                16
#define DDCADR_DAD5_MASK                32
#define DDCADR_DAD6_MASK                64
#define DDCADR_DAD7_MASK                128
#define DDCADR_DAD_1_MASK               254
#define DDCADR_DAD_1_BITNUM             1


/*** DDCCR - DDC Control Register; 0x00000018 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte DDC1EN      :1;                                       /* DDC1 Protocol Enable */
    byte SCLIEN      :1;                                       /* SCL Interrupt Enable */
    byte TXAK        :1;                                       /* Transmit Acknowledge Enable */
    byte             :1; 
    byte             :1; 
    byte DIEN        :1;                                       /* DDC Interrupt Enable */
    byte DEN         :1;                                       /* DDC Enable */
  } Bits;
} DDCCRSTR;
extern volatile DDCCRSTR _DDCCR;
#define DDCCR                           _DDCCR.Byte
#define DDCCR_DDC1EN                    _DDCCR.Bits.DDC1EN
#define DDCCR_SCLIEN                    _DDCCR.Bits.SCLIEN
#define DDCCR_TXAK                      _DDCCR.Bits.TXAK
#define DDCCR_DIEN                      _DDCCR.Bits.DIEN
#define DDCCR_DEN                       _DDCCR.Bits.DEN

#define DDCCR_DDC1EN_MASK               2
#define DDCCR_SCLIEN_MASK               4
#define DDCCR_TXAK_MASK                 8
#define DDCCR_DIEN_MASK                 64
#define DDCCR_DEN_MASK                  128


/*** DDCSR - DDC Status Register; 0x00000019 ***/
typedef union {
  byte Byte;
  struct {
    byte RXBF        :1;                                       /* DDC Receive Buffer Full */
    byte TXBE        :1;                                       /* DDC Transmit Buffer Empty */
    byte SCLIF       :1;                                       /* SCL Interrupt Flag */
    byte RXAK        :1;                                       /* DDC Receive Acknowledge */
    byte SRW         :1;                                       /* DDC Slave Read/Write */
    byte MATCH       :1;                                       /* DDC Address Match */
    byte TXIF        :1;                                       /* DDC Transmit Interrupt Flag */
    byte RXIF        :1;                                       /* DDC Receive Interrupt Flag */
  } Bits;
} DDCSRSTR;
extern volatile DDCSRSTR _DDCSR;
#define DDCSR                           _DDCSR.Byte
#define DDCSR_RXBF                      _DDCSR.Bits.RXBF
#define DDCSR_TXBE                      _DDCSR.Bits.TXBE
#define DDCSR_SCLIF                     _DDCSR.Bits.SCLIF
#define DDCSR_RXAK                      _DDCSR.Bits.RXAK
#define DDCSR_SRW                       _DDCSR.Bits.SRW
#define DDCSR_MATCH                     _DDCSR.Bits.MATCH
#define DDCSR_TXIF                      _DDCSR.Bits.TXIF
#define DDCSR_RXIF                      _DDCSR.Bits.RXIF

#define DDCSR_RXBF_MASK                 1
#define DDCSR_TXBE_MASK                 2
#define DDCSR_SCLIF_MASK                4
#define DDCSR_RXAK_MASK                 8
#define DDCSR_SRW_MASK                  16
#define DDCSR_MATCH_MASK                32
#define DDCSR_TXIF_MASK                 64
#define DDCSR_RXIF_MASK                 128


/*** DDCDTR - DDC Data Transmit Register; 0x0000001A ***/
typedef union {
  byte Byte;
  struct {
    byte DTD0        :1;                                       /* DDC Data Transmit Bit 0 */
    byte DTD1        :1;                                       /* DDC Data Transmit Bit 1 */
    byte DTD2        :1;                                       /* DDC Data Transmit Bit 2 */
    byte DTD3        :1;                                       /* DDC Data Transmit Bit 3 */
    byte DTD4        :1;                                       /* DDC Data Transmit Bit 4 */
    byte DTD5        :1;                                       /* DDC Data Transmit Bit 5 */
    byte DTD6        :1;                                       /* DDC Data Transmit Bit 6 */
    byte DTD7        :1;                                       /* DDC Data Transmit Bit 7 */
  } Bits;
} DDCDTRSTR;
extern volatile DDCDTRSTR _DDCDTR;
#define DDCDTR                          _DDCDTR.Byte
#define DDCDTR_DTD0                     _DDCDTR.Bits.DTD0
#define DDCDTR_DTD1                     _DDCDTR.Bits.DTD1
#define DDCDTR_DTD2                     _DDCDTR.Bits.DTD2
#define DDCDTR_DTD3                     _DDCDTR.Bits.DTD3
#define DDCDTR_DTD4                     _DDCDTR.Bits.DTD4
#define DDCDTR_DTD5                     _DDCDTR.Bits.DTD5
#define DDCDTR_DTD6                     _DDCDTR.Bits.DTD6
#define DDCDTR_DTD7                     _DDCDTR.Bits.DTD7

#define DDCDTR_DTD0_MASK                1
#define DDCDTR_DTD1_MASK                2
#define DDCDTR_DTD2_MASK                4
#define DDCDTR_DTD3_MASK                8
#define DDCDTR_DTD4_MASK                16
#define DDCDTR_DTD5_MASK                32
#define DDCDTR_DTD6_MASK                64
#define DDCDTR_DTD7_MASK                128


/*** DDCDRR - DDC Data Receive Register; 0x0000001B ***/
typedef union {
  byte Byte;
  struct {
    byte DRD0        :1;                                       /* DDC Data Receive Bit 0 */
    byte DRD1        :1;                                       /* DDC Data Receive Bit 1 */
    byte DRD2        :1;                                       /* DDC Data Receive Bit 2 */
    byte DRD3        :1;                                       /* DDC Data Receive Bit 3 */
    byte DRD4        :1;                                       /* DDC Data Receive Bit 4 */
    byte DRD5        :1;                                       /* DDC Data Receive Bit 5 */
    byte DRD6        :1;                                       /* DDC Data Receive Bit 6 */
    byte DRD7        :1;                                       /* DDC Data Receive Bit 7 */
  } Bits;
} DDCDRRSTR;
extern volatile DDCDRRSTR _DDCDRR;
#define DDCDRR                          _DDCDRR.Byte
#define DDCDRR_DRD0                     _DDCDRR.Bits.DRD0
#define DDCDRR_DRD1                     _DDCDRR.Bits.DRD1
#define DDCDRR_DRD2                     _DDCDRR.Bits.DRD2
#define DDCDRR_DRD3                     _DDCDRR.Bits.DRD3
#define DDCDRR_DRD4                     _DDCDRR.Bits.DRD4
#define DDCDRR_DRD5                     _DDCDRR.Bits.DRD5
#define DDCDRR_DRD6                     _DDCDRR.Bits.DRD6
#define DDCDRR_DRD7                     _DDCDRR.Bits.DRD7

#define DDCDRR_DRD0_MASK                1
#define DDCDRR_DRD1_MASK                2
#define DDCDRR_DRD2_MASK                4
#define DDCDRR_DRD3_MASK                8
#define DDCDRR_DRD4_MASK                16
#define DDCDRR_DRD5_MASK                32
#define DDCDRR_DRD6_MASK                64
#define DDCDRR_DRD7_MASK                128


/*** DDC2ADR - DDC2 Address Register; 0x0000001C ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte D2AD1       :1;                                       /* DDC2 Address Bit 1 */
    byte D2AD2       :1;                                       /* DDC2 Address Bit 2 */
    byte D2AD3       :1;                                       /* DDC2 Address Bit 3 */
    byte D2AD4       :1;                                       /* DDC2 Address Bit 4 */
    byte D2AD5       :1;                                       /* DDC2 Address Bit 5 */
    byte D2AD6       :1;                                       /* DDC2 Address Bit 6 */
    byte D2AD7       :1;                                       /* DDC2 Address Bit 7 */
  } Bits;
  struct {
    byte         :1;
    byte grpD2AD_1 :7;
  } MergedBits;
} DDC2ADRSTR;
extern volatile DDC2ADRSTR _DDC2ADR;
#define DDC2ADR                         _DDC2ADR.Byte
#define DDC2ADR_D2AD1                   _DDC2ADR.Bits.D2AD1
#define DDC2ADR_D2AD2                   _DDC2ADR.Bits.D2AD2
#define DDC2ADR_D2AD3                   _DDC2ADR.Bits.D2AD3
#define DDC2ADR_D2AD4                   _DDC2ADR.Bits.D2AD4
#define DDC2ADR_D2AD5                   _DDC2ADR.Bits.D2AD5
#define DDC2ADR_D2AD6                   _DDC2ADR.Bits.D2AD6
#define DDC2ADR_D2AD7                   _DDC2ADR.Bits.D2AD7
#define DDC2ADR_D2AD_1                  _DDC2ADR.MergedBits.grpD2AD_1
#define DDC2ADR_D2AD                    DDC2ADR_D2AD_1

#define DDC2ADR_D2AD1_MASK              2
#define DDC2ADR_D2AD2_MASK              4
#define DDC2ADR_D2AD3_MASK              8
#define DDC2ADR_D2AD4_MASK              16
#define DDC2ADR_D2AD5_MASK              32
#define DDC2ADR_D2AD6_MASK              64
#define DDC2ADR_D2AD7_MASK              128
#define DDC2ADR_D2AD_1_MASK             254
#define DDC2ADR_D2AD_1_BITNUM           1


/*** INTSCR - IRQ Status and Control Register; 0x0000001E ***/
typedef union {
  byte Byte;
  struct {
    byte MODE        :1;                                       /* IRQ Edge/Level Select Bit */
    byte IMASK       :1;                                       /* IRQ Interrupt Mask Bit */
    byte ACK         :1;                                       /* IRQ Interrupt Request Acknowledge Bit */
    byte IRQF        :1;                                       /* IRQ Flag */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} INTSCRSTR;
extern volatile INTSCRSTR _INTSCR;
#define INTSCR                          _INTSCR.Byte
#define INTSCR_MODE                     _INTSCR.Bits.MODE
#define INTSCR_IMASK                    _INTSCR.Bits.IMASK
#define INTSCR_ACK                      _INTSCR.Bits.ACK
#define INTSCR_IRQF                     _INTSCR.Bits.IRQF

#define INTSCR_MODE_MASK                1
#define INTSCR_IMASK_MASK               2
#define INTSCR_ACK_MASK                 4
#define INTSCR_IRQF_MASK                8


/*** CONFIG - Configuration Register; 0x0000001F ***/
typedef union {
  byte Byte;
  struct {
    byte COPD        :1;                                       /* COP Disable Bit */
    byte STOP        :1;                                       /* STOP Instruction Enable Bit */
    byte COPRS       :1;                                       /* COP Rate Select Bit */
    byte SSREC       :1;                                       /* Short Stop Recovery Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} CONFIGSTR;
extern volatile CONFIGSTR _CONFIG;
#define CONFIG                          _CONFIG.Byte
#define CONFIG_COPD                     _CONFIG.Bits.COPD
#define CONFIG_STOP                     _CONFIG.Bits.STOP
#define CONFIG_COPRS                    _CONFIG.Bits.COPRS
#define CONFIG_SSREC                    _CONFIG.Bits.SSREC

#define CONFIG_COPD_MASK                1
#define CONFIG_STOP_MASK                2
#define CONFIG_COPRS_MASK               4
#define CONFIG_SSREC_MASK               8


/*** DE0D0 - USB Embedded Device Endpoint 0 Data Register 0; 0x00000020 ***/
typedef union {
  byte Byte;
  struct {
    byte DE0R00_DE0T00 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 0 Bit 0, Embedded Device Endpoint 0 Transmit Data Buffer 0 Bit 0 */
    byte DE0R01_DE0T01 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 0 Bit 1, Embedded Device Endpoint 0 Transmit Data Buffer 0 Bit 1 */
    byte DE0R02_DE0T02 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 0 Bit 2, Embedded Device Endpoint 0 Transmit Data Buffer 0 Bit 2 */
    byte DE0R03_DE0T03 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 0 Bit 3, Embedded Device Endpoint 0 Transmit Data Buffer 0 Bit 3 */
    byte DE0R04_DE0T04 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 0 Bit 4, Embedded Device Endpoint 0 Transmit Data Buffer 0 Bit 4 */
    byte DE0R05_DE0T05 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 0 Bit 5, Embedded Device Endpoint 0 Transmit Data Buffer 0 Bit 5 */
    byte DE0R06_DE0T06 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 0 Bit 6, Embedded Device Endpoint 0 Transmit Data Buffer 0 Bit 6 */
    byte DE0R07_DE0T07 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 0 Bit 7, Embedded Device Endpoint 0 Transmit Data Buffer 0 Bit 7 */
  } Bits;
} DE0D0STR;
extern volatile DE0D0STR _DE0D0;
#define DE0D0                           _DE0D0.Byte
#define DE0D0_DE0R00_DE0T00             _DE0D0.Bits.DE0R00_DE0T00
#define DE0D0_DE0R01_DE0T01             _DE0D0.Bits.DE0R01_DE0T01
#define DE0D0_DE0R02_DE0T02             _DE0D0.Bits.DE0R02_DE0T02
#define DE0D0_DE0R03_DE0T03             _DE0D0.Bits.DE0R03_DE0T03
#define DE0D0_DE0R04_DE0T04             _DE0D0.Bits.DE0R04_DE0T04
#define DE0D0_DE0R05_DE0T05             _DE0D0.Bits.DE0R05_DE0T05
#define DE0D0_DE0R06_DE0T06             _DE0D0.Bits.DE0R06_DE0T06
#define DE0D0_DE0R07_DE0T07             _DE0D0.Bits.DE0R07_DE0T07
/* DE0D_ARR: Access 8 DE0Dx registers in an array */
#define DE0D_ARR                        ((volatile byte * __far) &DE0D0)

#define DE0D0_DE0R00_DE0T00_MASK        1
#define DE0D0_DE0R01_DE0T01_MASK        2
#define DE0D0_DE0R02_DE0T02_MASK        4
#define DE0D0_DE0R03_DE0T03_MASK        8
#define DE0D0_DE0R04_DE0T04_MASK        16
#define DE0D0_DE0R05_DE0T05_MASK        32
#define DE0D0_DE0R06_DE0T06_MASK        64
#define DE0D0_DE0R07_DE0T07_MASK        128


/*** DE0D1 - USB Embedded Device Endpoint 0 Data Register 1; 0x00000021 ***/
typedef union {
  byte Byte;
  struct {
    byte DE0R10_DE0T10 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 1 Bit 0, Embedded Device Endpoint 0 Transmit Data Buffer 1 Bit 0 */
    byte DE0R11_DE0T11 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 1 Bit 1, Embedded Device Endpoint 0 Transmit Data Buffer 1 Bit 1 */
    byte DE0R12_DE0T12 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 1 Bit 2, Embedded Device Endpoint 0 Transmit Data Buffer 1 Bit 2 */
    byte DE0R13_DE0T13 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 1 Bit 3, Embedded Device Endpoint 0 Transmit Data Buffer 1 Bit 3 */
    byte DE0R14_DE0T14 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 1 Bit 4, Embedded Device Endpoint 0 Transmit Data Buffer 1 Bit 4 */
    byte DE0R15_DE0T15 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 1 Bit 5, Embedded Device Endpoint 0 Transmit Data Buffer 1 Bit 5 */
    byte DE0R16_DE0T16 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 1 Bit 6, Embedded Device Endpoint 0 Transmit Data Buffer 1 Bit 6 */
    byte DE0R17_DE0T17 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 1 Bit 7, Embedded Device Endpoint 0 Transmit Data Buffer 1 Bit 7 */
  } Bits;
} DE0D1STR;
extern volatile DE0D1STR _DE0D1;
#define DE0D1                           _DE0D1.Byte
#define DE0D1_DE0R10_DE0T10             _DE0D1.Bits.DE0R10_DE0T10
#define DE0D1_DE0R11_DE0T11             _DE0D1.Bits.DE0R11_DE0T11
#define DE0D1_DE0R12_DE0T12             _DE0D1.Bits.DE0R12_DE0T12
#define DE0D1_DE0R13_DE0T13             _DE0D1.Bits.DE0R13_DE0T13
#define DE0D1_DE0R14_DE0T14             _DE0D1.Bits.DE0R14_DE0T14
#define DE0D1_DE0R15_DE0T15             _DE0D1.Bits.DE0R15_DE0T15
#define DE0D1_DE0R16_DE0T16             _DE0D1.Bits.DE0R16_DE0T16
#define DE0D1_DE0R17_DE0T17             _DE0D1.Bits.DE0R17_DE0T17

#define DE0D1_DE0R10_DE0T10_MASK        1
#define DE0D1_DE0R11_DE0T11_MASK        2
#define DE0D1_DE0R12_DE0T12_MASK        4
#define DE0D1_DE0R13_DE0T13_MASK        8
#define DE0D1_DE0R14_DE0T14_MASK        16
#define DE0D1_DE0R15_DE0T15_MASK        32
#define DE0D1_DE0R16_DE0T16_MASK        64
#define DE0D1_DE0R17_DE0T17_MASK        128


/*** DE0D2 - USB Embedded Device Endpoint 0 Data Register 2; 0x00000022 ***/
typedef union {
  byte Byte;
  struct {
    byte DE0R20_DE0T20 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 2 Bit 0, Embedded Device Endpoint 0 Transmit Data Buffer 2 Bit 0 */
    byte DE0R21_DE0T21 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 2 Bit 1, Embedded Device Endpoint 0 Transmit Data Buffer 2 Bit 1 */
    byte DE0R22_DE0T22 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 2 Bit 2, Embedded Device Endpoint 0 Transmit Data Buffer 2 Bit 2 */
    byte DE0R23_DE0T23 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 2 Bit 3, Embedded Device Endpoint 0 Transmit Data Buffer 2 Bit 3 */
    byte DE0R24_DE0T24 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 2 Bit 4, Embedded Device Endpoint 0 Transmit Data Buffer 2 Bit 4 */
    byte DE0R25_DE0T25 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 2 Bit 5, Embedded Device Endpoint 0 Transmit Data Buffer 2 Bit 5 */
    byte DE0R26_DE0T26 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 2 Bit 6, Embedded Device Endpoint 0 Transmit Data Buffer 2 Bit 6 */
    byte DE0R27_DE0T27 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 2 Bit 7, Embedded Device Endpoint 0 Transmit Data Buffer 2 Bit 7 */
  } Bits;
} DE0D2STR;
extern volatile DE0D2STR _DE0D2;
#define DE0D2                           _DE0D2.Byte
#define DE0D2_DE0R20_DE0T20             _DE0D2.Bits.DE0R20_DE0T20
#define DE0D2_DE0R21_DE0T21             _DE0D2.Bits.DE0R21_DE0T21
#define DE0D2_DE0R22_DE0T22             _DE0D2.Bits.DE0R22_DE0T22
#define DE0D2_DE0R23_DE0T23             _DE0D2.Bits.DE0R23_DE0T23
#define DE0D2_DE0R24_DE0T24             _DE0D2.Bits.DE0R24_DE0T24
#define DE0D2_DE0R25_DE0T25             _DE0D2.Bits.DE0R25_DE0T25
#define DE0D2_DE0R26_DE0T26             _DE0D2.Bits.DE0R26_DE0T26
#define DE0D2_DE0R27_DE0T27             _DE0D2.Bits.DE0R27_DE0T27

#define DE0D2_DE0R20_DE0T20_MASK        1
#define DE0D2_DE0R21_DE0T21_MASK        2
#define DE0D2_DE0R22_DE0T22_MASK        4
#define DE0D2_DE0R23_DE0T23_MASK        8
#define DE0D2_DE0R24_DE0T24_MASK        16
#define DE0D2_DE0R25_DE0T25_MASK        32
#define DE0D2_DE0R26_DE0T26_MASK        64
#define DE0D2_DE0R27_DE0T27_MASK        128


/*** DE0D3 - USB Embedded Device Endpoint 0 Data Register 3; 0x00000023 ***/
typedef union {
  byte Byte;
  struct {
    byte DE0R30_DE0T30 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 3 Bit 0, Embedded Device Endpoint 0 Transmit Data Buffer 3 Bit 0 */
    byte DE0R31_DE0T31 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 3 Bit 1, Embedded Device Endpoint 0 Transmit Data Buffer 3 Bit 1 */
    byte DE0R32_DE0T32 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 3 Bit 2, Embedded Device Endpoint 0 Transmit Data Buffer 3 Bit 2 */
    byte DE0R33_DE0T33 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 3 Bit 3, Embedded Device Endpoint 0 Transmit Data Buffer 3 Bit 3 */
    byte DE0R34_DE0T34 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 3 Bit 4, Embedded Device Endpoint 0 Transmit Data Buffer 3 Bit 4 */
    byte DE0R35_DE0T35 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 3 Bit 5, Embedded Device Endpoint 0 Transmit Data Buffer 3 Bit 5 */
    byte DE0R36_DE0T36 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 3 Bit 6, Embedded Device Endpoint 0 Transmit Data Buffer 3 Bit 6 */
    byte DE0R37_DE0T37 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 3 Bit 7, Embedded Device Endpoint 0 Transmit Data Buffer 3 Bit 7 */
  } Bits;
} DE0D3STR;
extern volatile DE0D3STR _DE0D3;
#define DE0D3                           _DE0D3.Byte
#define DE0D3_DE0R30_DE0T30             _DE0D3.Bits.DE0R30_DE0T30
#define DE0D3_DE0R31_DE0T31             _DE0D3.Bits.DE0R31_DE0T31
#define DE0D3_DE0R32_DE0T32             _DE0D3.Bits.DE0R32_DE0T32
#define DE0D3_DE0R33_DE0T33             _DE0D3.Bits.DE0R33_DE0T33
#define DE0D3_DE0R34_DE0T34             _DE0D3.Bits.DE0R34_DE0T34
#define DE0D3_DE0R35_DE0T35             _DE0D3.Bits.DE0R35_DE0T35
#define DE0D3_DE0R36_DE0T36             _DE0D3.Bits.DE0R36_DE0T36
#define DE0D3_DE0R37_DE0T37             _DE0D3.Bits.DE0R37_DE0T37

#define DE0D3_DE0R30_DE0T30_MASK        1
#define DE0D3_DE0R31_DE0T31_MASK        2
#define DE0D3_DE0R32_DE0T32_MASK        4
#define DE0D3_DE0R33_DE0T33_MASK        8
#define DE0D3_DE0R34_DE0T34_MASK        16
#define DE0D3_DE0R35_DE0T35_MASK        32
#define DE0D3_DE0R36_DE0T36_MASK        64
#define DE0D3_DE0R37_DE0T37_MASK        128


/*** DE0D4 - USB Embedded Device Endpoint 0 Data Register 4; 0x00000024 ***/
typedef union {
  byte Byte;
  struct {
    byte DE0R40_DE0T40 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 4 Bit 0, Embedded Device Endpoint 0 Transmit Data Buffer 4 Bit 0 */
    byte DE0R41_DE0T41 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 4 Bit 1, Embedded Device Endpoint 0 Transmit Data Buffer 4 Bit 1 */
    byte DE0R42_DE0T42 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 4 Bit 2, Embedded Device Endpoint 0 Transmit Data Buffer 4 Bit 2 */
    byte DE0R43_DE0T43 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 4 Bit 3, Embedded Device Endpoint 0 Transmit Data Buffer 4 Bit 3 */
    byte DE0R44_DE0T44 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 4 Bit 4, Embedded Device Endpoint 0 Transmit Data Buffer 4 Bit 4 */
    byte DE0R45_DE0T45 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 4 Bit 5, Embedded Device Endpoint 0 Transmit Data Buffer 4 Bit 5 */
    byte DE0R46_DE0T46 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 4 Bit 6, Embedded Device Endpoint 0 Transmit Data Buffer 4 Bit 6 */
    byte DE0R47_DE0T47 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 4 Bit 7, Embedded Device Endpoint 0 Transmit Data Buffer 4 Bit 7 */
  } Bits;
} DE0D4STR;
extern volatile DE0D4STR _DE0D4;
#define DE0D4                           _DE0D4.Byte
#define DE0D4_DE0R40_DE0T40             _DE0D4.Bits.DE0R40_DE0T40
#define DE0D4_DE0R41_DE0T41             _DE0D4.Bits.DE0R41_DE0T41
#define DE0D4_DE0R42_DE0T42             _DE0D4.Bits.DE0R42_DE0T42
#define DE0D4_DE0R43_DE0T43             _DE0D4.Bits.DE0R43_DE0T43
#define DE0D4_DE0R44_DE0T44             _DE0D4.Bits.DE0R44_DE0T44
#define DE0D4_DE0R45_DE0T45             _DE0D4.Bits.DE0R45_DE0T45
#define DE0D4_DE0R46_DE0T46             _DE0D4.Bits.DE0R46_DE0T46
#define DE0D4_DE0R47_DE0T47             _DE0D4.Bits.DE0R47_DE0T47

#define DE0D4_DE0R40_DE0T40_MASK        1
#define DE0D4_DE0R41_DE0T41_MASK        2
#define DE0D4_DE0R42_DE0T42_MASK        4
#define DE0D4_DE0R43_DE0T43_MASK        8
#define DE0D4_DE0R44_DE0T44_MASK        16
#define DE0D4_DE0R45_DE0T45_MASK        32
#define DE0D4_DE0R46_DE0T46_MASK        64
#define DE0D4_DE0R47_DE0T47_MASK        128


/*** DE0D5 - USB Embedded Device Endpoint 0 Data Register 5; 0x00000025 ***/
typedef union {
  byte Byte;
  struct {
    byte DE0R50_DE0T50 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 5 Bit 0, Embedded Device Endpoint 0 Transmit Data Buffer 5 Bit 0 */
    byte DE0R51_DE0T51 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 5 Bit 1, Embedded Device Endpoint 0 Transmit Data Buffer 5 Bit 1 */
    byte DE0R52_DE0T52 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 5 Bit 2, Embedded Device Endpoint 0 Transmit Data Buffer 5 Bit 2 */
    byte DE0R53_DE0T53 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 5 Bit 3, Embedded Device Endpoint 0 Transmit Data Buffer 5 Bit 3 */
    byte DE0R54_DE0T54 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 5 Bit 4, Embedded Device Endpoint 0 Transmit Data Buffer 5 Bit 4 */
    byte DE0R55_DE0T55 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 5 Bit 5, Embedded Device Endpoint 0 Transmit Data Buffer 5 Bit 5 */
    byte DE0R56_DE0T56 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 5 Bit 6, Embedded Device Endpoint 0 Transmit Data Buffer 5 Bit 6 */
    byte DE0R57_DE0T57 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 5 Bit 7, Embedded Device Endpoint 0 Transmit Data Buffer 5 Bit 7 */
  } Bits;
} DE0D5STR;
extern volatile DE0D5STR _DE0D5;
#define DE0D5                           _DE0D5.Byte
#define DE0D5_DE0R50_DE0T50             _DE0D5.Bits.DE0R50_DE0T50
#define DE0D5_DE0R51_DE0T51             _DE0D5.Bits.DE0R51_DE0T51
#define DE0D5_DE0R52_DE0T52             _DE0D5.Bits.DE0R52_DE0T52
#define DE0D5_DE0R53_DE0T53             _DE0D5.Bits.DE0R53_DE0T53
#define DE0D5_DE0R54_DE0T54             _DE0D5.Bits.DE0R54_DE0T54
#define DE0D5_DE0R55_DE0T55             _DE0D5.Bits.DE0R55_DE0T55
#define DE0D5_DE0R56_DE0T56             _DE0D5.Bits.DE0R56_DE0T56
#define DE0D5_DE0R57_DE0T57             _DE0D5.Bits.DE0R57_DE0T57

#define DE0D5_DE0R50_DE0T50_MASK        1
#define DE0D5_DE0R51_DE0T51_MASK        2
#define DE0D5_DE0R52_DE0T52_MASK        4
#define DE0D5_DE0R53_DE0T53_MASK        8
#define DE0D5_DE0R54_DE0T54_MASK        16
#define DE0D5_DE0R55_DE0T55_MASK        32
#define DE0D5_DE0R56_DE0T56_MASK        64
#define DE0D5_DE0R57_DE0T57_MASK        128


/*** DE0D6 - USB Embedded Device Endpoint 0 Data Register 6; 0x00000026 ***/
typedef union {
  byte Byte;
  struct {
    byte DE0R60_DE0T60 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 6 Bit 0, Embedded Device Endpoint 0 Transmit Data Buffer 6 Bit 0 */
    byte DE0R61_DE0T61 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 6 Bit 1, Embedded Device Endpoint 0 Transmit Data Buffer 6 Bit 1 */
    byte DE0R62_DE0T62 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 6 Bit 2, Embedded Device Endpoint 0 Transmit Data Buffer 6 Bit 2 */
    byte DE0R63_DE0T63 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 6 Bit 3, Embedded Device Endpoint 0 Transmit Data Buffer 6 Bit 3 */
    byte DE0R64_DE0T64 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 6 Bit 4, Embedded Device Endpoint 0 Transmit Data Buffer 6 Bit 4 */
    byte DE0R65_DE0T65 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 6 Bit 5, Embedded Device Endpoint 0 Transmit Data Buffer 6 Bit 5 */
    byte DE0R66_DE0T66 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 6 Bit 6, Embedded Device Endpoint 0 Transmit Data Buffer 6 Bit 6 */
    byte DE0R67_DE0T67 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 6 Bit 7, Embedded Device Endpoint 0 Transmit Data Buffer 6 Bit 7 */
  } Bits;
} DE0D6STR;
extern volatile DE0D6STR _DE0D6;
#define DE0D6                           _DE0D6.Byte
#define DE0D6_DE0R60_DE0T60             _DE0D6.Bits.DE0R60_DE0T60
#define DE0D6_DE0R61_DE0T61             _DE0D6.Bits.DE0R61_DE0T61
#define DE0D6_DE0R62_DE0T62             _DE0D6.Bits.DE0R62_DE0T62
#define DE0D6_DE0R63_DE0T63             _DE0D6.Bits.DE0R63_DE0T63
#define DE0D6_DE0R64_DE0T64             _DE0D6.Bits.DE0R64_DE0T64
#define DE0D6_DE0R65_DE0T65             _DE0D6.Bits.DE0R65_DE0T65
#define DE0D6_DE0R66_DE0T66             _DE0D6.Bits.DE0R66_DE0T66
#define DE0D6_DE0R67_DE0T67             _DE0D6.Bits.DE0R67_DE0T67

#define DE0D6_DE0R60_DE0T60_MASK        1
#define DE0D6_DE0R61_DE0T61_MASK        2
#define DE0D6_DE0R62_DE0T62_MASK        4
#define DE0D6_DE0R63_DE0T63_MASK        8
#define DE0D6_DE0R64_DE0T64_MASK        16
#define DE0D6_DE0R65_DE0T65_MASK        32
#define DE0D6_DE0R66_DE0T66_MASK        64
#define DE0D6_DE0R67_DE0T67_MASK        128


/*** DE0D7 - USB Embedded Device Endpoint 0 Data Register 7; 0x00000027 ***/
typedef union {
  byte Byte;
  struct {
    byte DE0R70_DE0T70 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 7 Bit 0, Embedded Device Endpoint 0 Transmit Data Buffer 7 Bit 0 */
    byte DE0R71_DE0T71 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 7 Bit 1, Embedded Device Endpoint 0 Transmit Data Buffer 7 Bit 1 */
    byte DE0R72_DE0T72 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 7 Bit 2, Embedded Device Endpoint 0 Transmit Data Buffer 7 Bit 2 */
    byte DE0R73_DE0T73 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 7 Bit 3, Embedded Device Endpoint 0 Transmit Data Buffer 7 Bit 3 */
    byte DE0R74_DE0T74 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 7 Bit 4, Embedded Device Endpoint 0 Transmit Data Buffer 7 Bit 4 */
    byte DE0R75_DE0T75 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 7 Bit 5, Embedded Device Endpoint 0 Transmit Data Buffer 7 Bit 5 */
    byte DE0R76_DE0T76 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 7 Bit 6, Embedded Device Endpoint 0 Transmit Data Buffer 7 Bit 6 */
    byte DE0R77_DE0T77 :1;                                     /* Embedded Device Endpoint 0 Receive Data Buffer 7 Bit 7, Embedded Device Endpoint 0 Transmit Data Buffer 7 Bit 7 */
  } Bits;
} DE0D7STR;
extern volatile DE0D7STR _DE0D7;
#define DE0D7                           _DE0D7.Byte
#define DE0D7_DE0R70_DE0T70             _DE0D7.Bits.DE0R70_DE0T70
#define DE0D7_DE0R71_DE0T71             _DE0D7.Bits.DE0R71_DE0T71
#define DE0D7_DE0R72_DE0T72             _DE0D7.Bits.DE0R72_DE0T72
#define DE0D7_DE0R73_DE0T73             _DE0D7.Bits.DE0R73_DE0T73
#define DE0D7_DE0R74_DE0T74             _DE0D7.Bits.DE0R74_DE0T74
#define DE0D7_DE0R75_DE0T75             _DE0D7.Bits.DE0R75_DE0T75
#define DE0D7_DE0R76_DE0T76             _DE0D7.Bits.DE0R76_DE0T76
#define DE0D7_DE0R77_DE0T77             _DE0D7.Bits.DE0R77_DE0T77

#define DE0D7_DE0R70_DE0T70_MASK        1
#define DE0D7_DE0R71_DE0T71_MASK        2
#define DE0D7_DE0R72_DE0T72_MASK        4
#define DE0D7_DE0R73_DE0T73_MASK        8
#define DE0D7_DE0R74_DE0T74_MASK        16
#define DE0D7_DE0R75_DE0T75_MASK        32
#define DE0D7_DE0R76_DE0T76_MASK        64
#define DE0D7_DE0R77_DE0T77_MASK        128


/*** DE1D0 - USB Embedded Device Endpoint 1/2 Data Register 0; 0x00000028 ***/
typedef union {
  byte Byte;
  struct {
    byte DE1T00      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 0 Bit 0 */
    byte DE1T01      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 0 Bit 1 */
    byte DE1T02      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 0 Bit 2 */
    byte DE1T03      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 0 Bit 3 */
    byte DE1T04      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 0 Bit 4 */
    byte DE1T05      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 0 Bit 5 */
    byte DE1T06      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 0 Bit 6 */
    byte DE1T07      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 0 Bit 7 */
  } Bits;
} DE1D0STR;
extern volatile DE1D0STR _DE1D0;
#define DE1D0                           _DE1D0.Byte
#define DE1D0_DE1T00                    _DE1D0.Bits.DE1T00
#define DE1D0_DE1T01                    _DE1D0.Bits.DE1T01
#define DE1D0_DE1T02                    _DE1D0.Bits.DE1T02
#define DE1D0_DE1T03                    _DE1D0.Bits.DE1T03
#define DE1D0_DE1T04                    _DE1D0.Bits.DE1T04
#define DE1D0_DE1T05                    _DE1D0.Bits.DE1T05
#define DE1D0_DE1T06                    _DE1D0.Bits.DE1T06
#define DE1D0_DE1T07                    _DE1D0.Bits.DE1T07
/* DE1D_ARR: Access 8 DE1Dx registers in an array */
#define DE1D_ARR                        ((volatile byte * __far) &DE1D0)

#define DE1D0_DE1T00_MASK               1
#define DE1D0_DE1T01_MASK               2
#define DE1D0_DE1T02_MASK               4
#define DE1D0_DE1T03_MASK               8
#define DE1D0_DE1T04_MASK               16
#define DE1D0_DE1T05_MASK               32
#define DE1D0_DE1T06_MASK               64
#define DE1D0_DE1T07_MASK               128


/*** DE1D1 - USB Embedded Device Endpoint 1/2 Data Register 1; 0x00000029 ***/
typedef union {
  byte Byte;
  struct {
    byte DE1T10      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 1 Bit 0 */
    byte DE1T11      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 1 Bit 1 */
    byte DE1T12      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 1 Bit 2 */
    byte DE1T13      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 1 Bit 3 */
    byte DE1T14      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 1 Bit 4 */
    byte DE1T15      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 1 Bit 5 */
    byte DE1T16      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 1 Bit 6 */
    byte DE1T17      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 1 Bit 7 */
  } Bits;
} DE1D1STR;
extern volatile DE1D1STR _DE1D1;
#define DE1D1                           _DE1D1.Byte
#define DE1D1_DE1T10                    _DE1D1.Bits.DE1T10
#define DE1D1_DE1T11                    _DE1D1.Bits.DE1T11
#define DE1D1_DE1T12                    _DE1D1.Bits.DE1T12
#define DE1D1_DE1T13                    _DE1D1.Bits.DE1T13
#define DE1D1_DE1T14                    _DE1D1.Bits.DE1T14
#define DE1D1_DE1T15                    _DE1D1.Bits.DE1T15
#define DE1D1_DE1T16                    _DE1D1.Bits.DE1T16
#define DE1D1_DE1T17                    _DE1D1.Bits.DE1T17

#define DE1D1_DE1T10_MASK               1
#define DE1D1_DE1T11_MASK               2
#define DE1D1_DE1T12_MASK               4
#define DE1D1_DE1T13_MASK               8
#define DE1D1_DE1T14_MASK               16
#define DE1D1_DE1T15_MASK               32
#define DE1D1_DE1T16_MASK               64
#define DE1D1_DE1T17_MASK               128


/*** DE1D2 - USB Embedded Device Endpoint 1/2 Data Register 2; 0x0000002A ***/
typedef union {
  byte Byte;
  struct {
    byte DE1T20      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 2 Bit 0 */
    byte DE1T21      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 2 Bit 1 */
    byte DE1T22      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 2 Bit 2 */
    byte DE1T23      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 2 Bit 3 */
    byte DE1T24      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 2 Bit 4 */
    byte DE1T25      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 2 Bit 5 */
    byte DE1T26      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 2 Bit 6 */
    byte DE1T27      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 2 Bit 7 */
  } Bits;
} DE1D2STR;
extern volatile DE1D2STR _DE1D2;
#define DE1D2                           _DE1D2.Byte
#define DE1D2_DE1T20                    _DE1D2.Bits.DE1T20
#define DE1D2_DE1T21                    _DE1D2.Bits.DE1T21
#define DE1D2_DE1T22                    _DE1D2.Bits.DE1T22
#define DE1D2_DE1T23                    _DE1D2.Bits.DE1T23
#define DE1D2_DE1T24                    _DE1D2.Bits.DE1T24
#define DE1D2_DE1T25                    _DE1D2.Bits.DE1T25
#define DE1D2_DE1T26                    _DE1D2.Bits.DE1T26
#define DE1D2_DE1T27                    _DE1D2.Bits.DE1T27

#define DE1D2_DE1T20_MASK               1
#define DE1D2_DE1T21_MASK               2
#define DE1D2_DE1T22_MASK               4
#define DE1D2_DE1T23_MASK               8
#define DE1D2_DE1T24_MASK               16
#define DE1D2_DE1T25_MASK               32
#define DE1D2_DE1T26_MASK               64
#define DE1D2_DE1T27_MASK               128


/*** DE1D3 - USB Embedded Device Endpoint 1/2 Data Register 3; 0x0000002B ***/
typedef union {
  byte Byte;
  struct {
    byte DE1T30      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 3 Bit 0 */
    byte DE1T31      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 3 Bit 1 */
    byte DE1T32      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 3 Bit 2 */
    byte DE1T33      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 3 Bit 3 */
    byte DE1T34      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 3 Bit 4 */
    byte DE1T35      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 3 Bit 5 */
    byte DE1T36      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 3 Bit 6 */
    byte DE1T37      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 3 Bit 7 */
  } Bits;
} DE1D3STR;
extern volatile DE1D3STR _DE1D3;
#define DE1D3                           _DE1D3.Byte
#define DE1D3_DE1T30                    _DE1D3.Bits.DE1T30
#define DE1D3_DE1T31                    _DE1D3.Bits.DE1T31
#define DE1D3_DE1T32                    _DE1D3.Bits.DE1T32
#define DE1D3_DE1T33                    _DE1D3.Bits.DE1T33
#define DE1D3_DE1T34                    _DE1D3.Bits.DE1T34
#define DE1D3_DE1T35                    _DE1D3.Bits.DE1T35
#define DE1D3_DE1T36                    _DE1D3.Bits.DE1T36
#define DE1D3_DE1T37                    _DE1D3.Bits.DE1T37

#define DE1D3_DE1T30_MASK               1
#define DE1D3_DE1T31_MASK               2
#define DE1D3_DE1T32_MASK               4
#define DE1D3_DE1T33_MASK               8
#define DE1D3_DE1T34_MASK               16
#define DE1D3_DE1T35_MASK               32
#define DE1D3_DE1T36_MASK               64
#define DE1D3_DE1T37_MASK               128


/*** DE1D4 - USB Embedded Device Endpoint 1/2 Data Register 4; 0x0000002C ***/
typedef union {
  byte Byte;
  struct {
    byte DE1T40      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 4 Bit 0 */
    byte DE1T41      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 4 Bit 1 */
    byte DE1T42      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 4 Bit 2 */
    byte DE1T43      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 4 Bit 3 */
    byte DE1T44      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 4 Bit 4 */
    byte DE1T45      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 4 Bit 5 */
    byte DE1T46      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 4 Bit 6 */
    byte DE1T47      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 4 Bit 7 */
  } Bits;
} DE1D4STR;
extern volatile DE1D4STR _DE1D4;
#define DE1D4                           _DE1D4.Byte
#define DE1D4_DE1T40                    _DE1D4.Bits.DE1T40
#define DE1D4_DE1T41                    _DE1D4.Bits.DE1T41
#define DE1D4_DE1T42                    _DE1D4.Bits.DE1T42
#define DE1D4_DE1T43                    _DE1D4.Bits.DE1T43
#define DE1D4_DE1T44                    _DE1D4.Bits.DE1T44
#define DE1D4_DE1T45                    _DE1D4.Bits.DE1T45
#define DE1D4_DE1T46                    _DE1D4.Bits.DE1T46
#define DE1D4_DE1T47                    _DE1D4.Bits.DE1T47

#define DE1D4_DE1T40_MASK               1
#define DE1D4_DE1T41_MASK               2
#define DE1D4_DE1T42_MASK               4
#define DE1D4_DE1T43_MASK               8
#define DE1D4_DE1T44_MASK               16
#define DE1D4_DE1T45_MASK               32
#define DE1D4_DE1T46_MASK               64
#define DE1D4_DE1T47_MASK               128


/*** DE1D5 - USB Embedded Device Endpoint 1/2 Data Register 5; 0x0000002D ***/
typedef union {
  byte Byte;
  struct {
    byte DE1T50      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 5 Bit 0 */
    byte DE1T51      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 5 Bit 1 */
    byte DE1T52      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 5 Bit 2 */
    byte DE1T53      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 5 Bit 3 */
    byte DE1T54      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 5 Bit 4 */
    byte DE1T55      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 5 Bit 5 */
    byte DE1T56      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 5 Bit 6 */
    byte DE1T57      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 5 Bit 7 */
  } Bits;
} DE1D5STR;
extern volatile DE1D5STR _DE1D5;
#define DE1D5                           _DE1D5.Byte
#define DE1D5_DE1T50                    _DE1D5.Bits.DE1T50
#define DE1D5_DE1T51                    _DE1D5.Bits.DE1T51
#define DE1D5_DE1T52                    _DE1D5.Bits.DE1T52
#define DE1D5_DE1T53                    _DE1D5.Bits.DE1T53
#define DE1D5_DE1T54                    _DE1D5.Bits.DE1T54
#define DE1D5_DE1T55                    _DE1D5.Bits.DE1T55
#define DE1D5_DE1T56                    _DE1D5.Bits.DE1T56
#define DE1D5_DE1T57                    _DE1D5.Bits.DE1T57

#define DE1D5_DE1T50_MASK               1
#define DE1D5_DE1T51_MASK               2
#define DE1D5_DE1T52_MASK               4
#define DE1D5_DE1T53_MASK               8
#define DE1D5_DE1T54_MASK               16
#define DE1D5_DE1T55_MASK               32
#define DE1D5_DE1T56_MASK               64
#define DE1D5_DE1T57_MASK               128


/*** DE1D6 - USB Embedded Device Endpoint 1/2 Data Register 6; 0x0000002E ***/
typedef union {
  byte Byte;
  struct {
    byte DE1T60      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 6 Bit 0 */
    byte DE1T61      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 6 Bit 1 */
    byte DE1T62      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 6 Bit 2 */
    byte DE1T63      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 6 Bit 3 */
    byte DE1T64      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 6 Bit 4 */
    byte DE1T65      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 6 Bit 5 */
    byte DE1T66      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 6 Bit 6 */
    byte DE1T67      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 6 Bit 7 */
  } Bits;
} DE1D6STR;
extern volatile DE1D6STR _DE1D6;
#define DE1D6                           _DE1D6.Byte
#define DE1D6_DE1T60                    _DE1D6.Bits.DE1T60
#define DE1D6_DE1T61                    _DE1D6.Bits.DE1T61
#define DE1D6_DE1T62                    _DE1D6.Bits.DE1T62
#define DE1D6_DE1T63                    _DE1D6.Bits.DE1T63
#define DE1D6_DE1T64                    _DE1D6.Bits.DE1T64
#define DE1D6_DE1T65                    _DE1D6.Bits.DE1T65
#define DE1D6_DE1T66                    _DE1D6.Bits.DE1T66
#define DE1D6_DE1T67                    _DE1D6.Bits.DE1T67

#define DE1D6_DE1T60_MASK               1
#define DE1D6_DE1T61_MASK               2
#define DE1D6_DE1T62_MASK               4
#define DE1D6_DE1T63_MASK               8
#define DE1D6_DE1T64_MASK               16
#define DE1D6_DE1T65_MASK               32
#define DE1D6_DE1T66_MASK               64
#define DE1D6_DE1T67_MASK               128


/*** DE1D7 - USB Embedded Device Endpoint 1/2 Data Register 7; 0x0000002F ***/
typedef union {
  byte Byte;
  struct {
    byte DE1T70      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 7 Bit 0 */
    byte DE1T71      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 7 Bit 1 */
    byte DE1T72      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 7 Bit 2 */
    byte DE1T73      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 7 Bit 3 */
    byte DE1T74      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 7 Bit 4 */
    byte DE1T75      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 7 Bit 5 */
    byte DE1T76      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 7 Bit 6 */
    byte DE1T77      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Buffer 7 Bit 7 */
  } Bits;
} DE1D7STR;
extern volatile DE1D7STR _DE1D7;
#define DE1D7                           _DE1D7.Byte
#define DE1D7_DE1T70                    _DE1D7.Bits.DE1T70
#define DE1D7_DE1T71                    _DE1D7.Bits.DE1T71
#define DE1D7_DE1T72                    _DE1D7.Bits.DE1T72
#define DE1D7_DE1T73                    _DE1D7.Bits.DE1T73
#define DE1D7_DE1T74                    _DE1D7.Bits.DE1T74
#define DE1D7_DE1T75                    _DE1D7.Bits.DE1T75
#define DE1D7_DE1T76                    _DE1D7.Bits.DE1T76
#define DE1D7_DE1T77                    _DE1D7.Bits.DE1T77

#define DE1D7_DE1T70_MASK               1
#define DE1D7_DE1T71_MASK               2
#define DE1D7_DE1T72_MASK               4
#define DE1D7_DE1T73_MASK               8
#define DE1D7_DE1T74_MASK               16
#define DE1D7_DE1T75_MASK               32
#define DE1D7_DE1T76_MASK               64
#define DE1D7_DE1T77_MASK               128


/*** HE0D0 - USB HUB Endpoint 0 Data Register 0; 0x00000030 ***/
typedef union {
  byte Byte;
  struct {
    byte HE0R00_HE0T00 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 0 Bit 0, HUB Endpoint 0 Transmit Data Buffer 0 Bit 0 */
    byte HE0R01_HE0T01 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 0 Bit 1, HUB Endpoint 0 Transmit Data Buffer 0 Bit 1 */
    byte HE0R02_HE0T02 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 0 Bit 2, HUB Endpoint 0 Transmit Data Buffer 0 Bit 2 */
    byte HE0R03_HE0T03 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 0 Bit 3, HUB Endpoint 0 Transmit Data Buffer 0 Bit 3 */
    byte HE0R04_HE0T04 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 0 Bit 4, HUB Endpoint 0 Transmit Data Buffer 0 Bit 4 */
    byte HE0R05_HE0T05 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 0 Bit 5, HUB Endpoint 0 Transmit Data Buffer 0 Bit 5 */
    byte HE0R06_HE0T06 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 0 Bit 6, HUB Endpoint 0 Transmit Data Buffer 0 Bit 6 */
    byte HE0R07_HE0T07 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 0 Bit 7, HUB Endpoint 0 Transmit Data Buffer 0 Bit 7 */
  } Bits;
} HE0D0STR;
extern volatile HE0D0STR _HE0D0;
#define HE0D0                           _HE0D0.Byte
#define HE0D0_HE0R00_HE0T00             _HE0D0.Bits.HE0R00_HE0T00
#define HE0D0_HE0R01_HE0T01             _HE0D0.Bits.HE0R01_HE0T01
#define HE0D0_HE0R02_HE0T02             _HE0D0.Bits.HE0R02_HE0T02
#define HE0D0_HE0R03_HE0T03             _HE0D0.Bits.HE0R03_HE0T03
#define HE0D0_HE0R04_HE0T04             _HE0D0.Bits.HE0R04_HE0T04
#define HE0D0_HE0R05_HE0T05             _HE0D0.Bits.HE0R05_HE0T05
#define HE0D0_HE0R06_HE0T06             _HE0D0.Bits.HE0R06_HE0T06
#define HE0D0_HE0R07_HE0T07             _HE0D0.Bits.HE0R07_HE0T07
/* HE0D_ARR: Access 8 HE0Dx registers in an array */
#define HE0D_ARR                        ((volatile byte * __far) &HE0D0)

#define HE0D0_HE0R00_HE0T00_MASK        1
#define HE0D0_HE0R01_HE0T01_MASK        2
#define HE0D0_HE0R02_HE0T02_MASK        4
#define HE0D0_HE0R03_HE0T03_MASK        8
#define HE0D0_HE0R04_HE0T04_MASK        16
#define HE0D0_HE0R05_HE0T05_MASK        32
#define HE0D0_HE0R06_HE0T06_MASK        64
#define HE0D0_HE0R07_HE0T07_MASK        128


/*** HE0D1 - USB HUB Endpoint 0 Data Register 1; 0x00000031 ***/
typedef union {
  byte Byte;
  struct {
    byte HE0R10_HE0T10 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 1 Bit 0, HUB Endpoint 0 Transmit Data Buffer 1 Bit 0 */
    byte HE0R11_HE0T11 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 1 Bit 1, HUB Endpoint 0 Transmit Data Buffer 1 Bit 1 */
    byte HE0R12_HE0T12 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 1 Bit 2, HUB Endpoint 0 Transmit Data Buffer 1 Bit 2 */
    byte HE0R13_HE0T13 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 1 Bit 3, HUB Endpoint 0 Transmit Data Buffer 1 Bit 3 */
    byte HE0R14_HE0T14 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 1 Bit 4, HUB Endpoint 0 Transmit Data Buffer 1 Bit 4 */
    byte HE0R15_HE0T15 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 1 Bit 5, HUB Endpoint 0 Transmit Data Buffer 1 Bit 5 */
    byte HE0R16_HE0T16 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 1 Bit 6, HUB Endpoint 0 Transmit Data Buffer 1 Bit 6 */
    byte HE0R17_HE0T17 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 1 Bit 7, HUB Endpoint 0 Transmit Data Buffer 1 Bit 7 */
  } Bits;
} HE0D1STR;
extern volatile HE0D1STR _HE0D1;
#define HE0D1                           _HE0D1.Byte
#define HE0D1_HE0R10_HE0T10             _HE0D1.Bits.HE0R10_HE0T10
#define HE0D1_HE0R11_HE0T11             _HE0D1.Bits.HE0R11_HE0T11
#define HE0D1_HE0R12_HE0T12             _HE0D1.Bits.HE0R12_HE0T12
#define HE0D1_HE0R13_HE0T13             _HE0D1.Bits.HE0R13_HE0T13
#define HE0D1_HE0R14_HE0T14             _HE0D1.Bits.HE0R14_HE0T14
#define HE0D1_HE0R15_HE0T15             _HE0D1.Bits.HE0R15_HE0T15
#define HE0D1_HE0R16_HE0T16             _HE0D1.Bits.HE0R16_HE0T16
#define HE0D1_HE0R17_HE0T17             _HE0D1.Bits.HE0R17_HE0T17

#define HE0D1_HE0R10_HE0T10_MASK        1
#define HE0D1_HE0R11_HE0T11_MASK        2
#define HE0D1_HE0R12_HE0T12_MASK        4
#define HE0D1_HE0R13_HE0T13_MASK        8
#define HE0D1_HE0R14_HE0T14_MASK        16
#define HE0D1_HE0R15_HE0T15_MASK        32
#define HE0D1_HE0R16_HE0T16_MASK        64
#define HE0D1_HE0R17_HE0T17_MASK        128


/*** HE0D2 - USB HUB Endpoint 0 Data Register 2; 0x00000032 ***/
typedef union {
  byte Byte;
  struct {
    byte HE0R20_HE0T20 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 2 Bit 0, HUB Endpoint 0 Transmit Data Buffer 2 Bit 0 */
    byte HE0R21_HE0T21 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 2 Bit 1, HUB Endpoint 0 Transmit Data Buffer 2 Bit 1 */
    byte HE0R22_HE0T22 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 2 Bit 2, HUB Endpoint 0 Transmit Data Buffer 2 Bit 2 */
    byte HE0R23_HE0T23 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 2 Bit 3, HUB Endpoint 0 Transmit Data Buffer 2 Bit 3 */
    byte HE0R24_HE0T24 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 2 Bit 4, HUB Endpoint 0 Transmit Data Buffer 2 Bit 4 */
    byte HE0R25_HE0T25 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 2 Bit 5, HUB Endpoint 0 Transmit Data Buffer 2 Bit 5 */
    byte HE0R26_HE0T26 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 2 Bit 6, HUB Endpoint 0 Transmit Data Buffer 2 Bit 6 */
    byte HE0R27_HE0T27 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 2 Bit 7, HUB Endpoint 0 Transmit Data Buffer 2 Bit 7 */
  } Bits;
} HE0D2STR;
extern volatile HE0D2STR _HE0D2;
#define HE0D2                           _HE0D2.Byte
#define HE0D2_HE0R20_HE0T20             _HE0D2.Bits.HE0R20_HE0T20
#define HE0D2_HE0R21_HE0T21             _HE0D2.Bits.HE0R21_HE0T21
#define HE0D2_HE0R22_HE0T22             _HE0D2.Bits.HE0R22_HE0T22
#define HE0D2_HE0R23_HE0T23             _HE0D2.Bits.HE0R23_HE0T23
#define HE0D2_HE0R24_HE0T24             _HE0D2.Bits.HE0R24_HE0T24
#define HE0D2_HE0R25_HE0T25             _HE0D2.Bits.HE0R25_HE0T25
#define HE0D2_HE0R26_HE0T26             _HE0D2.Bits.HE0R26_HE0T26
#define HE0D2_HE0R27_HE0T27             _HE0D2.Bits.HE0R27_HE0T27

#define HE0D2_HE0R20_HE0T20_MASK        1
#define HE0D2_HE0R21_HE0T21_MASK        2
#define HE0D2_HE0R22_HE0T22_MASK        4
#define HE0D2_HE0R23_HE0T23_MASK        8
#define HE0D2_HE0R24_HE0T24_MASK        16
#define HE0D2_HE0R25_HE0T25_MASK        32
#define HE0D2_HE0R26_HE0T26_MASK        64
#define HE0D2_HE0R27_HE0T27_MASK        128


/*** HE0D3 - USB HUB Endpoint 0 Data Register 3; 0x00000033 ***/
typedef union {
  byte Byte;
  struct {
    byte HE0R30_HE0T30 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 3 Bit 0, HUB Endpoint 0 Transmit Data Buffer 3 Bit 0 */
    byte HE0R31_HE0T31 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 3 Bit 1, HUB Endpoint 0 Transmit Data Buffer 3 Bit 1 */
    byte HE0R32_HE0T32 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 3 Bit 2, HUB Endpoint 0 Transmit Data Buffer 3 Bit 2 */
    byte HE0R33_HE0T33 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 3 Bit 3, HUB Endpoint 0 Transmit Data Buffer 3 Bit 3 */
    byte HE0R34_HE0T34 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 3 Bit 4, HUB Endpoint 0 Transmit Data Buffer 3 Bit 4 */
    byte HE0R35_HE0T35 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 3 Bit 5, HUB Endpoint 0 Transmit Data Buffer 3 Bit 5 */
    byte HE0R36_HE0T36 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 3 Bit 6, HUB Endpoint 0 Transmit Data Buffer 3 Bit 6 */
    byte HE0R37_HE0T37 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 3 Bit 7, HUB Endpoint 0 Transmit Data Buffer 3 Bit 7 */
  } Bits;
} HE0D3STR;
extern volatile HE0D3STR _HE0D3;
#define HE0D3                           _HE0D3.Byte
#define HE0D3_HE0R30_HE0T30             _HE0D3.Bits.HE0R30_HE0T30
#define HE0D3_HE0R31_HE0T31             _HE0D3.Bits.HE0R31_HE0T31
#define HE0D3_HE0R32_HE0T32             _HE0D3.Bits.HE0R32_HE0T32
#define HE0D3_HE0R33_HE0T33             _HE0D3.Bits.HE0R33_HE0T33
#define HE0D3_HE0R34_HE0T34             _HE0D3.Bits.HE0R34_HE0T34
#define HE0D3_HE0R35_HE0T35             _HE0D3.Bits.HE0R35_HE0T35
#define HE0D3_HE0R36_HE0T36             _HE0D3.Bits.HE0R36_HE0T36
#define HE0D3_HE0R37_HE0T37             _HE0D3.Bits.HE0R37_HE0T37

#define HE0D3_HE0R30_HE0T30_MASK        1
#define HE0D3_HE0R31_HE0T31_MASK        2
#define HE0D3_HE0R32_HE0T32_MASK        4
#define HE0D3_HE0R33_HE0T33_MASK        8
#define HE0D3_HE0R34_HE0T34_MASK        16
#define HE0D3_HE0R35_HE0T35_MASK        32
#define HE0D3_HE0R36_HE0T36_MASK        64
#define HE0D3_HE0R37_HE0T37_MASK        128


/*** HE0D4 - USB HUB Endpoint 0 Data Register 4; 0x00000034 ***/
typedef union {
  byte Byte;
  struct {
    byte HE0R40_HE0T40 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 4 Bit 0, HUB Endpoint 0 Transmit Data Buffer 4 Bit 0 */
    byte HE0R41_HE0T41 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 4 Bit 1, HUB Endpoint 0 Transmit Data Buffer 4 Bit 1 */
    byte HE0R42_HE0T42 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 4 Bit 2, HUB Endpoint 0 Transmit Data Buffer 4 Bit 2 */
    byte HE0R43_HE0T43 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 4 Bit 3, HUB Endpoint 0 Transmit Data Buffer 4 Bit 3 */
    byte HE0R44_HE0T44 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 4 Bit 4, HUB Endpoint 0 Transmit Data Buffer 4 Bit 4 */
    byte HE0R45_HE0T45 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 4 Bit 5, HUB Endpoint 0 Transmit Data Buffer 4 Bit 5 */
    byte HE0R46_HE0T46 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 4 Bit 6, HUB Endpoint 0 Transmit Data Buffer 4 Bit 6 */
    byte HE0R47_HE0T47 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 4 Bit 7, HUB Endpoint 0 Transmit Data Buffer 4 Bit 7 */
  } Bits;
} HE0D4STR;
extern volatile HE0D4STR _HE0D4;
#define HE0D4                           _HE0D4.Byte
#define HE0D4_HE0R40_HE0T40             _HE0D4.Bits.HE0R40_HE0T40
#define HE0D4_HE0R41_HE0T41             _HE0D4.Bits.HE0R41_HE0T41
#define HE0D4_HE0R42_HE0T42             _HE0D4.Bits.HE0R42_HE0T42
#define HE0D4_HE0R43_HE0T43             _HE0D4.Bits.HE0R43_HE0T43
#define HE0D4_HE0R44_HE0T44             _HE0D4.Bits.HE0R44_HE0T44
#define HE0D4_HE0R45_HE0T45             _HE0D4.Bits.HE0R45_HE0T45
#define HE0D4_HE0R46_HE0T46             _HE0D4.Bits.HE0R46_HE0T46
#define HE0D4_HE0R47_HE0T47             _HE0D4.Bits.HE0R47_HE0T47

#define HE0D4_HE0R40_HE0T40_MASK        1
#define HE0D4_HE0R41_HE0T41_MASK        2
#define HE0D4_HE0R42_HE0T42_MASK        4
#define HE0D4_HE0R43_HE0T43_MASK        8
#define HE0D4_HE0R44_HE0T44_MASK        16
#define HE0D4_HE0R45_HE0T45_MASK        32
#define HE0D4_HE0R46_HE0T46_MASK        64
#define HE0D4_HE0R47_HE0T47_MASK        128


/*** HE0D5 - USB HUB Endpoint 0 Data Register 5; 0x00000035 ***/
typedef union {
  byte Byte;
  struct {
    byte HE0R50_HE0T50 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 5 Bit 0, HUB Endpoint 0 Transmit Data Buffer 5 Bit 0 */
    byte HE0R51_HE0T51 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 5 Bit 1, HUB Endpoint 0 Transmit Data Buffer 5 Bit 1 */
    byte HE0R52_HE0T52 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 5 Bit 2, HUB Endpoint 0 Transmit Data Buffer 5 Bit 2 */
    byte HE0R53_HE0T53 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 5 Bit 3, HUB Endpoint 0 Transmit Data Buffer 5 Bit 3 */
    byte HE0R54_HE0T54 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 5 Bit 4, HUB Endpoint 0 Transmit Data Buffer 5 Bit 4 */
    byte HE0R55_HE0T55 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 5 Bit 5, HUB Endpoint 0 Transmit Data Buffer 5 Bit 5 */
    byte HE0R56_HE0T56 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 5 Bit 6, HUB Endpoint 0 Transmit Data Buffer 5 Bit 6 */
    byte HE0R57_HE0T57 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 5 Bit 7, HUB Endpoint 0 Transmit Data Buffer 5 Bit 7 */
  } Bits;
} HE0D5STR;
extern volatile HE0D5STR _HE0D5;
#define HE0D5                           _HE0D5.Byte
#define HE0D5_HE0R50_HE0T50             _HE0D5.Bits.HE0R50_HE0T50
#define HE0D5_HE0R51_HE0T51             _HE0D5.Bits.HE0R51_HE0T51
#define HE0D5_HE0R52_HE0T52             _HE0D5.Bits.HE0R52_HE0T52
#define HE0D5_HE0R53_HE0T53             _HE0D5.Bits.HE0R53_HE0T53
#define HE0D5_HE0R54_HE0T54             _HE0D5.Bits.HE0R54_HE0T54
#define HE0D5_HE0R55_HE0T55             _HE0D5.Bits.HE0R55_HE0T55
#define HE0D5_HE0R56_HE0T56             _HE0D5.Bits.HE0R56_HE0T56
#define HE0D5_HE0R57_HE0T57             _HE0D5.Bits.HE0R57_HE0T57

#define HE0D5_HE0R50_HE0T50_MASK        1
#define HE0D5_HE0R51_HE0T51_MASK        2
#define HE0D5_HE0R52_HE0T52_MASK        4
#define HE0D5_HE0R53_HE0T53_MASK        8
#define HE0D5_HE0R54_HE0T54_MASK        16
#define HE0D5_HE0R55_HE0T55_MASK        32
#define HE0D5_HE0R56_HE0T56_MASK        64
#define HE0D5_HE0R57_HE0T57_MASK        128


/*** HE0D6 - USB HUB Endpoint 0 Data Register 6; 0x00000036 ***/
typedef union {
  byte Byte;
  struct {
    byte HE0R60_HE0T60 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 6 Bit 0, HUB Endpoint 0 Transmit Data Buffer 6 Bit 0 */
    byte HE0R61_HE0T61 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 6 Bit 1, HUB Endpoint 0 Transmit Data Buffer 6 Bit 1 */
    byte HE0R62_HE0T62 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 6 Bit 2, HUB Endpoint 0 Transmit Data Buffer 6 Bit 2 */
    byte HE0R63_HE0T63 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 6 Bit 3, HUB Endpoint 0 Transmit Data Buffer 6 Bit 3 */
    byte HE0R64_HE0T64 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 6 Bit 4, HUB Endpoint 0 Transmit Data Buffer 6 Bit 4 */
    byte HE0R65_HE0T65 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 6 Bit 5, HUB Endpoint 0 Transmit Data Buffer 6 Bit 5 */
    byte HE0R66_HE0T66 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 6 Bit 6, HUB Endpoint 0 Transmit Data Buffer 6 Bit 6 */
    byte HE0R67_HE0T67 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 6 Bit 7, HUB Endpoint 0 Transmit Data Buffer 6 Bit 7 */
  } Bits;
} HE0D6STR;
extern volatile HE0D6STR _HE0D6;
#define HE0D6                           _HE0D6.Byte
#define HE0D6_HE0R60_HE0T60             _HE0D6.Bits.HE0R60_HE0T60
#define HE0D6_HE0R61_HE0T61             _HE0D6.Bits.HE0R61_HE0T61
#define HE0D6_HE0R62_HE0T62             _HE0D6.Bits.HE0R62_HE0T62
#define HE0D6_HE0R63_HE0T63             _HE0D6.Bits.HE0R63_HE0T63
#define HE0D6_HE0R64_HE0T64             _HE0D6.Bits.HE0R64_HE0T64
#define HE0D6_HE0R65_HE0T65             _HE0D6.Bits.HE0R65_HE0T65
#define HE0D6_HE0R66_HE0T66             _HE0D6.Bits.HE0R66_HE0T66
#define HE0D6_HE0R67_HE0T67             _HE0D6.Bits.HE0R67_HE0T67

#define HE0D6_HE0R60_HE0T60_MASK        1
#define HE0D6_HE0R61_HE0T61_MASK        2
#define HE0D6_HE0R62_HE0T62_MASK        4
#define HE0D6_HE0R63_HE0T63_MASK        8
#define HE0D6_HE0R64_HE0T64_MASK        16
#define HE0D6_HE0R65_HE0T65_MASK        32
#define HE0D6_HE0R66_HE0T66_MASK        64
#define HE0D6_HE0R67_HE0T67_MASK        128


/*** HE0D7 - USB HUB Endpoint 0 Data Register 7; 0x00000037 ***/
typedef union {
  byte Byte;
  struct {
    byte HE0R70_HE0T70 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 7 Bit 0, HUB Endpoint 0 Transmit Data Buffer 7 Bit 0 */
    byte HE0R71_HE0T71 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 7 Bit 1, HUB Endpoint 0 Transmit Data Buffer 7 Bit 1 */
    byte HE0R72_HE0T72 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 7 Bit 2, HUB Endpoint 0 Transmit Data Buffer 7 Bit 2 */
    byte HE0R73_HE0T73 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 7 Bit 3, HUB Endpoint 0 Transmit Data Buffer 7 Bit 3 */
    byte HE0R74_HE0T74 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 7 Bit 4, HUB Endpoint 0 Transmit Data Buffer 7 Bit 4 */
    byte HE0R75_HE0T75 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 7 Bit 5, HUB Endpoint 0 Transmit Data Buffer 7 Bit 5 */
    byte HE0R76_HE0T76 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 7 Bit 6, HUB Endpoint 0 Transmit Data Buffer 7 Bit 6 */
    byte HE0R77_HE0T77 :1;                                     /* HUB Endpoint 0 Receive Data Buffer 7 Bit 7, HUB Endpoint 0 Transmit Data Buffer 7 Bit 7 */
  } Bits;
} HE0D7STR;
extern volatile HE0D7STR _HE0D7;
#define HE0D7                           _HE0D7.Byte
#define HE0D7_HE0R70_HE0T70             _HE0D7.Bits.HE0R70_HE0T70
#define HE0D7_HE0R71_HE0T71             _HE0D7.Bits.HE0R71_HE0T71
#define HE0D7_HE0R72_HE0T72             _HE0D7.Bits.HE0R72_HE0T72
#define HE0D7_HE0R73_HE0T73             _HE0D7.Bits.HE0R73_HE0T73
#define HE0D7_HE0R74_HE0T74             _HE0D7.Bits.HE0R74_HE0T74
#define HE0D7_HE0R75_HE0T75             _HE0D7.Bits.HE0R75_HE0T75
#define HE0D7_HE0R76_HE0T76             _HE0D7.Bits.HE0R76_HE0T76
#define HE0D7_HE0R77_HE0T77             _HE0D7.Bits.HE0R77_HE0T77

#define HE0D7_HE0R70_HE0T70_MASK        1
#define HE0D7_HE0R71_HE0T71_MASK        2
#define HE0D7_HE0R72_HE0T72_MASK        4
#define HE0D7_HE0R73_HE0T73_MASK        8
#define HE0D7_HE0R74_HE0T74_MASK        16
#define HE0D7_HE0R75_HE0T75_MASK        32
#define HE0D7_HE0R76_HE0T76_MASK        64
#define HE0D7_HE0R77_HE0T77_MASK        128


/*** PCTL - PLL Control Register; 0x00000038 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BCS         :1;                                       /* Base Clock Select Bit */
    byte PLLON       :1;                                       /* PLL On Bit */
    byte PLLF        :1;                                       /* PLL Flag Bit */
    byte PLLIE       :1;                                       /* PLL Interrupt Enable Bit */
  } Bits;
} PCTLSTR;
extern volatile PCTLSTR _PCTL;
#define PCTL                            _PCTL.Byte
#define PCTL_BCS                        _PCTL.Bits.BCS
#define PCTL_PLLON                      _PCTL.Bits.PLLON
#define PCTL_PLLF                       _PCTL.Bits.PLLF
#define PCTL_PLLIE                      _PCTL.Bits.PLLIE

#define PCTL_BCS_MASK                   16
#define PCTL_PLLON_MASK                 32
#define PCTL_PLLF_MASK                  64
#define PCTL_PLLIE_MASK                 128


/*** PBWC - PLL Bandwidth Control Register; 0x00000039 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte XLD         :1;                                       /* Crystal Loss Detect Bit */
    byte ACQ         :1;                                       /* Acquisition Mode Bit */
    byte LOCK        :1;                                       /* Lock Indicator Bit */
    byte AUTO        :1;                                       /* Automatic Bandwidth Control Bit */
  } Bits;
} PBWCSTR;
extern volatile PBWCSTR _PBWC;
#define PBWC                            _PBWC.Byte
#define PBWC_XLD                        _PBWC.Bits.XLD
#define PBWC_ACQ                        _PBWC.Bits.ACQ
#define PBWC_LOCK                       _PBWC.Bits.LOCK
#define PBWC_AUTO                       _PBWC.Bits.AUTO

#define PBWC_XLD_MASK                   16
#define PBWC_ACQ_MASK                   32
#define PBWC_LOCK_MASK                  64
#define PBWC_AUTO_MASK                  128


/*** PPG - PLL Programming Register; 0x0000003A ***/
typedef union {
  byte Byte;
  struct {
    byte VRS4        :1;                                       /* VCO Range Select Bit 4 */
    byte VRS5        :1;                                       /* VCO Range Select Bit 5 */
    byte VRS6        :1;                                       /* VCO Range Select Bit 6 */
    byte VRS7        :1;                                       /* VCO Range Select Bit 7 */
    byte MUL4        :1;                                       /* Multiplier Select Bit 4 */
    byte MUL5        :1;                                       /* Multiplier Select Bit 5 */
    byte MUL6        :1;                                       /* Multiplier Select Bit 6 */
    byte MUL7        :1;                                       /* Multiplier Select Bit 7 */
  } Bits;
  struct {
    byte grpVRS_4 :4;
    byte grpMUL_4 :4;
  } MergedBits;
} PPGSTR;
extern volatile PPGSTR _PPG;
#define PPG                             _PPG.Byte
#define PPG_VRS4                        _PPG.Bits.VRS4
#define PPG_VRS5                        _PPG.Bits.VRS5
#define PPG_VRS6                        _PPG.Bits.VRS6
#define PPG_VRS7                        _PPG.Bits.VRS7
#define PPG_MUL4                        _PPG.Bits.MUL4
#define PPG_MUL5                        _PPG.Bits.MUL5
#define PPG_MUL6                        _PPG.Bits.MUL6
#define PPG_MUL7                        _PPG.Bits.MUL7
#define PPG_VRS_4                       _PPG.MergedBits.grpVRS_4
#define PPG_MUL_4                       _PPG.MergedBits.grpMUL_4
#define PPG_VRS                         PPG_VRS_4
#define PPG_MUL                         PPG_MUL_4

#define PPG_VRS4_MASK                   1
#define PPG_VRS5_MASK                   2
#define PPG_VRS6_MASK                   4
#define PPG_VRS7_MASK                   8
#define PPG_MUL4_MASK                   16
#define PPG_MUL5_MASK                   32
#define PPG_MUL6_MASK                   64
#define PPG_MUL7_MASK                   128
#define PPG_VRS_4_MASK                  15
#define PPG_VRS_4_BITNUM                0
#define PPG_MUL_4_MASK                  240
#define PPG_MUL_4_BITNUM                4


/*** ADSCR - ADC Status and Control Register; 0x0000003B ***/
typedef union {
  byte Byte;
  struct {
    byte ADCH0       :1;                                       /* ADC Channel Select Bit 0 */
    byte ADCH1       :1;                                       /* ADC Channel Select Bit 1 */
    byte ADCH2       :1;                                       /* ADC Channel Select Bit 2 */
    byte ADCH3       :1;                                       /* ADC Channel Select Bit 3 */
    byte ADCH4       :1;                                       /* ADC Channel Select Bit 4 */
    byte ADCO        :1;                                       /* ADC Continuous Conversion Bit */
    byte AIEN        :1;                                       /* ADC Interrupt Enable Bit */
    byte COCO        :1;                                       /* Conversions Complete Bit */
  } Bits;
  struct {
    byte grpADCH :5;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} ADSCRSTR;
extern volatile ADSCRSTR _ADSCR;
#define ADSCR                           _ADSCR.Byte
#define ADSCR_ADCH0                     _ADSCR.Bits.ADCH0
#define ADSCR_ADCH1                     _ADSCR.Bits.ADCH1
#define ADSCR_ADCH2                     _ADSCR.Bits.ADCH2
#define ADSCR_ADCH3                     _ADSCR.Bits.ADCH3
#define ADSCR_ADCH4                     _ADSCR.Bits.ADCH4
#define ADSCR_ADCO                      _ADSCR.Bits.ADCO
#define ADSCR_AIEN                      _ADSCR.Bits.AIEN
#define ADSCR_COCO                      _ADSCR.Bits.COCO
#define ADSCR_ADCH                      _ADSCR.MergedBits.grpADCH

#define ADSCR_ADCH0_MASK                1
#define ADSCR_ADCH1_MASK                2
#define ADSCR_ADCH2_MASK                4
#define ADSCR_ADCH3_MASK                8
#define ADSCR_ADCH4_MASK                16
#define ADSCR_ADCO_MASK                 32
#define ADSCR_AIEN_MASK                 64
#define ADSCR_COCO_MASK                 128
#define ADSCR_ADCH_MASK                 31
#define ADSCR_ADCH_BITNUM               0


/*** ADR - ADC Data Register; 0x0000003C ***/
typedef union {
  byte Byte;
  struct {
    byte AD0         :1;                                       /* ADC Data Bit 0 */
    byte AD1         :1;                                       /* ADC Data Bit 1 */
    byte AD2         :1;                                       /* ADC Data Bit 2 */
    byte AD3         :1;                                       /* ADC Data Bit 3 */
    byte AD4         :1;                                       /* ADC Data Bit 4 */
    byte AD5         :1;                                       /* ADC Data Bit 5 */
    byte AD6         :1;                                       /* ADC Data Bit 6 */
    byte AD7         :1;                                       /* ADC Data Bit 7 */
  } Bits;
} ADRSTR;
extern volatile ADRSTR _ADR;
#define ADR                             _ADR.Byte
#define ADR_AD0                         _ADR.Bits.AD0
#define ADR_AD1                         _ADR.Bits.AD1
#define ADR_AD2                         _ADR.Bits.AD2
#define ADR_AD3                         _ADR.Bits.AD3
#define ADR_AD4                         _ADR.Bits.AD4
#define ADR_AD5                         _ADR.Bits.AD5
#define ADR_AD6                         _ADR.Bits.AD6
#define ADR_AD7                         _ADR.Bits.AD7

#define ADR_AD0_MASK                    1
#define ADR_AD1_MASK                    2
#define ADR_AD2_MASK                    4
#define ADR_AD3_MASK                    8
#define ADR_AD4_MASK                    16
#define ADR_AD5_MASK                    32
#define ADR_AD6_MASK                    64
#define ADR_AD7_MASK                    128


/*** ADICLK - ADC Input Clock Register; 0x0000003D ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte ADIV0       :1;                                       /* ADC Clock Prescaler Bit 0 */
    byte ADIV1       :1;                                       /* ADC Clock Prescaler Bit 1 */
    byte ADIV2       :1;                                       /* ADC Clock Prescaler Bit 2 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpADIV :3;
  } MergedBits;
} ADICLKSTR;
extern volatile ADICLKSTR _ADICLK;
#define ADICLK                          _ADICLK.Byte
#define ADICLK_ADIV0                    _ADICLK.Bits.ADIV0
#define ADICLK_ADIV1                    _ADICLK.Bits.ADIV1
#define ADICLK_ADIV2                    _ADICLK.Bits.ADIV2
#define ADICLK_ADIV                     _ADICLK.MergedBits.grpADIV

#define ADICLK_ADIV0_MASK               32
#define ADICLK_ADIV1_MASK               64
#define ADICLK_ADIV2_MASK               128
#define ADICLK_ADIV_MASK                224
#define ADICLK_ADIV_BITNUM              5


/*** HVOCR - H & V Sync Output Control Register; 0x0000003F ***/
typedef union {
  byte Byte;
  struct {
    byte HVOCR0      :1;                                       /* Free Running Video Mode Select Bit 0 */
    byte HVOCR1      :1;                                       /* Free Running Video Mode Select Bit 1 */
    byte             :1; 
    byte DCLKPH0     :1;                                       /* DCLK Output Phase Adjustment Bit 0 */
    byte DCLKPH1     :1;                                       /* DCLK Output Phase Adjustment Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpHVOCR :2;
    byte         :1;
    byte grpDCLKPH :2;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} HVOCRSTR;
extern volatile HVOCRSTR _HVOCR;
#define HVOCR                           _HVOCR.Byte
#define HVOCR_HVOCR0                    _HVOCR.Bits.HVOCR0
#define HVOCR_HVOCR1                    _HVOCR.Bits.HVOCR1
#define HVOCR_DCLKPH0                   _HVOCR.Bits.DCLKPH0
#define HVOCR_DCLKPH1                   _HVOCR.Bits.DCLKPH1
#define HVOCR_HVOCR                     _HVOCR.MergedBits.grpHVOCR
#define HVOCR_DCLKPH                    _HVOCR.MergedBits.grpDCLKPH

#define HVOCR_HVOCR0_MASK               1
#define HVOCR_HVOCR1_MASK               2
#define HVOCR_DCLKPH0_MASK              8
#define HVOCR_DCLKPH1_MASK              16
#define HVOCR_HVOCR_MASK                3
#define HVOCR_HVOCR_BITNUM              0
#define HVOCR_DCLKPH_MASK               24
#define HVOCR_DCLKPH_BITNUM             3


/*** SPCSR - Sync Processor Control and Status Register; 0x00000040 ***/
typedef union {
  byte Byte;
  struct {
    byte HPOL        :1;                                       /* Hsync Input Polarity */
    byte VPOL        :1;                                       /* Vsync Input Polarity */
    byte HINVO       :1;                                       /* HOUT Signal Polarity */
    byte VINVO       :1;                                       /* VOUT Signal Polarity */
    byte COMP        :1;                                       /* Composite Sync Input Enable */
    byte VSIF        :1;                                       /* VSync Interrupt Flag */
    byte VEDGE       :1;                                       /* VSync Interrupt Edge Select */
    byte VSIE        :1;                                       /* VSync Interrupt Enable */
  } Bits;
} SPCSRSTR;
extern volatile SPCSRSTR _SPCSR;
#define SPCSR                           _SPCSR.Byte
#define SPCSR_HPOL                      _SPCSR.Bits.HPOL
#define SPCSR_VPOL                      _SPCSR.Bits.VPOL
#define SPCSR_HINVO                     _SPCSR.Bits.HINVO
#define SPCSR_VINVO                     _SPCSR.Bits.VINVO
#define SPCSR_COMP                      _SPCSR.Bits.COMP
#define SPCSR_VSIF                      _SPCSR.Bits.VSIF
#define SPCSR_VEDGE                     _SPCSR.Bits.VEDGE
#define SPCSR_VSIE                      _SPCSR.Bits.VSIE

#define SPCSR_HPOL_MASK                 1
#define SPCSR_VPOL_MASK                 2
#define SPCSR_HINVO_MASK                4
#define SPCSR_VINVO_MASK                8
#define SPCSR_COMP_MASK                 16
#define SPCSR_VSIF_MASK                 32
#define SPCSR_VEDGE_MASK                64
#define SPCSR_VSIE_MASK                 128


/*** VFHR - Vertical Frequency Register High; 0x00000041 ***/
typedef union {
  byte Byte;
  struct {
    byte VF8         :1;                                       /* Vertical Frame Frequency Bit 8 */
    byte VF9         :1;                                       /* Vertical Frame Frequency Bit 9 */
    byte VF10        :1;                                       /* Vertical Frame Frequency Bit 10 */
    byte VF11        :1;                                       /* Vertical Frame Frequency Bit 11 */
    byte VF12        :1;                                       /* Vertical Frame Frequency Bit 12 */
    byte CPW0        :1;                                       /* Clamp Pulse Width Bit 0 */
    byte CPW1        :1;                                       /* Clamp Pulse Width Bit 1 */
    byte VOF         :1;                                       /* Vertical Frequency Counter Overflow */
  } Bits;
  struct {
    byte grpVF_8 :5;
    byte grpCPW  :2;
    byte         :1;
  } MergedBits;
} VFHRSTR;
extern volatile VFHRSTR _VFHR;
#define VFHR                            _VFHR.Byte
#define VFHR_VF8                        _VFHR.Bits.VF8
#define VFHR_VF9                        _VFHR.Bits.VF9
#define VFHR_VF10                       _VFHR.Bits.VF10
#define VFHR_VF11                       _VFHR.Bits.VF11
#define VFHR_VF12                       _VFHR.Bits.VF12
#define VFHR_CPW0                       _VFHR.Bits.CPW0
#define VFHR_CPW1                       _VFHR.Bits.CPW1
#define VFHR_VOF                        _VFHR.Bits.VOF
#define VFHR_VF_8                       _VFHR.MergedBits.grpVF_8
#define VFHR_CPW                        _VFHR.MergedBits.grpCPW
#define VFHR_VF                         VFHR_VF_8

#define VFHR_VF8_MASK                   1
#define VFHR_VF9_MASK                   2
#define VFHR_VF10_MASK                  4
#define VFHR_VF11_MASK                  8
#define VFHR_VF12_MASK                  16
#define VFHR_CPW0_MASK                  32
#define VFHR_CPW1_MASK                  64
#define VFHR_VOF_MASK                   128
#define VFHR_VF_8_MASK                  31
#define VFHR_VF_8_BITNUM                0
#define VFHR_CPW_MASK                   96
#define VFHR_CPW_BITNUM                 5


/*** VFLR - Vertical Frequency Register Low; 0x00000042 ***/
typedef union {
  byte Byte;
  struct {
    byte VF0         :1;                                       /* Vertical Frame Frequency Bit 0 */
    byte VF1         :1;                                       /* Vertical Frame Frequency Bit 1 */
    byte VF2         :1;                                       /* Vertical Frame Frequency Bit 2 */
    byte VF3         :1;                                       /* Vertical Frame Frequency Bit 3 */
    byte VF4         :1;                                       /* Vertical Frame Frequency Bit 4 */
    byte VF5         :1;                                       /* Vertical Frame Frequency Bit 5 */
    byte VF6         :1;                                       /* Vertical Frame Frequency Bit 6 */
    byte VF7         :1;                                       /* Vertical Frame Frequency Bit 7 */
  } Bits;
} VFLRSTR;
extern volatile VFLRSTR _VFLR;
#define VFLR                            _VFLR.Byte
#define VFLR_VF0                        _VFLR.Bits.VF0
#define VFLR_VF1                        _VFLR.Bits.VF1
#define VFLR_VF2                        _VFLR.Bits.VF2
#define VFLR_VF3                        _VFLR.Bits.VF3
#define VFLR_VF4                        _VFLR.Bits.VF4
#define VFLR_VF5                        _VFLR.Bits.VF5
#define VFLR_VF6                        _VFLR.Bits.VF6
#define VFLR_VF7                        _VFLR.Bits.VF7

#define VFLR_VF0_MASK                   1
#define VFLR_VF1_MASK                   2
#define VFLR_VF2_MASK                   4
#define VFLR_VF3_MASK                   8
#define VFLR_VF4_MASK                   16
#define VFLR_VF5_MASK                   32
#define VFLR_VF6_MASK                   64
#define VFLR_VF7_MASK                   128


/*** HFHR - Hsync Frequency Register High; 0x00000043 ***/
typedef union {
  byte Byte;
  struct {
    byte HFH0        :1;                                       /* Horizontal Line Frequency Bit 0 */
    byte HFH1        :1;                                       /* Horizontal Line Frequency Bit 1 */
    byte HFH2        :1;                                       /* Horizontal Line Frequency Bit 2 */
    byte HFH3        :1;                                       /* Horizontal Line Frequency Bit 3 */
    byte HFH4        :1;                                       /* Horizontal Line Frequency Bit 4 */
    byte HFH5        :1;                                       /* Horizontal Line Frequency Bit 5 */
    byte HFH6        :1;                                       /* Horizontal Line Frequency Bit 6 */
    byte HFH7        :1;                                       /* Horizontal Line Frequency Bit 7 */
  } Bits;
} HFHRSTR;
extern volatile HFHRSTR _HFHR;
#define HFHR                            _HFHR.Byte
#define HFHR_HFH0                       _HFHR.Bits.HFH0
#define HFHR_HFH1                       _HFHR.Bits.HFH1
#define HFHR_HFH2                       _HFHR.Bits.HFH2
#define HFHR_HFH3                       _HFHR.Bits.HFH3
#define HFHR_HFH4                       _HFHR.Bits.HFH4
#define HFHR_HFH5                       _HFHR.Bits.HFH5
#define HFHR_HFH6                       _HFHR.Bits.HFH6
#define HFHR_HFH7                       _HFHR.Bits.HFH7

#define HFHR_HFH0_MASK                  1
#define HFHR_HFH1_MASK                  2
#define HFHR_HFH2_MASK                  4
#define HFHR_HFH3_MASK                  8
#define HFHR_HFH4_MASK                  16
#define HFHR_HFH5_MASK                  32
#define HFHR_HFH6_MASK                  64
#define HFHR_HFH7_MASK                  128


/*** HFLR - Hsync Frequency Register Low; 0x00000044 ***/
typedef union {
  byte Byte;
  struct {
    byte HFL0        :1;                                       /* Horizontal Line Frequency Bit 0 */
    byte HFL1        :1;                                       /* Horizontal Line Frequency Bit 1 */
    byte HFL2        :1;                                       /* Horizontal Line Frequency Bit 2 */
    byte HFL3        :1;                                       /* Horizontal Line Frequency Bit 3 */
    byte HFL4        :1;                                       /* Horizontal Line Frequency Bit 4 */
    byte             :1; 
    byte             :1; 
    byte HOVER       :1;                                       /* Hsync Frequency Counter Overflow */
  } Bits;
  struct {
    byte grpHFL  :5;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} HFLRSTR;
extern volatile HFLRSTR _HFLR;
#define HFLR                            _HFLR.Byte
#define HFLR_HFL0                       _HFLR.Bits.HFL0
#define HFLR_HFL1                       _HFLR.Bits.HFL1
#define HFLR_HFL2                       _HFLR.Bits.HFL2
#define HFLR_HFL3                       _HFLR.Bits.HFL3
#define HFLR_HFL4                       _HFLR.Bits.HFL4
#define HFLR_HOVER                      _HFLR.Bits.HOVER
#define HFLR_HFL                        _HFLR.MergedBits.grpHFL

#define HFLR_HFL0_MASK                  1
#define HFLR_HFL1_MASK                  2
#define HFLR_HFL2_MASK                  4
#define HFLR_HFL3_MASK                  8
#define HFLR_HFL4_MASK                  16
#define HFLR_HOVER_MASK                 128
#define HFLR_HFL_MASK                   31
#define HFLR_HFL_BITNUM                 0


/*** SPIOCR - Sync Processor Input/Output Control Register; 0x00000045 ***/
typedef union {
  byte Byte;
  struct {
    byte SOUT        :1;                                       /* Sync Output Enable */
    byte BPOR        :1;                                       /* Back Porch */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte COINV       :1;                                       /* Clamp Output Invert */
    byte HSYNCS      :1;                                       /* HSYNC Input State */
    byte VSYNCS      :1;                                       /* VSYNC Input State */
  } Bits;
} SPIOCRSTR;
extern volatile SPIOCRSTR _SPIOCR;
#define SPIOCR                          _SPIOCR.Byte
#define SPIOCR_SOUT                     _SPIOCR.Bits.SOUT
#define SPIOCR_BPOR                     _SPIOCR.Bits.BPOR
#define SPIOCR_COINV                    _SPIOCR.Bits.COINV
#define SPIOCR_HSYNCS                   _SPIOCR.Bits.HSYNCS
#define SPIOCR_VSYNCS                   _SPIOCR.Bits.VSYNCS

#define SPIOCR_SOUT_MASK                1
#define SPIOCR_BPOR_MASK                2
#define SPIOCR_COINV_MASK               32
#define SPIOCR_HSYNCS_MASK              64
#define SPIOCR_VSYNCS_MASK              128


/*** SPCR1 - Sync Processor Control Register 1; 0x00000046 ***/
typedef union {
  byte Byte;
  struct {
    byte FSHF        :1;                                       /* Fast Horizontal Frequency Count */
    byte ATPOL       :1;                                       /* Auto Polarity */
    byte             :1; 
    byte             :1; 
    byte HPS0        :1;                                       /* HSYNC Input Detection Pulse Width Bit 0 */
    byte HPS1        :1;                                       /* HSYNC Input Detection Pulse Width Bit 1 */
    byte LVSIF       :1;                                       /* Low VSync Interrupt Flag */
    byte LVSIE       :1;                                       /* Low VSync Interrupt Enable */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpHPS  :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} SPCR1STR;
extern volatile SPCR1STR _SPCR1;
#define SPCR1                           _SPCR1.Byte
#define SPCR1_FSHF                      _SPCR1.Bits.FSHF
#define SPCR1_ATPOL                     _SPCR1.Bits.ATPOL
#define SPCR1_HPS0                      _SPCR1.Bits.HPS0
#define SPCR1_HPS1                      _SPCR1.Bits.HPS1
#define SPCR1_LVSIF                     _SPCR1.Bits.LVSIF
#define SPCR1_LVSIE                     _SPCR1.Bits.LVSIE
#define SPCR1_HPS                       _SPCR1.MergedBits.grpHPS

#define SPCR1_FSHF_MASK                 1
#define SPCR1_ATPOL_MASK                2
#define SPCR1_HPS0_MASK                 16
#define SPCR1_HPS1_MASK                 32
#define SPCR1_LVSIF_MASK                64
#define SPCR1_LVSIE_MASK                128
#define SPCR1_HPS_MASK                  48
#define SPCR1_HPS_BITNUM                4


/*** DCR2 - USB Embedded Device Control Register 2; 0x00000047 ***/
typedef union {
  byte Byte;
  struct {
    byte DSTALL1     :1;                                       /* Embedded Device Endpoint 1 Force Stall Bit */
    byte DSTALL2     :1;                                       /* Embedded Device Endpoint 2 Force Stall Bit */
    byte ENABLE1     :1;                                       /* Embedded Device Endpoint 1 Enable */
    byte ENABLE2     :1;                                       /* Embedded Device Endpoint 2 Enable */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDSTALL_1 :2;
    byte grpENABLE_1 :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DCR2STR;
extern volatile DCR2STR _DCR2;
#define DCR2                            _DCR2.Byte
#define DCR2_DSTALL1                    _DCR2.Bits.DSTALL1
#define DCR2_DSTALL2                    _DCR2.Bits.DSTALL2
#define DCR2_ENABLE1                    _DCR2.Bits.ENABLE1
#define DCR2_ENABLE2                    _DCR2.Bits.ENABLE2
#define DCR2_DSTALL_1                   _DCR2.MergedBits.grpDSTALL_1
#define DCR2_ENABLE_1                   _DCR2.MergedBits.grpENABLE_1
#define DCR2_DSTALL                     DCR2_DSTALL_1
#define DCR2_ENABLE                     DCR2_ENABLE_1

#define DCR2_DSTALL1_MASK               1
#define DCR2_DSTALL2_MASK               2
#define DCR2_ENABLE1_MASK               4
#define DCR2_ENABLE2_MASK               8
#define DCR2_DSTALL_1_MASK              3
#define DCR2_DSTALL_1_BITNUM            0
#define DCR2_ENABLE_1_MASK              12
#define DCR2_ENABLE_1_BITNUM            2


/*** DADDR - USB Embedded Device Address Register; 0x00000048 ***/
typedef union {
  byte Byte;
  struct {
    byte DADD0       :1;                                       /* USB Embedded Device Function Address Bit 0 */
    byte DADD1       :1;                                       /* USB Embedded Device Function Address Bit 1 */
    byte DADD2       :1;                                       /* USB Embedded Device Function Address Bit 2 */
    byte DADD3       :1;                                       /* USB Embedded Device Function Address Bit 3 */
    byte DADD4       :1;                                       /* USB Embedded Device Function Address Bit 4 */
    byte DADD5       :1;                                       /* USB Embedded Device Function Address Bit 5 */
    byte DADD6       :1;                                       /* USB Embedded Device Function Address Bit 6 */
    byte DEVEN       :1;                                       /* Enable USB Embedded Device */
  } Bits;
  struct {
    byte grpDADD :7;
    byte         :1;
  } MergedBits;
} DADDRSTR;
extern volatile DADDRSTR _DADDR;
#define DADDR                           _DADDR.Byte
#define DADDR_DADD0                     _DADDR.Bits.DADD0
#define DADDR_DADD1                     _DADDR.Bits.DADD1
#define DADDR_DADD2                     _DADDR.Bits.DADD2
#define DADDR_DADD3                     _DADDR.Bits.DADD3
#define DADDR_DADD4                     _DADDR.Bits.DADD4
#define DADDR_DADD5                     _DADDR.Bits.DADD5
#define DADDR_DADD6                     _DADDR.Bits.DADD6
#define DADDR_DEVEN                     _DADDR.Bits.DEVEN
#define DADDR_DADD                      _DADDR.MergedBits.grpDADD

#define DADDR_DADD0_MASK                1
#define DADDR_DADD1_MASK                2
#define DADDR_DADD2_MASK                4
#define DADDR_DADD3_MASK                8
#define DADDR_DADD4_MASK                16
#define DADDR_DADD5_MASK                32
#define DADDR_DADD6_MASK                64
#define DADDR_DEVEN_MASK                128
#define DADDR_DADD_MASK                 127
#define DADDR_DADD_BITNUM               0


/*** DIR0 - USB Embedded Device Interrupt Register 0; 0x00000049 ***/
typedef union {
  byte Byte;
  struct {
    byte RXD0FR      :1;                                       /* Embedded Device Endpoint 0 Receive Flag Reset */
    byte TXD0FR      :1;                                       /* Embedded Device Endpoint 0 Transmit Flag Reset */
    byte RXD0IE      :1;                                       /* Embedded Device Endpoint Endpoint 0 Receive Interrupt Enable */
    byte TXD0IE      :1;                                       /* Embedded Device Endpoint Endpoint 0 Transmit Interrupt Enable */
    byte             :1; 
    byte             :1; 
    byte RXD0F       :1;                                       /* Embedded Device Endpoint 0 Data Receive Flag */
    byte TXD0F       :1;                                       /* Embedded Device Endpoint 0 Data Transmit Flag */
  } Bits;
} DIR0STR;
extern volatile DIR0STR _DIR0;
#define DIR0                            _DIR0.Byte
#define DIR0_RXD0FR                     _DIR0.Bits.RXD0FR
#define DIR0_TXD0FR                     _DIR0.Bits.TXD0FR
#define DIR0_RXD0IE                     _DIR0.Bits.RXD0IE
#define DIR0_TXD0IE                     _DIR0.Bits.TXD0IE
#define DIR0_RXD0F                      _DIR0.Bits.RXD0F
#define DIR0_TXD0F                      _DIR0.Bits.TXD0F
/* DIR_ARR: Access 2 DIRx registers in an array */
#define DIR_ARR                         ((volatile byte * __far) &DIR0)

#define DIR0_RXD0FR_MASK                1
#define DIR0_TXD0FR_MASK                2
#define DIR0_RXD0IE_MASK                4
#define DIR0_TXD0IE_MASK                8
#define DIR0_RXD0F_MASK                 64
#define DIR0_TXD0F_MASK                 128


/*** DIR1 - USB Embedded Device Interrupt Register 1; 0x0000004A ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte TXD1FR      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Flag Reset */
    byte             :1; 
    byte TXD1IE      :1;                                       /* Embedded Device Endpoint 1/2 Transmit Interrupt Enable */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte TXD1F       :1;                                       /* Embedded Device Endpoint 1/2 Data Transmit Flag */
  } Bits;
} DIR1STR;
extern volatile DIR1STR _DIR1;
#define DIR1                            _DIR1.Byte
#define DIR1_TXD1FR                     _DIR1.Bits.TXD1FR
#define DIR1_TXD1IE                     _DIR1.Bits.TXD1IE
#define DIR1_TXD1F                      _DIR1.Bits.TXD1F

#define DIR1_TXD1FR_MASK                2
#define DIR1_TXD1IE_MASK                8
#define DIR1_TXD1F_MASK                 128


/*** DCR0 - USB Embedded Device Control Register 0; 0x0000004B ***/
typedef union {
  byte Byte;
  struct {
    byte TP0SIZ0     :1;                                       /* Embedded Device Endpoint 0 Transmit Data Packet Size Bit 0 */
    byte TP0SIZ1     :1;                                       /* Embedded Device Endpoint 0 Transmit Data Packet Size Bit 1 */
    byte TP0SIZ2     :1;                                       /* Embedded Device Endpoint 0 Transmit Data Packet Size Bit 2 */
    byte TP0SIZ3     :1;                                       /* Embedded Device Endpoint 0 Transmit Data Packet Size Bit 3 */
    byte RX0E        :1;                                       /* Embedded Device Endpoint 0 Receive Enable */
    byte TX0E        :1;                                       /* Embedded Device Endpoint 0 Transmit Enable */
    byte DSTALL0     :1;                                       /* Embedded Device Endpoint 0 Force Stall Bit */
    byte T0SEQ       :1;                                       /* Embedded Device Endpoint 0 Transmit Sequence Bit */
  } Bits;
  struct {
    byte grpTP0SIZ :4;
    byte         :1;
    byte         :1;
    byte grpDSTALL :1;
    byte         :1;
  } MergedBits;
} DCR0STR;
extern volatile DCR0STR _DCR0;
#define DCR0                            _DCR0.Byte
#define DCR0_TP0SIZ0                    _DCR0.Bits.TP0SIZ0
#define DCR0_TP0SIZ1                    _DCR0.Bits.TP0SIZ1
#define DCR0_TP0SIZ2                    _DCR0.Bits.TP0SIZ2
#define DCR0_TP0SIZ3                    _DCR0.Bits.TP0SIZ3
#define DCR0_RX0E                       _DCR0.Bits.RX0E
#define DCR0_TX0E                       _DCR0.Bits.TX0E
#define DCR0_DSTALL0                    _DCR0.Bits.DSTALL0
#define DCR0_T0SEQ                      _DCR0.Bits.T0SEQ
/* DCR_ARR: Access 2 DCRx registers in an array */
#define DCR_ARR                         ((volatile byte * __far) &DCR0)
#define DCR0_TP0SIZ                     _DCR0.MergedBits.grpTP0SIZ

#define DCR0_TP0SIZ0_MASK               1
#define DCR0_TP0SIZ1_MASK               2
#define DCR0_TP0SIZ2_MASK               4
#define DCR0_TP0SIZ3_MASK               8
#define DCR0_RX0E_MASK                  16
#define DCR0_TX0E_MASK                  32
#define DCR0_DSTALL0_MASK               64
#define DCR0_T0SEQ_MASK                 128
#define DCR0_TP0SIZ_MASK                15
#define DCR0_TP0SIZ_BITNUM              0


/*** DCR1 - USB Embedded Device Control Register 1; 0x0000004C ***/
typedef union {
  byte Byte;
  struct {
    byte TP1SIZ0     :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Packet Size Bit 0 */
    byte TP1SIZ1     :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Packet Size Bit 1 */
    byte TP1SIZ2     :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Packet Size Bit 2 */
    byte TP1SIZ3     :1;                                       /* Embedded Device Endpoint 1/2 Transmit Data Packet Size Bit 3 */
    byte             :1; 
    byte TX1E        :1;                                       /* Embedded Device Endpoint 1/2 Transmit Enable */
    byte ENDADD      :1;                                       /* Endpoint Address Select */
    byte T1SEQ       :1;                                       /* Embedded Device Endpoint 1/2 Transmit Sequence Bit */
  } Bits;
  struct {
    byte grpTP1SIZ :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DCR1STR;
extern volatile DCR1STR _DCR1;
#define DCR1                            _DCR1.Byte
#define DCR1_TP1SIZ0                    _DCR1.Bits.TP1SIZ0
#define DCR1_TP1SIZ1                    _DCR1.Bits.TP1SIZ1
#define DCR1_TP1SIZ2                    _DCR1.Bits.TP1SIZ2
#define DCR1_TP1SIZ3                    _DCR1.Bits.TP1SIZ3
#define DCR1_TX1E                       _DCR1.Bits.TX1E
#define DCR1_ENDADD                     _DCR1.Bits.ENDADD
#define DCR1_T1SEQ                      _DCR1.Bits.T1SEQ
#define DCR1_TP1SIZ                     _DCR1.MergedBits.grpTP1SIZ

#define DCR1_TP1SIZ0_MASK               1
#define DCR1_TP1SIZ1_MASK               2
#define DCR1_TP1SIZ2_MASK               4
#define DCR1_TP1SIZ3_MASK               8
#define DCR1_TX1E_MASK                  32
#define DCR1_ENDADD_MASK                64
#define DCR1_T1SEQ_MASK                 128
#define DCR1_TP1SIZ_MASK                15
#define DCR1_TP1SIZ_BITNUM              0


/*** DSR - USB Embedded Device Statsu Register; 0x0000004D ***/
typedef union {
  byte Byte;
  struct {
    byte RP0SIZ0     :1;                                       /* Embedded Device Endpoint 0 Receive Data Packet Size Bit 0 */
    byte RP0SIZ1     :1;                                       /* Embedded Device Endpoint 0 Receive Data Packet Size Bit 1 */
    byte RP0SIZ2     :1;                                       /* Embedded Device Endpoint 0 Receive Data Packet Size Bit 2 */
    byte RP0SIZ3     :1;                                       /* Embedded Device Endpoint 0 Receive Data Packet Size Bit 3 */
    byte DTX1STR     :1;                                       /* Clear Transmit First Flag */
    byte DTX1ST      :1;                                       /* Embedded Device Transmit First Flag */
    byte DSETUP      :1;                                       /* Embedded Device SETUP Token Detect Bit */
    byte DRSEQ       :1;                                       /* Embedded Device Endpoint 0 Receive Sequence Bit */
  } Bits;
  struct {
    byte grpRP0SIZ :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DSRSTR;
extern volatile DSRSTR _DSR;
#define DSR                             _DSR.Byte
#define DSR_RP0SIZ0                     _DSR.Bits.RP0SIZ0
#define DSR_RP0SIZ1                     _DSR.Bits.RP0SIZ1
#define DSR_RP0SIZ2                     _DSR.Bits.RP0SIZ2
#define DSR_RP0SIZ3                     _DSR.Bits.RP0SIZ3
#define DSR_DTX1STR                     _DSR.Bits.DTX1STR
#define DSR_DTX1ST                      _DSR.Bits.DTX1ST
#define DSR_DSETUP                      _DSR.Bits.DSETUP
#define DSR_DRSEQ                       _DSR.Bits.DRSEQ
#define DSR_RP0SIZ                      _DSR.MergedBits.grpRP0SIZ

#define DSR_RP0SIZ0_MASK                1
#define DSR_RP0SIZ1_MASK                2
#define DSR_RP0SIZ2_MASK                4
#define DSR_RP0SIZ3_MASK                8
#define DSR_DTX1STR_MASK                16
#define DSR_DTX1ST_MASK                 32
#define DSR_DSETUP_MASK                 64
#define DSR_DRSEQ_MASK                  128
#define DSR_RP0SIZ_MASK                 15
#define DSR_RP0SIZ_BITNUM               0


/*** KBSCR - Keyboard Status and Control Register; 0x0000004E ***/
typedef union {
  byte Byte;
  struct {
    byte MODEK       :1;                                       /* Keyboard Triggering Sensitivity Bit */
    byte IMASKK      :1;                                       /* Keyboard Interrupt Mask Bit */
    byte ACKK        :1;                                       /* Keyboard Acknowledge Bit */
    byte KEYF        :1;                                       /* Keyboard Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} KBSCRSTR;
extern volatile KBSCRSTR _KBSCR;
#define KBSCR                           _KBSCR.Byte
#define KBSCR_MODEK                     _KBSCR.Bits.MODEK
#define KBSCR_IMASKK                    _KBSCR.Bits.IMASKK
#define KBSCR_ACKK                      _KBSCR.Bits.ACKK
#define KBSCR_KEYF                      _KBSCR.Bits.KEYF

#define KBSCR_MODEK_MASK                1
#define KBSCR_IMASKK_MASK               2
#define KBSCR_ACKK_MASK                 4
#define KBSCR_KEYF_MASK                 8


/*** KBIER - Keyboard Interrupt Enable Register; 0x0000004F ***/
typedef union {
  byte Byte;
  struct {
    byte KBIE0       :1;                                       /* Keyboard Interrupt Enable Bit 0 */
    byte KBIE1       :1;                                       /* Keyboard Interrupt Enable Bit 1 */
    byte KBIE2       :1;                                       /* Keyboard Interrupt Enable Bit 2 */
    byte KBIE3       :1;                                       /* Keyboard Interrupt Enable Bit 3 */
    byte KBIE4       :1;                                       /* Keyboard Interrupt Enable Bit 4 */
    byte KBIE5       :1;                                       /* Keyboard Interrupt Enable Bit 5 */
    byte KBIE6       :1;                                       /* Keyboard Interrupt Enable Bit 6 */
    byte KBIE7       :1;                                       /* Keyboard Interrupt Enable Bit 7 */
  } Bits;
} KBIERSTR;
extern volatile KBIERSTR _KBIER;
#define KBIER                           _KBIER.Byte
#define KBIER_KBIE0                     _KBIER.Bits.KBIE0
#define KBIER_KBIE1                     _KBIER.Bits.KBIE1
#define KBIER_KBIE2                     _KBIER.Bits.KBIE2
#define KBIER_KBIE3                     _KBIER.Bits.KBIE3
#define KBIER_KBIE4                     _KBIER.Bits.KBIE4
#define KBIER_KBIE5                     _KBIER.Bits.KBIE5
#define KBIER_KBIE6                     _KBIER.Bits.KBIE6
#define KBIER_KBIE7                     _KBIER.Bits.KBIE7

#define KBIER_KBIE0_MASK                1
#define KBIER_KBIE1_MASK                2
#define KBIER_KBIE2_MASK                4
#define KBIER_KBIE3_MASK                8
#define KBIER_KBIE4_MASK                16
#define KBIER_KBIE5_MASK                32
#define KBIER_KBIE6_MASK                64
#define KBIER_KBIE7_MASK                128


/*** HDP1CR - USB HUB Downstream Port 1 Control Register; 0x00000051 ***/
typedef union {
  byte Byte;
  struct {
    byte D1MINUS     :1;                                       /* Downstream Port Differential Data MINUS */
    byte D1PLUS      :1;                                       /* Downstream Port Differential Data PLUS */
    byte             :1; 
    byte SUSP1       :1;                                       /* Downstream Port Selective Suspend Bit */
    byte RESUM1      :1;                                       /* Force Resume to the Downstream Port */
    byte RST1        :1;                                       /* Force Reset to the Downstream Port */
    byte LOWSP1      :1;                                       /* Full-Speed / Low-Speed Port Control Bit */
    byte PEN1        :1;                                       /* Downstream Port Enable Control Bit */
  } Bits;
} HDP1CRSTR;
extern volatile HDP1CRSTR _HDP1CR;
#define HDP1CR                          _HDP1CR.Byte
#define HDP1CR_D1MINUS                  _HDP1CR.Bits.D1MINUS
#define HDP1CR_D1PLUS                   _HDP1CR.Bits.D1PLUS
#define HDP1CR_SUSP1                    _HDP1CR.Bits.SUSP1
#define HDP1CR_RESUM1                   _HDP1CR.Bits.RESUM1
#define HDP1CR_RST1                     _HDP1CR.Bits.RST1
#define HDP1CR_LOWSP1                   _HDP1CR.Bits.LOWSP1
#define HDP1CR_PEN1                     _HDP1CR.Bits.PEN1

#define HDP1CR_D1MINUS_MASK             1
#define HDP1CR_D1PLUS_MASK              2
#define HDP1CR_SUSP1_MASK               8
#define HDP1CR_RESUM1_MASK              16
#define HDP1CR_RST1_MASK                32
#define HDP1CR_LOWSP1_MASK              64
#define HDP1CR_PEN1_MASK                128


/*** HDP2CR - USB HUB Downstream Port 2 Control Register; 0x00000052 ***/
typedef union {
  byte Byte;
  struct {
    byte D2MINUS     :1;                                       /* Downstream Port Differential Data MINUS */
    byte D2PLUS      :1;                                       /* Downstream Port Differential Data PLUS */
    byte             :1; 
    byte SUSP2       :1;                                       /* Downstream Port Selective Suspend Bit */
    byte RESUM2      :1;                                       /* Force Resume to the Downstream Port */
    byte RST2        :1;                                       /* Force Reset to the Downstream Port */
    byte LOWSP2      :1;                                       /* Full-Speed / Low-Speed Port Control Bit */
    byte PEN2        :1;                                       /* Downstream Port Enable Control Bit */
  } Bits;
} HDP2CRSTR;
extern volatile HDP2CRSTR _HDP2CR;
#define HDP2CR                          _HDP2CR.Byte
#define HDP2CR_D2MINUS                  _HDP2CR.Bits.D2MINUS
#define HDP2CR_D2PLUS                   _HDP2CR.Bits.D2PLUS
#define HDP2CR_SUSP2                    _HDP2CR.Bits.SUSP2
#define HDP2CR_RESUM2                   _HDP2CR.Bits.RESUM2
#define HDP2CR_RST2                     _HDP2CR.Bits.RST2
#define HDP2CR_LOWSP2                   _HDP2CR.Bits.LOWSP2
#define HDP2CR_PEN2                     _HDP2CR.Bits.PEN2

#define HDP2CR_D2MINUS_MASK             1
#define HDP2CR_D2PLUS_MASK              2
#define HDP2CR_SUSP2_MASK               8
#define HDP2CR_RESUM2_MASK              16
#define HDP2CR_RST2_MASK                32
#define HDP2CR_LOWSP2_MASK              64
#define HDP2CR_PEN2_MASK                128


/*** HDP3CR - USB HUB Downstream Port 3 Control Register; 0x00000053 ***/
typedef union {
  byte Byte;
  struct {
    byte D3MINUS     :1;                                       /* Downstream Port Differential Data MINUS */
    byte D3PLUS      :1;                                       /* Downstream Port Differential Data PLUS */
    byte             :1; 
    byte SUSP3       :1;                                       /* Downstream Port Selective Suspend Bit */
    byte RESUM3      :1;                                       /* Force Resume to the Downstream Port */
    byte RST3        :1;                                       /* Force Reset to the Downstream Port */
    byte LOWSP3      :1;                                       /* Full-Speed / Low-Speed Port Control Bit */
    byte PEN3        :1;                                       /* Downstream Port Enable Control Bit */
  } Bits;
} HDP3CRSTR;
extern volatile HDP3CRSTR _HDP3CR;
#define HDP3CR                          _HDP3CR.Byte
#define HDP3CR_D3MINUS                  _HDP3CR.Bits.D3MINUS
#define HDP3CR_D3PLUS                   _HDP3CR.Bits.D3PLUS
#define HDP3CR_SUSP3                    _HDP3CR.Bits.SUSP3
#define HDP3CR_RESUM3                   _HDP3CR.Bits.RESUM3
#define HDP3CR_RST3                     _HDP3CR.Bits.RST3
#define HDP3CR_LOWSP3                   _HDP3CR.Bits.LOWSP3
#define HDP3CR_PEN3                     _HDP3CR.Bits.PEN3

#define HDP3CR_D3MINUS_MASK             1
#define HDP3CR_D3PLUS_MASK              2
#define HDP3CR_SUSP3_MASK               8
#define HDP3CR_RESUM3_MASK              16
#define HDP3CR_RST3_MASK                32
#define HDP3CR_LOWSP3_MASK              64
#define HDP3CR_PEN3_MASK                128


/*** HDP4CR - USB HUB Downstream Port 4 Control Register; 0x00000054 ***/
typedef union {
  byte Byte;
  struct {
    byte D4MINUS     :1;                                       /* Downstream Port Differential Data MINUS */
    byte D4PLUS      :1;                                       /* Downstream Port Differential Data PLUS */
    byte             :1; 
    byte SUSP4       :1;                                       /* Downstream Port Selective Suspend Bit */
    byte RESUM4      :1;                                       /* Force Resume to the Downstream Port */
    byte RST4        :1;                                       /* Force Reset to the Downstream Port */
    byte LOWSP4      :1;                                       /* Full-Speed / Low-Speed Port Control Bit */
    byte PEN4        :1;                                       /* Downstream Port Enable Control Bit */
  } Bits;
} HDP4CRSTR;
extern volatile HDP4CRSTR _HDP4CR;
#define HDP4CR                          _HDP4CR.Byte
#define HDP4CR_D4MINUS                  _HDP4CR.Bits.D4MINUS
#define HDP4CR_D4PLUS                   _HDP4CR.Bits.D4PLUS
#define HDP4CR_SUSP4                    _HDP4CR.Bits.SUSP4
#define HDP4CR_RESUM4                   _HDP4CR.Bits.RESUM4
#define HDP4CR_RST4                     _HDP4CR.Bits.RST4
#define HDP4CR_LOWSP4                   _HDP4CR.Bits.LOWSP4
#define HDP4CR_PEN4                     _HDP4CR.Bits.PEN4

#define HDP4CR_D4MINUS_MASK             1
#define HDP4CR_D4PLUS_MASK              2
#define HDP4CR_SUSP4_MASK               8
#define HDP4CR_RESUM4_MASK              16
#define HDP4CR_RST4_MASK                32
#define HDP4CR_LOWSP4_MASK              64
#define HDP4CR_PEN4_MASK                128


/*** SIETIR - USB SIE Timing Interrupt Register; 0x00000056 ***/
typedef union {
  byte Byte;
  struct {
    byte TRANIE      :1;                                       /* Bus Signal Transition Detect Interrupt Enable */
    byte EOPIE       :1;                                       /* End of Packet Detect Interrupt Enable */
    byte OEF2IE      :1;                                       /* The Second End Of Frame Point Interrupt Enable */
    byte SOFIE       :1;                                       /* Start Of Frame Interrupt Enable */
    byte TRANF       :1;                                       /* Bus Signal Transition Detect Flag */
    byte EOPF        :1;                                       /* End of Packet Detect Flag */
    byte EOF2F       :1;                                       /* Second End Of Frame Point Flag */
    byte SOFF        :1;                                       /* Start Of Frame Detect Flag */
  } Bits;
} SIETIRSTR;
extern volatile SIETIRSTR _SIETIR;
#define SIETIR                          _SIETIR.Byte
#define SIETIR_TRANIE                   _SIETIR.Bits.TRANIE
#define SIETIR_EOPIE                    _SIETIR.Bits.EOPIE
#define SIETIR_OEF2IE                   _SIETIR.Bits.OEF2IE
#define SIETIR_SOFIE                    _SIETIR.Bits.SOFIE
#define SIETIR_TRANF                    _SIETIR.Bits.TRANF
#define SIETIR_EOPF                     _SIETIR.Bits.EOPF
#define SIETIR_EOF2F                    _SIETIR.Bits.EOF2F
#define SIETIR_SOFF                     _SIETIR.Bits.SOFF

#define SIETIR_TRANIE_MASK              1
#define SIETIR_EOPIE_MASK               2
#define SIETIR_OEF2IE_MASK              4
#define SIETIR_SOFIE_MASK               8
#define SIETIR_TRANF_MASK               16
#define SIETIR_EOPF_MASK                32
#define SIETIR_EOF2F_MASK               64
#define SIETIR_SOFF_MASK                128


/*** SIETSR - USB SIE Timing Status Register; 0x00000057 ***/
typedef union {
  byte Byte;
  struct {
    byte TRANFR      :1;                                       /* Bus Signal Transition Flag Reset */
    byte EOPFR       :1;                                       /* End of Packet Flag Reset */
    byte EOF2FR      :1;                                       /* The second End of Frame Point Flag Reset */
    byte LOCKFR      :1;                                       /* Clear Frame Timer Locked Flag */
    byte SOFFR       :1;                                       /* Start Of Frame Flag Reset */
    byte LOCKF       :1;                                       /* USB Frame Timer Locked */
    byte RSTFR       :1;                                       /* Clear Reset Flag Bit */
    byte RSTF        :1;                                       /* USB Reset Flag */
  } Bits;
} SIETSRSTR;
extern volatile SIETSRSTR _SIETSR;
#define SIETSR                          _SIETSR.Byte
#define SIETSR_TRANFR                   _SIETSR.Bits.TRANFR
#define SIETSR_EOPFR                    _SIETSR.Bits.EOPFR
#define SIETSR_EOF2FR                   _SIETSR.Bits.EOF2FR
#define SIETSR_LOCKFR                   _SIETSR.Bits.LOCKFR
#define SIETSR_SOFFR                    _SIETSR.Bits.SOFFR
#define SIETSR_LOCKF                    _SIETSR.Bits.LOCKF
#define SIETSR_RSTFR                    _SIETSR.Bits.RSTFR
#define SIETSR_RSTF                     _SIETSR.Bits.RSTF

#define SIETSR_TRANFR_MASK              1
#define SIETSR_EOPFR_MASK               2
#define SIETSR_EOF2FR_MASK              4
#define SIETSR_LOCKFR_MASK              8
#define SIETSR_SOFFR_MASK               16
#define SIETSR_LOCKF_MASK               32
#define SIETSR_RSTFR_MASK               64
#define SIETSR_RSTF_MASK                128


/*** HADDR - USB HUB Address Register; 0x00000058 ***/
typedef union {
  byte Byte;
  struct {
    byte ADD0        :1;                                       /* USB HUB Function Address Bit 0 */
    byte ADD1        :1;                                       /* USB HUB Function Address Bit 1 */
    byte ADD2        :1;                                       /* USB HUB Function Address Bit 2 */
    byte ADD3        :1;                                       /* USB HUB Function Address Bit 3 */
    byte ADD4        :1;                                       /* USB HUB Function Address Bit 4 */
    byte ADD5        :1;                                       /* USB HUB Function Address Bit 5 */
    byte ADD6        :1;                                       /* USB HUB Function Address Bit 6 */
    byte USBEN       :1;                                       /* USB Module Enable */
  } Bits;
  struct {
    byte grpADD  :7;
    byte         :1;
  } MergedBits;
} HADDRSTR;
extern volatile HADDRSTR _HADDR;
#define HADDR                           _HADDR.Byte
#define HADDR_ADD0                      _HADDR.Bits.ADD0
#define HADDR_ADD1                      _HADDR.Bits.ADD1
#define HADDR_ADD2                      _HADDR.Bits.ADD2
#define HADDR_ADD3                      _HADDR.Bits.ADD3
#define HADDR_ADD4                      _HADDR.Bits.ADD4
#define HADDR_ADD5                      _HADDR.Bits.ADD5
#define HADDR_ADD6                      _HADDR.Bits.ADD6
#define HADDR_USBEN                     _HADDR.Bits.USBEN
#define HADDR_ADD                       _HADDR.MergedBits.grpADD

#define HADDR_ADD0_MASK                 1
#define HADDR_ADD1_MASK                 2
#define HADDR_ADD2_MASK                 4
#define HADDR_ADD3_MASK                 8
#define HADDR_ADD4_MASK                 16
#define HADDR_ADD5_MASK                 32
#define HADDR_ADD6_MASK                 64
#define HADDR_USBEN_MASK                128
#define HADDR_ADD_MASK                  127
#define HADDR_ADD_BITNUM                0


/*** HIR0 - USB HUB Interrupt Register 0; 0x00000059 ***/
typedef union {
  byte Byte;
  struct {
    byte RXDFR       :1;                                       /* Hub Endpoint 0 Receive Flag Reset */
    byte TXDFR       :1;                                       /* Hub Endpoint 0 Transmit Flag Reset */
    byte RXDIE       :1;                                       /* Hub Endpoint 0 Receive Interrupt Enable */
    byte TXDIE       :1;                                       /* Hub Endpoint 0 Transmit Interrupt Enable */
    byte             :1; 
    byte             :1; 
    byte RXDF        :1;                                       /* Hub Endpoint 0 Data Receive Flag */
    byte TXDF        :1;                                       /* Hub Endpoint 0 Data Transmit Flag */
  } Bits;
} HIR0STR;
extern volatile HIR0STR _HIR0;
#define HIR0                            _HIR0.Byte
#define HIR0_RXDFR                      _HIR0.Bits.RXDFR
#define HIR0_TXDFR                      _HIR0.Bits.TXDFR
#define HIR0_RXDIE                      _HIR0.Bits.RXDIE
#define HIR0_TXDIE                      _HIR0.Bits.TXDIE
#define HIR0_RXDF                       _HIR0.Bits.RXDF
#define HIR0_TXDF                       _HIR0.Bits.TXDF

#define HIR0_RXDFR_MASK                 1
#define HIR0_TXDFR_MASK                 2
#define HIR0_RXDIE_MASK                 4
#define HIR0_TXDIE_MASK                 8
#define HIR0_RXDF_MASK                  64
#define HIR0_TXDF_MASK                  128


/*** HCR0 - USB Hub Control Register 0; 0x0000005B ***/
typedef union {
  byte Byte;
  struct {
    byte TPSIZ0      :1;                                       /* Hub Endpoint 0 Transmit Data Packet Size Bit 0 */
    byte TPSIZ1      :1;                                       /* Hub Endpoint 0 Transmit Data Packet Size Bit 1 */
    byte TPSIZ2      :1;                                       /* Hub Endpoint 0 Transmit Data Packet Size Bit 2 */
    byte TPSIZ3      :1;                                       /* Hub Endpoint 0 Transmit Data Packet Size Bit 3 */
    byte RXE         :1;                                       /* Hub Endpoint 0 Receive Enable */
    byte TXE         :1;                                       /* Hub Endpoint 0 Transmit Enable */
    byte STALL0      :1;                                       /* Hub Endpoint 0 Force Stall Bit */
    byte TSEQ        :1;                                       /* Hub Endpoint 0 Transmit Sequence Bit */
  } Bits;
  struct {
    byte grpTPSIZ :4;
    byte         :1;
    byte         :1;
    byte grpSTALL :1;
    byte         :1;
  } MergedBits;
} HCR0STR;
extern volatile HCR0STR _HCR0;
#define HCR0                            _HCR0.Byte
#define HCR0_TPSIZ0                     _HCR0.Bits.TPSIZ0
#define HCR0_TPSIZ1                     _HCR0.Bits.TPSIZ1
#define HCR0_TPSIZ2                     _HCR0.Bits.TPSIZ2
#define HCR0_TPSIZ3                     _HCR0.Bits.TPSIZ3
#define HCR0_RXE                        _HCR0.Bits.RXE
#define HCR0_TXE                        _HCR0.Bits.TXE
#define HCR0_STALL0                     _HCR0.Bits.STALL0
#define HCR0_TSEQ                       _HCR0.Bits.TSEQ
#define HCR0_TPSIZ                      _HCR0.MergedBits.grpTPSIZ

#define HCR0_TPSIZ0_MASK                1
#define HCR0_TPSIZ1_MASK                2
#define HCR0_TPSIZ2_MASK                4
#define HCR0_TPSIZ3_MASK                8
#define HCR0_RXE_MASK                   16
#define HCR0_TXE_MASK                   32
#define HCR0_STALL0_MASK                64
#define HCR0_TSEQ_MASK                  128
#define HCR0_TPSIZ_MASK                 15
#define HCR0_TPSIZ_BITNUM               0


/*** HCDR - USB Hub Endpoint 1 Control and Data Register; 0x0000005C ***/
typedef union {
  byte Byte;
  struct {
    byte PCHG0       :1;                                       /* Hub and Port Status Change Bitmap Bit 0 */
    byte PCHG1       :1;                                       /* Hub and Port Status Change Bitmap Bit 1 */
    byte PCHG2       :1;                                       /* Hub and Port Status Change Bitmap Bit 2 */
    byte PCHG3       :1;                                       /* Hub and Port Status Change Bitmap Bit 3 */
    byte PCHG4       :1;                                       /* Hub and Port Status Change Bitmap Bit 4 */
    byte PCHG5       :1;                                       /* Hub and Port Status Change Bitmap Bit 5 */
    byte PNEW        :1;                                       /* Port New Status Change */
    byte STALL1      :1;                                       /* Hub Endpoint 1 Force Stall Bit */
  } Bits;
  struct {
    byte grpPCHG :6;
    byte         :1;
    byte grpSTALL_1 :1;
  } MergedBits;
} HCDRSTR;
extern volatile HCDRSTR _HCDR;
#define HCDR                            _HCDR.Byte
#define HCDR_PCHG0                      _HCDR.Bits.PCHG0
#define HCDR_PCHG1                      _HCDR.Bits.PCHG1
#define HCDR_PCHG2                      _HCDR.Bits.PCHG2
#define HCDR_PCHG3                      _HCDR.Bits.PCHG3
#define HCDR_PCHG4                      _HCDR.Bits.PCHG4
#define HCDR_PCHG5                      _HCDR.Bits.PCHG5
#define HCDR_PNEW                       _HCDR.Bits.PNEW
#define HCDR_STALL1                     _HCDR.Bits.STALL1
#define HCDR_PCHG                       _HCDR.MergedBits.grpPCHG

#define HCDR_PCHG0_MASK                 1
#define HCDR_PCHG1_MASK                 2
#define HCDR_PCHG2_MASK                 4
#define HCDR_PCHG3_MASK                 8
#define HCDR_PCHG4_MASK                 16
#define HCDR_PCHG5_MASK                 32
#define HCDR_PNEW_MASK                  64
#define HCDR_STALL1_MASK                128
#define HCDR_PCHG_MASK                  63
#define HCDR_PCHG_BITNUM                0


/*** HSR - USB Hub Status Register; 0x0000005D ***/
typedef union {
  byte Byte;
  struct {
    byte PRSIZ0      :1;                                       /* Hub Endpoint 0 Receive Data Packet Size Bit 0 */
    byte PRSIZ1      :1;                                       /* Hub Endpoint 0 Receive Data Packet Size Bit 1 */
    byte PRSIZ2      :1;                                       /* Hub Endpoint 0 Receive Data Packet Size Bit 2 */
    byte PRSIZ3      :1;                                       /* Hub Endpoint 0 Receive Data Packet Size Bit 3 */
    byte TX1STR      :1;                                       /* Clear Hub Transmit First Flag */
    byte TX1ST       :1;                                       /* Hub Transmit First Flag */
    byte SETUP       :1;                                       /* Hub SETUP Token Detect Bit */
    byte RSEQ        :1;                                       /* Hub Endpoint 0 Receive Sequence Bit */
  } Bits;
  struct {
    byte grpPRSIZ :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} HSRSTR;
extern volatile HSRSTR _HSR;
#define HSR                             _HSR.Byte
#define HSR_PRSIZ0                      _HSR.Bits.PRSIZ0
#define HSR_PRSIZ1                      _HSR.Bits.PRSIZ1
#define HSR_PRSIZ2                      _HSR.Bits.PRSIZ2
#define HSR_PRSIZ3                      _HSR.Bits.PRSIZ3
#define HSR_TX1STR                      _HSR.Bits.TX1STR
#define HSR_TX1ST                       _HSR.Bits.TX1ST
#define HSR_SETUP                       _HSR.Bits.SETUP
#define HSR_RSEQ                        _HSR.Bits.RSEQ
#define HSR_PRSIZ                       _HSR.MergedBits.grpPRSIZ

#define HSR_PRSIZ0_MASK                 1
#define HSR_PRSIZ1_MASK                 2
#define HSR_PRSIZ2_MASK                 4
#define HSR_PRSIZ3_MASK                 8
#define HSR_TX1STR_MASK                 16
#define HSR_TX1ST_MASK                  32
#define HSR_SETUP_MASK                  64
#define HSR_RSEQ_MASK                   128
#define HSR_PRSIZ_MASK                  15
#define HSR_PRSIZ_BITNUM                0


/*** HRPCR - USB Hub Root Port Control Register; 0x0000005E ***/
typedef union {
  byte Byte;
  struct {
    byte D0MINUS     :1;                                       /* Root Port Differential Data MINUS */
    byte D0PLUS      :1;                                       /* Root Port Differential Data PLUS */
    byte             :1; 
    byte SUSPND      :1;                                       /* USB Suspend Control Bit */
    byte RESUM0      :1;                                       /* Force Resume to the Root Port */
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} HRPCRSTR;
extern volatile HRPCRSTR _HRPCR;
#define HRPCR                           _HRPCR.Byte
#define HRPCR_D0MINUS                   _HRPCR.Bits.D0MINUS
#define HRPCR_D0PLUS                    _HRPCR.Bits.D0PLUS
#define HRPCR_SUSPND                    _HRPCR.Bits.SUSPND
#define HRPCR_RESUM0                    _HRPCR.Bits.RESUM0

#define HRPCR_D0MINUS_MASK              1
#define HRPCR_D0PLUS_MASK               2
#define HRPCR_SUSPND_MASK               8
#define HRPCR_RESUM0_MASK               16


/*** OSDCR - OSD Control Register; 0x00000060 ***/
typedef union {
  byte Byte;
  struct {
    byte OSDIEN      :1;                                       /* OSD Interrupt Enable */
    byte HALFCLK     :1;                                       /* Half Frequency of Pixel Clock */
    byte CLKPH0      :1;                                       /* Pixel Clock Phase Adjustment Bit 0 */
    byte CLKPH1      :1;                                       /* Pixel Clock Phase Adjustment Bit 1 */
    byte CLKINV      :1;                                       /* Pixel Clock Inversion */
    byte OSDRST      :1;                                       /* OSD Module Reset */
    byte             :1; 
    byte OSDMEN      :1;                                       /* OSD Memory Enable */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpCLKPH :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} OSDCRSTR;
extern volatile OSDCRSTR _OSDCR;
#define OSDCR                           _OSDCR.Byte
#define OSDCR_OSDIEN                    _OSDCR.Bits.OSDIEN
#define OSDCR_HALFCLK                   _OSDCR.Bits.HALFCLK
#define OSDCR_CLKPH0                    _OSDCR.Bits.CLKPH0
#define OSDCR_CLKPH1                    _OSDCR.Bits.CLKPH1
#define OSDCR_CLKINV                    _OSDCR.Bits.CLKINV
#define OSDCR_OSDRST                    _OSDCR.Bits.OSDRST
#define OSDCR_OSDMEN                    _OSDCR.Bits.OSDMEN
#define OSDCR_CLKPH                     _OSDCR.MergedBits.grpCLKPH

#define OSDCR_OSDIEN_MASK               1
#define OSDCR_HALFCLK_MASK              2
#define OSDCR_CLKPH0_MASK               4
#define OSDCR_CLKPH1_MASK               8
#define OSDCR_CLKINV_MASK               16
#define OSDCR_OSDRST_MASK               32
#define OSDCR_OSDMEN_MASK               128
#define OSDCR_CLKPH_MASK                12
#define OSDCR_CLKPH_BITNUM              2


/*** OSDSR - OSD Status Register; 0x00000061 ***/
typedef union {
  byte Byte;
  struct {
    byte DENDIF      :1;                                       /* OSD Display Interrupt End */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte WRDY        :1;                                       /* OSD Buffer Write Ready */
  } Bits;
} OSDSRSTR;
extern volatile OSDSRSTR _OSDSR;
#define OSDSR                           _OSDSR.Byte
#define OSDSR_DENDIF                    _OSDSR.Bits.DENDIF
#define OSDSR_WRDY                      _OSDSR.Bits.WRDY

#define OSDSR_DENDIF_MASK               1
#define OSDSR_WRDY_MASK                 128


/*** OSDDR - OSD Data Register; 0x00000062 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** OSDDRL - OSD Data Register Low; 0x00000062 ***/
    union {
      byte Byte;
      struct {
        byte OSDD0       :1;                                       /* OSD Data Bit 0 */
        byte OSDD1       :1;                                       /* OSD Data Bit 1 */
        byte OSDD2       :1;                                       /* OSD Data Bit 2 */
        byte OSDD3       :1;                                       /* OSD Data Bit 3 */
        byte OSDD4       :1;                                       /* OSD Data Bit 4 */
        byte OSDD5       :1;                                       /* OSD Data Bit 5 */
        byte OSDD6       :1;                                       /* OSD Data Bit 6 */
        byte OSDD7       :1;                                       /* OSD Data Bit 7 */
      } Bits;
    } OSDDRLSTR;
    #define OSDDRL                      _OSDDR.Overlap_STR.OSDDRLSTR.Byte
    #define OSDDRL_OSDD0                _OSDDR.Overlap_STR.OSDDRLSTR.Bits.OSDD0
    #define OSDDRL_OSDD1                _OSDDR.Overlap_STR.OSDDRLSTR.Bits.OSDD1
    #define OSDDRL_OSDD2                _OSDDR.Overlap_STR.OSDDRLSTR.Bits.OSDD2
    #define OSDDRL_OSDD3                _OSDDR.Overlap_STR.OSDDRLSTR.Bits.OSDD3
    #define OSDDRL_OSDD4                _OSDDR.Overlap_STR.OSDDRLSTR.Bits.OSDD4
    #define OSDDRL_OSDD5                _OSDDR.Overlap_STR.OSDDRLSTR.Bits.OSDD5
    #define OSDDRL_OSDD6                _OSDDR.Overlap_STR.OSDDRLSTR.Bits.OSDD6
    #define OSDDRL_OSDD7                _OSDDR.Overlap_STR.OSDDRLSTR.Bits.OSDD7
    
    #define OSDDRL_OSDD0_MASK           1
    #define OSDDRL_OSDD1_MASK           2
    #define OSDDRL_OSDD2_MASK           4
    #define OSDDRL_OSDD3_MASK           8
    #define OSDDRL_OSDD4_MASK           16
    #define OSDDRL_OSDD5_MASK           32
    #define OSDDRL_OSDD6_MASK           64
    #define OSDDRL_OSDD7_MASK           128
    

    /*** OSDDRH - OSD Data Register High; 0x00000063 ***/
    union {
      byte Byte;
      struct {
        byte OSDD8       :1;                                       /* OSD Data Bit 8 */
        byte OSDD9       :1;                                       /* OSD Data Bit 9 */
        byte OSDD10      :1;                                       /* OSD Data Bit 10 */
        byte OSDD11      :1;                                       /* OSD Data Bit 11 */
        byte OSDD12      :1;                                       /* OSD Data Bit 12 */
        byte OSDD13      :1;                                       /* OSD Data Bit 13 */
        byte OSDD14      :1;                                       /* OSD Data Bit 14 */
        byte OSDD15      :1;                                       /* OSD Data Bit 15 */
      } Bits;
    } OSDDRHSTR;
    #define OSDDRH                      _OSDDR.Overlap_STR.OSDDRHSTR.Byte
    #define OSDDRH_OSDD8                _OSDDR.Overlap_STR.OSDDRHSTR.Bits.OSDD8
    #define OSDDRH_OSDD9                _OSDDR.Overlap_STR.OSDDRHSTR.Bits.OSDD9
    #define OSDDRH_OSDD10               _OSDDR.Overlap_STR.OSDDRHSTR.Bits.OSDD10
    #define OSDDRH_OSDD11               _OSDDR.Overlap_STR.OSDDRHSTR.Bits.OSDD11
    #define OSDDRH_OSDD12               _OSDDR.Overlap_STR.OSDDRHSTR.Bits.OSDD12
    #define OSDDRH_OSDD13               _OSDDR.Overlap_STR.OSDDRHSTR.Bits.OSDD13
    #define OSDDRH_OSDD14               _OSDDR.Overlap_STR.OSDDRHSTR.Bits.OSDD14
    #define OSDDRH_OSDD15               _OSDDR.Overlap_STR.OSDDRHSTR.Bits.OSDD15
    
    #define OSDDRH_OSDD8_MASK           1
    #define OSDDRH_OSDD9_MASK           2
    #define OSDDRH_OSDD10_MASK          4
    #define OSDDRH_OSDD11_MASK          8
    #define OSDDRH_OSDD12_MASK          16
    #define OSDDRH_OSDD13_MASK          32
    #define OSDDRH_OSDD14_MASK          64
    #define OSDDRH_OSDD15_MASK          128
    
  } Overlap_STR;

} OSDDRSTR;
extern volatile OSDDRSTR _OSDDR;
#define OSDDR                           _OSDDR.Word


/*** OSDRAR - OSD Row Address Register; 0x00000064 ***/
typedef union {
  byte Byte;
  struct {
    byte ROWA0       :1;                                       /* OSD Row Address Bit 0 */
    byte ROWA1       :1;                                       /* OSD Row Address Bit 1 */
    byte ROWA2       :1;                                       /* OSD Row Address Bit 2 */
    byte ROWA3       :1;                                       /* OSD Row Address Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpROWA :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} OSDRARSTR;
extern volatile OSDRARSTR _OSDRAR;
#define OSDRAR                          _OSDRAR.Byte
#define OSDRAR_ROWA0                    _OSDRAR.Bits.ROWA0
#define OSDRAR_ROWA1                    _OSDRAR.Bits.ROWA1
#define OSDRAR_ROWA2                    _OSDRAR.Bits.ROWA2
#define OSDRAR_ROWA3                    _OSDRAR.Bits.ROWA3
#define OSDRAR_ROWA                     _OSDRAR.MergedBits.grpROWA

#define OSDRAR_ROWA0_MASK               1
#define OSDRAR_ROWA1_MASK               2
#define OSDRAR_ROWA2_MASK               4
#define OSDRAR_ROWA3_MASK               8
#define OSDRAR_ROWA_MASK                15
#define OSDRAR_ROWA_BITNUM              0


/*** OSDCAR - OSD Column Address Register; 0x00000065 ***/
typedef union {
  byte Byte;
  struct {
    byte COLA0       :1;                                       /* OSD RAM Column Address Bit 0 */
    byte COLA1       :1;                                       /* OSD RAM Column Address Bit 1 */
    byte COLA2       :1;                                       /* OSD RAM Column Address Bit 2 */
    byte COLA3       :1;                                       /* OSD RAM Column Address Bit 3 */
    byte COLA4       :1;                                       /* OSD RAM Column Address Bit 4 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpCOLA :5;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} OSDCARSTR;
extern volatile OSDCARSTR _OSDCAR;
#define OSDCAR                          _OSDCAR.Byte
#define OSDCAR_COLA0                    _OSDCAR.Bits.COLA0
#define OSDCAR_COLA1                    _OSDCAR.Bits.COLA1
#define OSDCAR_COLA2                    _OSDCAR.Bits.COLA2
#define OSDCAR_COLA3                    _OSDCAR.Bits.COLA3
#define OSDCAR_COLA4                    _OSDCAR.Bits.COLA4
#define OSDCAR_COLA                     _OSDCAR.MergedBits.grpCOLA

#define OSDCAR_COLA0_MASK               1
#define OSDCAR_COLA1_MASK               2
#define OSDCAR_COLA2_MASK               4
#define OSDCAR_COLA3_MASK               8
#define OSDCAR_COLA4_MASK               16
#define OSDCAR_COLA_MASK                31
#define OSDCAR_COLA_BITNUM              0


/*** OSDEHBUF - OSD FLASH Even High Byte Write Buffer; 0x00000066 ***/
typedef union {
  byte Byte;
  struct {
    byte DOT8        :1;                                       /* OSD FLASH Even High Byte Buffer Bit 8 */
    byte DOT9        :1;                                       /* OSD FLASH Even High Byte Buffer Bit 9 */
    byte DOT10       :1;                                       /* OSD FLASH Even High Byte Buffer Bit 10 */
    byte DOT11       :1;                                       /* OSD FLASH Even High Byte Buffer Bit 11 */
    byte DOT12       :1;                                       /* OSD FLASH Even High Byte Buffer Bit 12 */
    byte DOT13       :1;                                       /* OSD FLASH Even High Byte Buffer Bit 13 */
    byte DOT14       :1;                                       /* OSD FLASH Even High Byte Buffer Bit 14 */
    byte DOT15       :1;                                       /* OSD FLASH Even High Byte Buffer Bit 15 */
  } Bits;
} OSDEHBUFSTR;
extern volatile OSDEHBUFSTR _OSDEHBUF;
#define OSDEHBUF                        _OSDEHBUF.Byte
#define OSDEHBUF_DOT8                   _OSDEHBUF.Bits.DOT8
#define OSDEHBUF_DOT9                   _OSDEHBUF.Bits.DOT9
#define OSDEHBUF_DOT10                  _OSDEHBUF.Bits.DOT10
#define OSDEHBUF_DOT11                  _OSDEHBUF.Bits.DOT11
#define OSDEHBUF_DOT12                  _OSDEHBUF.Bits.DOT12
#define OSDEHBUF_DOT13                  _OSDEHBUF.Bits.DOT13
#define OSDEHBUF_DOT14                  _OSDEHBUF.Bits.DOT14
#define OSDEHBUF_DOT15                  _OSDEHBUF.Bits.DOT15

#define OSDEHBUF_DOT8_MASK              1
#define OSDEHBUF_DOT9_MASK              2
#define OSDEHBUF_DOT10_MASK             4
#define OSDEHBUF_DOT11_MASK             8
#define OSDEHBUF_DOT12_MASK             16
#define OSDEHBUF_DOT13_MASK             32
#define OSDEHBUF_DOT14_MASK             64
#define OSDEHBUF_DOT15_MASK             128


/*** PECR - Port E Control Register; 0x00000068 ***/
typedef union {
  byte Byte;
  struct {
    byte USBDS1E     :1;                                       /* USB HUB Data Pin 1 Enable */
    byte USBDS2E     :1;                                       /* USB HUB Data Pin 2 Enable */
    byte USBDS3E     :1;                                       /* USB HUB Data Pin 3 Enable */
    byte USBDS4E     :1;                                       /* USB HUB Data Pin 4 Enable */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} PECRSTR;
extern volatile PECRSTR _PECR;
#define PECR                            _PECR.Byte
#define PECR_USBDS1E                    _PECR.Bits.USBDS1E
#define PECR_USBDS2E                    _PECR.Bits.USBDS2E
#define PECR_USBDS3E                    _PECR.Bits.USBDS3E
#define PECR_USBDS4E                    _PECR.Bits.USBDS4E

#define PECR_USBDS1E_MASK               1
#define PECR_USBDS2E_MASK               2
#define PECR_USBDS3E_MASK               4
#define PECR_USBDS4E_MASK               8


/*** PDCR - Port D Configuration Register; 0x00000069 ***/
typedef union {
  byte Byte;
  struct {
    byte DCLKE       :1;                                       /* DCLK Pin Enable */
    byte DEE         :1;                                       /* DE Pin Enable */
    byte VOUTE       :1;                                       /* VOUT Pin Enable */
    byte HOUTE       :1;                                       /* HOUT Pin Enable */
    byte DDCSCLE     :1;                                       /* DDC Clock Pin Enable */
    byte DDCDATE     :1;                                       /* DDC Data Pin Enable */
    byte IICSCLE     :1;                                       /* MMIIC Clock Pin Enable */
    byte IICDATE     :1;                                       /* MMIIC Data Pin Enable */
  } Bits;
} PDCRSTR;
extern volatile PDCRSTR _PDCR;
#define PDCR                            _PDCR.Byte
#define PDCR_DCLKE                      _PDCR.Bits.DCLKE
#define PDCR_DEE                        _PDCR.Bits.DEE
#define PDCR_VOUTE                      _PDCR.Bits.VOUTE
#define PDCR_HOUTE                      _PDCR.Bits.HOUTE
#define PDCR_DDCSCLE                    _PDCR.Bits.DDCSCLE
#define PDCR_DDCDATE                    _PDCR.Bits.DDCDATE
#define PDCR_IICSCLE                    _PDCR.Bits.IICSCLE
#define PDCR_IICDATE                    _PDCR.Bits.IICDATE

#define PDCR_DCLKE_MASK                 1
#define PDCR_DEE_MASK                   2
#define PDCR_VOUTE_MASK                 4
#define PDCR_HOUTE_MASK                 8
#define PDCR_DDCSCLE_MASK               16
#define PDCR_DDCDATE_MASK               32
#define PDCR_IICSCLE_MASK               64
#define PDCR_IICDATE_MASK               128


/*** MIMCR - Multi-Master IIC Master Control Register; 0x0000006A ***/
typedef union {
  byte Byte;
  struct {
    byte MMBR0       :1;                                       /* Baud Rate Select Bit 0 */
    byte MMBR1       :1;                                       /* Baud Rate Select Bit 1 */
    byte MMBR2       :1;                                       /* Baud Rate Select Bit 2 */
    byte MMRW        :1;                                       /* Master Read/Write */
    byte MMAST       :1;                                       /* Master Control Bit */
    byte MMBB        :1;                                       /* Bus Busy Flag */
    byte MMNAKIF     :1;                                       /* No Acknowledge Interrupt Flag */
    byte MMALIF      :1;                                       /* Multi-Master Arbitration Lost Interrupt Flag */
  } Bits;
  struct {
    byte grpMMBR :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} MIMCRSTR;
extern volatile MIMCRSTR _MIMCR;
#define MIMCR                           _MIMCR.Byte
#define MIMCR_MMBR0                     _MIMCR.Bits.MMBR0
#define MIMCR_MMBR1                     _MIMCR.Bits.MMBR1
#define MIMCR_MMBR2                     _MIMCR.Bits.MMBR2
#define MIMCR_MMRW                      _MIMCR.Bits.MMRW
#define MIMCR_MMAST                     _MIMCR.Bits.MMAST
#define MIMCR_MMBB                      _MIMCR.Bits.MMBB
#define MIMCR_MMNAKIF                   _MIMCR.Bits.MMNAKIF
#define MIMCR_MMALIF                    _MIMCR.Bits.MMALIF
#define MIMCR_MMBR                      _MIMCR.MergedBits.grpMMBR

#define MIMCR_MMBR0_MASK                1
#define MIMCR_MMBR1_MASK                2
#define MIMCR_MMBR2_MASK                4
#define MIMCR_MMRW_MASK                 8
#define MIMCR_MMAST_MASK                16
#define MIMCR_MMBB_MASK                 32
#define MIMCR_MMNAKIF_MASK              64
#define MIMCR_MMALIF_MASK               128
#define MIMCR_MMBR_MASK                 7
#define MIMCR_MMBR_BITNUM               0


/*** MMADR - Multi-Master IIC Address Register; 0x0000006B ***/
typedef union {
  byte Byte;
  struct {
    byte MMEXTAD     :1;                                       /* Multi-Master Expanded Address */
    byte MMAD1       :1;                                       /* Multi-Master Address Bit 1 */
    byte MMAD2       :1;                                       /* Multi-Master Address Bit 2 */
    byte MMAD3       :1;                                       /* Multi-Master Address Bit 3 */
    byte MMAD4       :1;                                       /* Multi-Master Address Bit 4 */
    byte MMAD5       :1;                                       /* Multi-Master Address Bit 5 */
    byte MMAD6       :1;                                       /* Multi-Master Address Bit 6 */
    byte MMAD7       :1;                                       /* Multi-Master Address Bit 7 */
  } Bits;
  struct {
    byte         :1;
    byte grpMMAD_1 :7;
  } MergedBits;
} MMADRSTR;
extern volatile MMADRSTR _MMADR;
#define MMADR                           _MMADR.Byte
#define MMADR_MMEXTAD                   _MMADR.Bits.MMEXTAD
#define MMADR_MMAD1                     _MMADR.Bits.MMAD1
#define MMADR_MMAD2                     _MMADR.Bits.MMAD2
#define MMADR_MMAD3                     _MMADR.Bits.MMAD3
#define MMADR_MMAD4                     _MMADR.Bits.MMAD4
#define MMADR_MMAD5                     _MMADR.Bits.MMAD5
#define MMADR_MMAD6                     _MMADR.Bits.MMAD6
#define MMADR_MMAD7                     _MMADR.Bits.MMAD7
#define MMADR_MMAD_1                    _MMADR.MergedBits.grpMMAD_1
#define MMADR_MMAD                      MMADR_MMAD_1

#define MMADR_MMEXTAD_MASK              1
#define MMADR_MMAD1_MASK                2
#define MMADR_MMAD2_MASK                4
#define MMADR_MMAD3_MASK                8
#define MMADR_MMAD4_MASK                16
#define MMADR_MMAD5_MASK                32
#define MMADR_MMAD6_MASK                64
#define MMADR_MMAD7_MASK                128
#define MMADR_MMAD_1_MASK               254
#define MMADR_MMAD_1_BITNUM             1


/*** MMCR - Multi-Master IIC Control Register; 0x0000006C ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte MMTXAK      :1;                                       /* Transmit Acknowledge Enable */
    byte             :1; 
    byte             :1; 
    byte MMIEN       :1;                                       /* Multi-Master IIC Interrupt Enable */
    byte MMEN        :1;                                       /* Multi-Master IIC Enable */
  } Bits;
} MMCRSTR;
extern volatile MMCRSTR _MMCR;
#define MMCR                            _MMCR.Byte
#define MMCR_MMTXAK                     _MMCR.Bits.MMTXAK
#define MMCR_MMIEN                      _MMCR.Bits.MMIEN
#define MMCR_MMEN                       _MMCR.Bits.MMEN

#define MMCR_MMTXAK_MASK                8
#define MMCR_MMIEN_MASK                 64
#define MMCR_MMEN_MASK                  128


/*** MMSR - Multi-Master IIC Status Register; 0x0000006D ***/
typedef union {
  byte Byte;
  struct {
    byte MMRXBF      :1;                                       /* Multi-Master Receive Buffer Full */
    byte MMTXBE      :1;                                       /* Multi-Master Transmit Buffer Empty */
    byte             :1; 
    byte MMRXAK      :1;                                       /* Multi-Master Receive Acknowledge */
    byte MMSRW       :1;                                       /* Multi-Master Slave Read/Write */
    byte MMATCH      :1;                                       /* Multi-Master Address Match */
    byte MMTXIF      :1;                                       /* Multi-Master Transmit Interrupt Flag */
    byte MMRXIF      :1;                                       /* Multi-Master IIC Receive Interrupt Flag */
  } Bits;
} MMSRSTR;
extern volatile MMSRSTR _MMSR;
#define MMSR                            _MMSR.Byte
#define MMSR_MMRXBF                     _MMSR.Bits.MMRXBF
#define MMSR_MMTXBE                     _MMSR.Bits.MMTXBE
#define MMSR_MMRXAK                     _MMSR.Bits.MMRXAK
#define MMSR_MMSRW                      _MMSR.Bits.MMSRW
#define MMSR_MMATCH                     _MMSR.Bits.MMATCH
#define MMSR_MMTXIF                     _MMSR.Bits.MMTXIF
#define MMSR_MMRXIF                     _MMSR.Bits.MMRXIF

#define MMSR_MMRXBF_MASK                1
#define MMSR_MMTXBE_MASK                2
#define MMSR_MMRXAK_MASK                8
#define MMSR_MMSRW_MASK                 16
#define MMSR_MMATCH_MASK                32
#define MMSR_MMTXIF_MASK                64
#define MMSR_MMRXIF_MASK                128


/*** MMDTR - Multi-Master IIC Data Transmit Register; 0x0000006E ***/
typedef union {
  byte Byte;
  struct {
    byte MMTD0       :1;                                       /* Multi-Master IIC Transmit Data Bit 0 */
    byte MMTD1       :1;                                       /* Multi-Master IIC Transmit Data Bit 1 */
    byte MMTD2       :1;                                       /* Multi-Master IIC Transmit Data Bit 2 */
    byte MMTD3       :1;                                       /* Multi-Master IIC Transmit Data Bit 3 */
    byte MMTD4       :1;                                       /* Multi-Master IIC Transmit Data Bit 4 */
    byte MMTD5       :1;                                       /* Multi-Master IIC Transmit Data Bit 5 */
    byte MMTD6       :1;                                       /* Multi-Master IIC Transmit Data Bit 6 */
    byte MMTD7       :1;                                       /* Multi-Master IIC Transmit Data Bit 7 */
  } Bits;
} MMDTRSTR;
extern volatile MMDTRSTR _MMDTR;
#define MMDTR                           _MMDTR.Byte
#define MMDTR_MMTD0                     _MMDTR.Bits.MMTD0
#define MMDTR_MMTD1                     _MMDTR.Bits.MMTD1
#define MMDTR_MMTD2                     _MMDTR.Bits.MMTD2
#define MMDTR_MMTD3                     _MMDTR.Bits.MMTD3
#define MMDTR_MMTD4                     _MMDTR.Bits.MMTD4
#define MMDTR_MMTD5                     _MMDTR.Bits.MMTD5
#define MMDTR_MMTD6                     _MMDTR.Bits.MMTD6
#define MMDTR_MMTD7                     _MMDTR.Bits.MMTD7

#define MMDTR_MMTD0_MASK                1
#define MMDTR_MMTD1_MASK                2
#define MMDTR_MMTD2_MASK                4
#define MMDTR_MMTD3_MASK                8
#define MMDTR_MMTD4_MASK                16
#define MMDTR_MMTD5_MASK                32
#define MMDTR_MMTD6_MASK                64
#define MMDTR_MMTD7_MASK                128


/*** MMDRR - Multi-Master IIC Data Receive Register; 0x0000006F ***/
typedef union {
  byte Byte;
  struct {
    byte MMRD0       :1;                                       /* Multi-Master IIC Receive Data Bit 0 */
    byte MMRD1       :1;                                       /* Multi-Master IIC Receive Data Bit 1 */
    byte MMRD2       :1;                                       /* Multi-Master IIC Receive Data Bit 2 */
    byte MMRD3       :1;                                       /* Multi-Master IIC Receive Data Bit 3 */
    byte MMRD4       :1;                                       /* Multi-Master IIC Receive Data Bit 4 */
    byte MMRD5       :1;                                       /* Multi-Master IIC Receive Data Bit 5 */
    byte MMRD6       :1;                                       /* Multi-Master IIC Receive Data Bit 6 */
    byte MMRD7       :1;                                       /* Multi-Master IIC Receive Data Bit 7 */
  } Bits;
} MMDRRSTR;
extern volatile MMDRRSTR _MMDRR;
#define MMDRR                           _MMDRR.Byte
#define MMDRR_MMRD0                     _MMDRR.Bits.MMRD0
#define MMDRR_MMRD1                     _MMDRR.Bits.MMRD1
#define MMDRR_MMRD2                     _MMDRR.Bits.MMRD2
#define MMDRR_MMRD3                     _MMDRR.Bits.MMRD3
#define MMDRR_MMRD4                     _MMDRR.Bits.MMRD4
#define MMDRR_MMRD5                     _MMDRR.Bits.MMRD5
#define MMDRR_MMRD6                     _MMDRR.Bits.MMRD6
#define MMDRR_MMRD7                     _MMDRR.Bits.MMRD7

#define MMDRR_MMRD0_MASK                1
#define MMDRR_MMRD1_MASK                2
#define MMDRR_MMRD2_MASK                4
#define MMDRR_MMRD3_MASK                8
#define MMDRR_MMRD4_MASK                16
#define MMDRR_MMRD5_MASK                32
#define MMDRR_MMRD6_MASK                64
#define MMDRR_MMRD7_MASK                128


/*** PWM0 - PWM Data Register 0; 0x00000070 ***/
typedef union {
  byte Byte;
  struct {
    byte BRM0        :1;                                       /* Binary Rate Multiplier Bit 0 */
    byte BRM1        :1;                                       /* Binary Rate Multiplier Bit 1 */
    byte BRM2        :1;                                       /* Binary Rate Multiplier Bit 2 */
    byte PWM_0       :1;                                       /* PWM Bit 0 */
    byte PWM_1       :1;                                       /* PWM Bit 1 */
    byte PWM_2       :1;                                       /* PWM Bit 2 */
    byte PWM_3       :1;                                       /* PWM Bit 3 */
    byte PWM_4       :1;                                       /* PWM Bit 4 */
  } Bits;
  struct {
    byte grpBRM  :3;
    byte grpPWM  :5;
  } MergedBits;
} PWM0STR;
extern volatile PWM0STR _PWM0;
#define PWM0                            _PWM0.Byte
#define PWM0_BRM0                       _PWM0.Bits.BRM0
#define PWM0_BRM1                       _PWM0.Bits.BRM1
#define PWM0_BRM2                       _PWM0.Bits.BRM2
#define PWM0_PWM_0                      _PWM0.Bits.PWM_0
#define PWM0_PWM_1                      _PWM0.Bits.PWM_1
#define PWM0_PWM_2                      _PWM0.Bits.PWM_2
#define PWM0_PWM_3                      _PWM0.Bits.PWM_3
#define PWM0_PWM_4                      _PWM0.Bits.PWM_4
/* PWM_ARR: Access 8 PWMx registers in an array */
#define PWM_ARR                         ((volatile byte * __far) &PWM0)
#define PWM0_BRM                        _PWM0.MergedBits.grpBRM
#define PWM0_PWM                        _PWM0.MergedBits.grpPWM

#define PWM0_BRM0_MASK                  1
#define PWM0_BRM1_MASK                  2
#define PWM0_BRM2_MASK                  4
#define PWM0_PWM_0_MASK                 8
#define PWM0_PWM_1_MASK                 16
#define PWM0_PWM_2_MASK                 32
#define PWM0_PWM_3_MASK                 64
#define PWM0_PWM_4_MASK                 128
#define PWM0_BRM_MASK                   7
#define PWM0_BRM_BITNUM                 0
#define PWM0_PWM_MASK                   248
#define PWM0_PWM_BITNUM                 3


/*** PWM1 - PWM Data Register 1; 0x00000071 ***/
typedef union {
  byte Byte;
  struct {
    byte BRM0        :1;                                       /* Binary Rate Multiplier Bit 0 */
    byte BRM1        :1;                                       /* Binary Rate Multiplier Bit 1 */
    byte BRM2        :1;                                       /* Binary Rate Multiplier Bit 2 */
    byte PWM_0       :1;                                       /* PWM Bit 0 */
    byte PWM_1       :1;                                       /* PWM Bit 1 */
    byte PWM_2       :1;                                       /* PWM Bit 2 */
    byte PWM_3       :1;                                       /* PWM Bit 3 */
    byte PWM_4       :1;                                       /* PWM Bit 4 */
  } Bits;
  struct {
    byte grpBRM  :3;
    byte grpPWM  :5;
  } MergedBits;
} PWM1STR;
extern volatile PWM1STR _PWM1;
#define PWM1                            _PWM1.Byte
#define PWM1_BRM0                       _PWM1.Bits.BRM0
#define PWM1_BRM1                       _PWM1.Bits.BRM1
#define PWM1_BRM2                       _PWM1.Bits.BRM2
#define PWM1_PWM_0                      _PWM1.Bits.PWM_0
#define PWM1_PWM_1                      _PWM1.Bits.PWM_1
#define PWM1_PWM_2                      _PWM1.Bits.PWM_2
#define PWM1_PWM_3                      _PWM1.Bits.PWM_3
#define PWM1_PWM_4                      _PWM1.Bits.PWM_4
#define PWM1_BRM                        _PWM1.MergedBits.grpBRM
#define PWM1_PWM                        _PWM1.MergedBits.grpPWM

#define PWM1_BRM0_MASK                  1
#define PWM1_BRM1_MASK                  2
#define PWM1_BRM2_MASK                  4
#define PWM1_PWM_0_MASK                 8
#define PWM1_PWM_1_MASK                 16
#define PWM1_PWM_2_MASK                 32
#define PWM1_PWM_3_MASK                 64
#define PWM1_PWM_4_MASK                 128
#define PWM1_BRM_MASK                   7
#define PWM1_BRM_BITNUM                 0
#define PWM1_PWM_MASK                   248
#define PWM1_PWM_BITNUM                 3


/*** PWM2 - PWM Data Register 2; 0x00000072 ***/
typedef union {
  byte Byte;
  struct {
    byte BRM0        :1;                                       /* Binary Rate Multiplier Bit 0 */
    byte BRM1        :1;                                       /* Binary Rate Multiplier Bit 1 */
    byte BRM2        :1;                                       /* Binary Rate Multiplier Bit 2 */
    byte PWM_0       :1;                                       /* PWM Bit 0 */
    byte PWM_1       :1;                                       /* PWM Bit 1 */
    byte PWM_2       :1;                                       /* PWM Bit 2 */
    byte PWM_3       :1;                                       /* PWM Bit 3 */
    byte PWM_4       :1;                                       /* PWM Bit 4 */
  } Bits;
  struct {
    byte grpBRM  :3;
    byte grpPWM  :5;
  } MergedBits;
} PWM2STR;
extern volatile PWM2STR _PWM2;
#define PWM2                            _PWM2.Byte
#define PWM2_BRM0                       _PWM2.Bits.BRM0
#define PWM2_BRM1                       _PWM2.Bits.BRM1
#define PWM2_BRM2                       _PWM2.Bits.BRM2
#define PWM2_PWM_0                      _PWM2.Bits.PWM_0
#define PWM2_PWM_1                      _PWM2.Bits.PWM_1
#define PWM2_PWM_2                      _PWM2.Bits.PWM_2
#define PWM2_PWM_3                      _PWM2.Bits.PWM_3
#define PWM2_PWM_4                      _PWM2.Bits.PWM_4
#define PWM2_BRM                        _PWM2.MergedBits.grpBRM
#define PWM2_PWM                        _PWM2.MergedBits.grpPWM

#define PWM2_BRM0_MASK                  1
#define PWM2_BRM1_MASK                  2
#define PWM2_BRM2_MASK                  4
#define PWM2_PWM_0_MASK                 8
#define PWM2_PWM_1_MASK                 16
#define PWM2_PWM_2_MASK                 32
#define PWM2_PWM_3_MASK                 64
#define PWM2_PWM_4_MASK                 128
#define PWM2_BRM_MASK                   7
#define PWM2_BRM_BITNUM                 0
#define PWM2_PWM_MASK                   248
#define PWM2_PWM_BITNUM                 3


/*** PWM3 - PWM Data Register 3; 0x00000073 ***/
typedef union {
  byte Byte;
  struct {
    byte BRM0        :1;                                       /* Binary Rate Multiplier Bit 0 */
    byte BRM1        :1;                                       /* Binary Rate Multiplier Bit 1 */
    byte BRM2        :1;                                       /* Binary Rate Multiplier Bit 2 */
    byte PWM_0       :1;                                       /* PWM Bit 0 */
    byte PWM_1       :1;                                       /* PWM Bit 1 */
    byte PWM_2       :1;                                       /* PWM Bit 2 */
    byte PWM_3       :1;                                       /* PWM Bit 3 */
    byte PWM_4       :1;                                       /* PWM Bit 4 */
  } Bits;
  struct {
    byte grpBRM  :3;
    byte grpPWM  :5;
  } MergedBits;
} PWM3STR;
extern volatile PWM3STR _PWM3;
#define PWM3                            _PWM3.Byte
#define PWM3_BRM0                       _PWM3.Bits.BRM0
#define PWM3_BRM1                       _PWM3.Bits.BRM1
#define PWM3_BRM2                       _PWM3.Bits.BRM2
#define PWM3_PWM_0                      _PWM3.Bits.PWM_0
#define PWM3_PWM_1                      _PWM3.Bits.PWM_1
#define PWM3_PWM_2                      _PWM3.Bits.PWM_2
#define PWM3_PWM_3                      _PWM3.Bits.PWM_3
#define PWM3_PWM_4                      _PWM3.Bits.PWM_4
#define PWM3_BRM                        _PWM3.MergedBits.grpBRM
#define PWM3_PWM                        _PWM3.MergedBits.grpPWM

#define PWM3_BRM0_MASK                  1
#define PWM3_BRM1_MASK                  2
#define PWM3_BRM2_MASK                  4
#define PWM3_PWM_0_MASK                 8
#define PWM3_PWM_1_MASK                 16
#define PWM3_PWM_2_MASK                 32
#define PWM3_PWM_3_MASK                 64
#define PWM3_PWM_4_MASK                 128
#define PWM3_BRM_MASK                   7
#define PWM3_BRM_BITNUM                 0
#define PWM3_PWM_MASK                   248
#define PWM3_PWM_BITNUM                 3


/*** PWM4 - PWM Data Register 4; 0x00000074 ***/
typedef union {
  byte Byte;
  struct {
    byte BRM0        :1;                                       /* Binary Rate Multiplier Bit 0 */
    byte BRM1        :1;                                       /* Binary Rate Multiplier Bit 1 */
    byte BRM2        :1;                                       /* Binary Rate Multiplier Bit 2 */
    byte PWM_0       :1;                                       /* PWM Bit 0 */
    byte PWM_1       :1;                                       /* PWM Bit 1 */
    byte PWM_2       :1;                                       /* PWM Bit 2 */
    byte PWM_3       :1;                                       /* PWM Bit 3 */
    byte PWM_4       :1;                                       /* PWM Bit 4 */
  } Bits;
  struct {
    byte grpBRM  :3;
    byte grpPWM  :5;
  } MergedBits;
} PWM4STR;
extern volatile PWM4STR _PWM4;
#define PWM4                            _PWM4.Byte
#define PWM4_BRM0                       _PWM4.Bits.BRM0
#define PWM4_BRM1                       _PWM4.Bits.BRM1
#define PWM4_BRM2                       _PWM4.Bits.BRM2
#define PWM4_PWM_0                      _PWM4.Bits.PWM_0
#define PWM4_PWM_1                      _PWM4.Bits.PWM_1
#define PWM4_PWM_2                      _PWM4.Bits.PWM_2
#define PWM4_PWM_3                      _PWM4.Bits.PWM_3
#define PWM4_PWM_4                      _PWM4.Bits.PWM_4
#define PWM4_BRM                        _PWM4.MergedBits.grpBRM
#define PWM4_PWM                        _PWM4.MergedBits.grpPWM

#define PWM4_BRM0_MASK                  1
#define PWM4_BRM1_MASK                  2
#define PWM4_BRM2_MASK                  4
#define PWM4_PWM_0_MASK                 8
#define PWM4_PWM_1_MASK                 16
#define PWM4_PWM_2_MASK                 32
#define PWM4_PWM_3_MASK                 64
#define PWM4_PWM_4_MASK                 128
#define PWM4_BRM_MASK                   7
#define PWM4_BRM_BITNUM                 0
#define PWM4_PWM_MASK                   248
#define PWM4_PWM_BITNUM                 3


/*** PWM5 - PWM Data Register 5; 0x00000075 ***/
typedef union {
  byte Byte;
  struct {
    byte BRM0        :1;                                       /* Binary Rate Multiplier Bit 0 */
    byte BRM1        :1;                                       /* Binary Rate Multiplier Bit 1 */
    byte BRM2        :1;                                       /* Binary Rate Multiplier Bit 2 */
    byte PWM_0       :1;                                       /* PWM Bit 0 */
    byte PWM_1       :1;                                       /* PWM Bit 1 */
    byte PWM_2       :1;                                       /* PWM Bit 2 */
    byte PWM_3       :1;                                       /* PWM Bit 3 */
    byte PWM_4       :1;                                       /* PWM Bit 4 */
  } Bits;
  struct {
    byte grpBRM  :3;
    byte grpPWM  :5;
  } MergedBits;
} PWM5STR;
extern volatile PWM5STR _PWM5;
#define PWM5                            _PWM5.Byte
#define PWM5_BRM0                       _PWM5.Bits.BRM0
#define PWM5_BRM1                       _PWM5.Bits.BRM1
#define PWM5_BRM2                       _PWM5.Bits.BRM2
#define PWM5_PWM_0                      _PWM5.Bits.PWM_0
#define PWM5_PWM_1                      _PWM5.Bits.PWM_1
#define PWM5_PWM_2                      _PWM5.Bits.PWM_2
#define PWM5_PWM_3                      _PWM5.Bits.PWM_3
#define PWM5_PWM_4                      _PWM5.Bits.PWM_4
#define PWM5_BRM                        _PWM5.MergedBits.grpBRM
#define PWM5_PWM                        _PWM5.MergedBits.grpPWM

#define PWM5_BRM0_MASK                  1
#define PWM5_BRM1_MASK                  2
#define PWM5_BRM2_MASK                  4
#define PWM5_PWM_0_MASK                 8
#define PWM5_PWM_1_MASK                 16
#define PWM5_PWM_2_MASK                 32
#define PWM5_PWM_3_MASK                 64
#define PWM5_PWM_4_MASK                 128
#define PWM5_BRM_MASK                   7
#define PWM5_BRM_BITNUM                 0
#define PWM5_PWM_MASK                   248
#define PWM5_PWM_BITNUM                 3


/*** PWM6 - PWM Data Register 6; 0x00000076 ***/
typedef union {
  byte Byte;
  struct {
    byte BRM0        :1;                                       /* Binary Rate Multiplier Bit 0 */
    byte BRM1        :1;                                       /* Binary Rate Multiplier Bit 1 */
    byte BRM2        :1;                                       /* Binary Rate Multiplier Bit 2 */
    byte PWM_0       :1;                                       /* PWM Bit 0 */
    byte PWM_1       :1;                                       /* PWM Bit 1 */
    byte PWM_2       :1;                                       /* PWM Bit 2 */
    byte PWM_3       :1;                                       /* PWM Bit 3 */
    byte PWM_4       :1;                                       /* PWM Bit 4 */
  } Bits;
  struct {
    byte grpBRM  :3;
    byte grpPWM  :5;
  } MergedBits;
} PWM6STR;
extern volatile PWM6STR _PWM6;
#define PWM6                            _PWM6.Byte
#define PWM6_BRM0                       _PWM6.Bits.BRM0
#define PWM6_BRM1                       _PWM6.Bits.BRM1
#define PWM6_BRM2                       _PWM6.Bits.BRM2
#define PWM6_PWM_0                      _PWM6.Bits.PWM_0
#define PWM6_PWM_1                      _PWM6.Bits.PWM_1
#define PWM6_PWM_2                      _PWM6.Bits.PWM_2
#define PWM6_PWM_3                      _PWM6.Bits.PWM_3
#define PWM6_PWM_4                      _PWM6.Bits.PWM_4
#define PWM6_BRM                        _PWM6.MergedBits.grpBRM
#define PWM6_PWM                        _PWM6.MergedBits.grpPWM

#define PWM6_BRM0_MASK                  1
#define PWM6_BRM1_MASK                  2
#define PWM6_BRM2_MASK                  4
#define PWM6_PWM_0_MASK                 8
#define PWM6_PWM_1_MASK                 16
#define PWM6_PWM_2_MASK                 32
#define PWM6_PWM_3_MASK                 64
#define PWM6_PWM_4_MASK                 128
#define PWM6_BRM_MASK                   7
#define PWM6_BRM_BITNUM                 0
#define PWM6_PWM_MASK                   248
#define PWM6_PWM_BITNUM                 3


/*** PWM7 - PWM Data Register 7; 0x00000077 ***/
typedef union {
  byte Byte;
  struct {
    byte BRM0        :1;                                       /* Binary Rate Multiplier Bit 0 */
    byte BRM1        :1;                                       /* Binary Rate Multiplier Bit 1 */
    byte BRM2        :1;                                       /* Binary Rate Multiplier Bit 2 */
    byte PWM_0       :1;                                       /* PWM Bit 0 */
    byte PWM_1       :1;                                       /* PWM Bit 1 */
    byte PWM_2       :1;                                       /* PWM Bit 2 */
    byte PWM_3       :1;                                       /* PWM Bit 3 */
    byte PWM_4       :1;                                       /* PWM Bit 4 */
  } Bits;
  struct {
    byte grpBRM  :3;
    byte grpPWM  :5;
  } MergedBits;
} PWM7STR;
extern volatile PWM7STR _PWM7;
#define PWM7                            _PWM7.Byte
#define PWM7_BRM0                       _PWM7.Bits.BRM0
#define PWM7_BRM1                       _PWM7.Bits.BRM1
#define PWM7_BRM2                       _PWM7.Bits.BRM2
#define PWM7_PWM_0                      _PWM7.Bits.PWM_0
#define PWM7_PWM_1                      _PWM7.Bits.PWM_1
#define PWM7_PWM_2                      _PWM7.Bits.PWM_2
#define PWM7_PWM_3                      _PWM7.Bits.PWM_3
#define PWM7_PWM_4                      _PWM7.Bits.PWM_4
#define PWM7_BRM                        _PWM7.MergedBits.grpBRM
#define PWM7_PWM                        _PWM7.MergedBits.grpPWM

#define PWM7_BRM0_MASK                  1
#define PWM7_BRM1_MASK                  2
#define PWM7_BRM2_MASK                  4
#define PWM7_PWM_0_MASK                 8
#define PWM7_PWM_1_MASK                 16
#define PWM7_PWM_2_MASK                 32
#define PWM7_PWM_3_MASK                 64
#define PWM7_PWM_4_MASK                 128
#define PWM7_BRM_MASK                   7
#define PWM7_BRM_BITNUM                 0
#define PWM7_PWM_MASK                   248
#define PWM7_PWM_BITNUM                 3


/*** PWMCR - PWM Control Register; 0x00000078 ***/
typedef union {
  byte Byte;
  struct {
    byte PWM0E       :1;                                       /* PWM 0 Output Enable */
    byte PWM1E       :1;                                       /* PWM 1 Output Enable */
    byte PWM2E       :1;                                       /* PWM 2 Output Enable */
    byte PWM3E       :1;                                       /* PWM 3 Output Enable */
    byte PWM4E       :1;                                       /* PWM 4 Output Enable */
    byte PWM5E       :1;                                       /* PWM 5 Output Enable */
    byte PWM6E       :1;                                       /* PWM 6 Output Enable */
    byte PWM7E       :1;                                       /* PWM 7 Output Enable */
  } Bits;
} PWMCRSTR;
extern volatile PWMCRSTR _PWMCR;
#define PWMCR                           _PWMCR.Byte
#define PWMCR_PWM0E                     _PWMCR.Bits.PWM0E
#define PWMCR_PWM1E                     _PWMCR.Bits.PWM1E
#define PWMCR_PWM2E                     _PWMCR.Bits.PWM2E
#define PWMCR_PWM3E                     _PWMCR.Bits.PWM3E
#define PWMCR_PWM4E                     _PWMCR.Bits.PWM4E
#define PWMCR_PWM5E                     _PWMCR.Bits.PWM5E
#define PWMCR_PWM6E                     _PWMCR.Bits.PWM6E
#define PWMCR_PWM7E                     _PWMCR.Bits.PWM7E

#define PWMCR_PWM0E_MASK                1
#define PWMCR_PWM1E_MASK                2
#define PWMCR_PWM2E_MASK                4
#define PWMCR_PWM3E_MASK                8
#define PWMCR_PWM4E_MASK                16
#define PWMCR_PWM5E_MASK                32
#define PWMCR_PWM6E_MASK                64
#define PWMCR_PWM7E_MASK                128


/*** SBSR - SIM Break Status Register; 0x0000FE00 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte SBSW        :1;                                       /* SIM Break Stop/Wait */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SBSRSTR;
extern volatile SBSRSTR _SBSR;
#define SBSR                            _SBSR.Byte
#define SBSR_SBSW                       _SBSR.Bits.SBSW

#define SBSR_SBSW_MASK                  2


/*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte LVI         :1;                                       /* Low-Voltage Inhibit Reset Bit */
    byte             :1; 
    byte ILAD        :1;                                       /* Illegal Address Reset Bit */
    byte ILOP        :1;                                       /* Illegal Opcode Reset Bit */
    byte COP         :1;                                       /* Computer Operating Properly Reset Bit */
    byte PIN         :1;                                       /* External Reset Bit */
    byte POR         :1;                                       /* Power-On Reset Bit */
  } Bits;
} SRSRSTR;
extern volatile SRSRSTR _SRSR;
#define SRSR                            _SRSR.Byte
#define SRSR_LVI                        _SRSR.Bits.LVI
#define SRSR_ILAD                       _SRSR.Bits.ILAD
#define SRSR_ILOP                       _SRSR.Bits.ILOP
#define SRSR_COP                        _SRSR.Bits.COP
#define SRSR_PIN                        _SRSR.Bits.PIN
#define SRSR_POR                        _SRSR.Bits.POR

#define SRSR_LVI_MASK                   2
#define SRSR_ILAD_MASK                  8
#define SRSR_ILOP_MASK                  16
#define SRSR_COP_MASK                   32
#define SRSR_PIN_MASK                   64
#define SRSR_POR_MASK                   128


/*** SBFCR - SIM Break Flag Control Register; 0x0000FE03 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BCFE        :1;                                       /* Break Clear Flag Enable Bit */
  } Bits;
} SBFCRSTR;
extern volatile SBFCRSTR _SBFCR;
#define SBFCR                           _SBFCR.Byte
#define SBFCR_BCFE                      _SBFCR.Bits.BCFE

#define SBFCR_BCFE_MASK                 128


/*** INT1 - Interrupt Status Register 1; 0x0000FE04 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte IF1         :1;                                       /* Interrupt Flag 1 */
    byte IF2         :1;                                       /* Interrupt Flag 2 */
    byte IF3         :1;                                       /* Interrupt Flag 3 */
    byte IF4         :1;                                       /* Interrupt Flag 4 */
    byte IF5         :1;                                       /* Interrupt Flag 5 */
    byte IF6         :1;                                       /* Interrupt Flag 6 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpIF_1 :6;
  } MergedBits;
} INT1STR;
extern volatile INT1STR _INT1;
#define INT1                            _INT1.Byte
#define INT1_IF1                        _INT1.Bits.IF1
#define INT1_IF2                        _INT1.Bits.IF2
#define INT1_IF3                        _INT1.Bits.IF3
#define INT1_IF4                        _INT1.Bits.IF4
#define INT1_IF5                        _INT1.Bits.IF5
#define INT1_IF6                        _INT1.Bits.IF6
#define INT1_IF_1                       _INT1.MergedBits.grpIF_1
#define INT1_IF                         INT1_IF_1

#define INT1_IF1_MASK                   4
#define INT1_IF2_MASK                   8
#define INT1_IF3_MASK                   16
#define INT1_IF4_MASK                   32
#define INT1_IF5_MASK                   64
#define INT1_IF6_MASK                   128
#define INT1_IF_1_MASK                  252
#define INT1_IF_1_BITNUM                2


/*** INT2 - Interrupt Status Register 2; 0x0000FE05 ***/
typedef union {
  byte Byte;
  struct {
    byte IF7         :1;                                       /* Interrupt Flag 7 */
    byte IF8         :1;                                       /* Interrupt Flag 8 */
    byte IF9         :1;                                       /* Interrupt Flag 9 */
    byte IF10        :1;                                       /* Interrupt Flag 10 */
    byte IF11        :1;                                       /* Interrupt Flag 11 */
    byte IF12        :1;                                       /* Interrupt Flag 12 */
    byte IF13        :1;                                       /* Interrupt Flag 13 */
    byte IF14        :1;                                       /* Interrupt Flag 14 */
  } Bits;
} INT2STR;
extern volatile INT2STR _INT2;
#define INT2                            _INT2.Byte
#define INT2_IF7                        _INT2.Bits.IF7
#define INT2_IF8                        _INT2.Bits.IF8
#define INT2_IF9                        _INT2.Bits.IF9
#define INT2_IF10                       _INT2.Bits.IF10
#define INT2_IF11                       _INT2.Bits.IF11
#define INT2_IF12                       _INT2.Bits.IF12
#define INT2_IF13                       _INT2.Bits.IF13
#define INT2_IF14                       _INT2.Bits.IF14

#define INT2_IF7_MASK                   1
#define INT2_IF8_MASK                   2
#define INT2_IF9_MASK                   4
#define INT2_IF10_MASK                  8
#define INT2_IF11_MASK                  16
#define INT2_IF12_MASK                  32
#define INT2_IF13_MASK                  64
#define INT2_IF14_MASK                  128


/*** FLCR - 47,616 Bytes FLASH Control Register; 0x0000FE07 ***/
typedef union {
  byte Byte;
  struct {
    byte PGM         :1;                                       /* Program Control Bit */
    byte ERASE       :1;                                       /* Erase Control Bit */
    byte MASS        :1;                                       /* Mass Erase Control Bit */
    byte HVEN        :1;                                       /* High-Voltage Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} FLCRSTR;
extern volatile FLCRSTR _FLCR;
#define FLCR                            _FLCR.Byte
#define FLCR_PGM                        _FLCR.Bits.PGM
#define FLCR_ERASE                      _FLCR.Bits.ERASE
#define FLCR_MASS                       _FLCR.Bits.MASS
#define FLCR_HVEN                       _FLCR.Bits.HVEN

#define FLCR_PGM_MASK                   1
#define FLCR_ERASE_MASK                 2
#define FLCR_MASS_MASK                  4
#define FLCR_HVEN_MASK                  8


/*** FLBPR - FLASH Block Protect Register; 0x0000FE08 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte BPR1        :1;                                       /* Flash Block Protect Bit 1 */
    byte BPR2        :1;                                       /* Flash Block Protect Bit 2 */
    byte BPR3        :1;                                       /* Flash Block Protect Bit 3 */
    byte BPR4        :1;                                       /* Flash Block Protect Bit 4 */
    byte BPR5        :1;                                       /* Flash Block Protect Bit 5 */
    byte BPR6        :1;                                       /* Flash Block Protect Bit 6 */
    byte BPR7        :1;                                       /* Flash Block Protect Bit 7 */
  } Bits;
  struct {
    byte         :1;
    byte grpBPR_1 :7;
  } MergedBits;
} FLBPRSTR;
extern volatile FLBPRSTR _FLBPR;
#define FLBPR                           _FLBPR.Byte
#define FLBPR_BPR1                      _FLBPR.Bits.BPR1
#define FLBPR_BPR2                      _FLBPR.Bits.BPR2
#define FLBPR_BPR3                      _FLBPR.Bits.BPR3
#define FLBPR_BPR4                      _FLBPR.Bits.BPR4
#define FLBPR_BPR5                      _FLBPR.Bits.BPR5
#define FLBPR_BPR6                      _FLBPR.Bits.BPR6
#define FLBPR_BPR7                      _FLBPR.Bits.BPR7
#define FLBPR_BPR_1                     _FLBPR.MergedBits.grpBPR_1
#define FLBPR_BPR                       FLBPR_BPR_1

#define FLBPR_BPR1_MASK                 2
#define FLBPR_BPR2_MASK                 4
#define FLBPR_BPR3_MASK                 8
#define FLBPR_BPR4_MASK                 16
#define FLBPR_BPR5_MASK                 32
#define FLBPR_BPR6_MASK                 64
#define FLBPR_BPR7_MASK                 128
#define FLBPR_BPR_1_MASK                254
#define FLBPR_BPR_1_BITNUM              1


/*** FLCR1 - 13k-Bytes FLASH Control Register; 0x0000FE0A ***/
typedef union {
  byte Byte;
  struct {
    byte PGM1        :1;                                       /* Program Control Bit */
    byte ERASE1      :1;                                       /* Erase Control Bit */
    byte MASS1       :1;                                       /* Mass Erase Control Bit */
    byte HVEN1       :1;                                       /* High-Voltage Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} FLCR1STR;
extern volatile FLCR1STR _FLCR1;
#define FLCR1                           _FLCR1.Byte
#define FLCR1_PGM1                      _FLCR1.Bits.PGM1
#define FLCR1_ERASE1                    _FLCR1.Bits.ERASE1
#define FLCR1_MASS1                     _FLCR1.Bits.MASS1
#define FLCR1_HVEN1                     _FLCR1.Bits.HVEN1

#define FLCR1_PGM1_MASK                 1
#define FLCR1_ERASE1_MASK               2
#define FLCR1_MASS1_MASK                4
#define FLCR1_HVEN1_MASK                8


/*** FLBPR1 - 13k-Bytes FLASH Block Protect Register; 0x0000FE0B ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte BPR11       :1;                                       /* Block Protect Register Bit 11 */
    byte BPR12       :1;                                       /* Block Protect Register Bit 12 */
    byte BPR13       :1;                                       /* Block Protect Register Bit 13 */
    byte BPR14       :1;                                       /* Block Protect Register Bit 14 */
    byte BPR15       :1;                                       /* Block Protect Register Bit 15 */
    byte BPR16       :1;                                       /* Block Protect Register Bit 16 */
    byte BPR17       :1;                                       /* Block Protect Register Bit 17 */
  } Bits;
  struct {
    byte         :1;
    byte grpBPR_11 :7;
  } MergedBits;
} FLBPR1STR;
extern volatile FLBPR1STR _FLBPR1;
#define FLBPR1                          _FLBPR1.Byte
#define FLBPR1_BPR11                    _FLBPR1.Bits.BPR11
#define FLBPR1_BPR12                    _FLBPR1.Bits.BPR12
#define FLBPR1_BPR13                    _FLBPR1.Bits.BPR13
#define FLBPR1_BPR14                    _FLBPR1.Bits.BPR14
#define FLBPR1_BPR15                    _FLBPR1.Bits.BPR15
#define FLBPR1_BPR16                    _FLBPR1.Bits.BPR16
#define FLBPR1_BPR17                    _FLBPR1.Bits.BPR17
#define FLBPR1_BPR_11                   _FLBPR1.MergedBits.grpBPR_11
#define FLBPR1_BPR                      FLBPR1_BPR_11

#define FLBPR1_BPR11_MASK               2
#define FLBPR1_BPR12_MASK               4
#define FLBPR1_BPR13_MASK               8
#define FLBPR1_BPR14_MASK               16
#define FLBPR1_BPR15_MASK               32
#define FLBPR1_BPR16_MASK               64
#define FLBPR1_BPR17_MASK               128
#define FLBPR1_BPR_11_MASK              254
#define FLBPR1_BPR_11_BITNUM            1


/*** BRK - Break Address Register; 0x0000FE0C ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** BRKH - Break Address Register; 0x0000FE0C ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Break Address Register Bit */
        byte BIT9        :1;                                       /* Break Address Register Bit */
        byte BIT10       :1;                                       /* Break Address Register Bit */
        byte BIT11       :1;                                       /* Break Address Register Bit */
        byte BIT12       :1;                                       /* Break Address Register Bit */
        byte BIT13       :1;                                       /* Break Address Register Bit */
        byte BIT14       :1;                                       /* Break Address Register Bit */
        byte BIT15       :1;                                       /* Break Address Register Bit */
      } Bits;
    } BRKHSTR;
    #define BRKH                        _BRK.Overlap_STR.BRKHSTR.Byte
    #define BRKH_BIT8                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT8
    #define BRKH_BIT9                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT9
    #define BRKH_BIT10                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT10
    #define BRKH_BIT11                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT11
    #define BRKH_BIT12                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT12
    #define BRKH_BIT13                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT13
    #define BRKH_BIT14                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT14
    #define BRKH_BIT15                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT15
    
    #define BRKH_BIT8_MASK              1
    #define BRKH_BIT9_MASK              2
    #define BRKH_BIT10_MASK             4
    #define BRKH_BIT11_MASK             8
    #define BRKH_BIT12_MASK             16
    #define BRKH_BIT13_MASK             32
    #define BRKH_BIT14_MASK             64
    #define BRKH_BIT15_MASK             128
    

    /*** BRKL - Break Address Register; 0x0000FE0D ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Break Address Register Bit */
        byte BIT1        :1;                                       /* Break Address Register Bit */
        byte BIT2        :1;                                       /* Break Address Register Bit */
        byte BIT3        :1;                                       /* Break Address Register Bit */
        byte BIT4        :1;                                       /* Break Address Register Bit */
        byte BIT5        :1;                                       /* Break Address Register Bit */
        byte BIT6        :1;                                       /* Break Address Register Bit */
        byte BIT7        :1;                                       /* Break Address Register Bit */
      } Bits;
    } BRKLSTR;
    #define BRKL                        _BRK.Overlap_STR.BRKLSTR.Byte
    #define BRKL_BIT0                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT0
    #define BRKL_BIT1                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT1
    #define BRKL_BIT2                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT2
    #define BRKL_BIT3                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT3
    #define BRKL_BIT4                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT4
    #define BRKL_BIT5                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT5
    #define BRKL_BIT6                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT6
    #define BRKL_BIT7                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT7
    
    #define BRKL_BIT0_MASK              1
    #define BRKL_BIT1_MASK              2
    #define BRKL_BIT2_MASK              4
    #define BRKL_BIT3_MASK              8
    #define BRKL_BIT4_MASK              16
    #define BRKL_BIT5_MASK              32
    #define BRKL_BIT6_MASK              64
    #define BRKL_BIT7_MASK              128
    
  } Overlap_STR;

} BRKSTR;
extern volatile BRKSTR _BRK;
#define BRK                             _BRK.Word


/*** BRKSCR - Break Status and Control Register; 0x0000FE0E ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BRKA        :1;                                       /* Break Active Bit */
    byte BRKE        :1;                                       /* Break Enable Bit */
  } Bits;
} BRKSCRSTR;
extern volatile BRKSCRSTR _BRKSCR;
#define BRKSCR                          _BRKSCR.Byte
#define BRKSCR_BRKA                     _BRKSCR.Bits.BRKA
#define BRKSCR_BRKE                     _BRKSCR.Bits.BRKE

#define BRKSCR_BRKA_MASK                64
#define BRKSCR_BRKE_MASK                128


/*** COPCTL - COP Control Register; 0x0000FFFF ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Bit 0 */
    byte BIT1        :1;                                       /* Bit 1 */
    byte BIT2        :1;                                       /* Bit 2 */
    byte BIT3        :1;                                       /* Bit 3 */
    byte BIT4        :1;                                       /* Bit 4 */
    byte BIT5        :1;                                       /* Bit 5 */
    byte BIT6        :1;                                       /* Bit 6 */
    byte BIT7        :1;                                       /* Bit 7 */
  } Bits;
} COPCTLSTR;
extern volatile COPCTLSTR _COPCTL;
#define COPCTL                          _COPCTL.Byte
#define COPCTL_BIT0                     _COPCTL.Bits.BIT0
#define COPCTL_BIT1                     _COPCTL.Bits.BIT1
#define COPCTL_BIT2                     _COPCTL.Bits.BIT2
#define COPCTL_BIT3                     _COPCTL.Bits.BIT3
#define COPCTL_BIT4                     _COPCTL.Bits.BIT4
#define COPCTL_BIT5                     _COPCTL.Bits.BIT5
#define COPCTL_BIT6                     _COPCTL.Bits.BIT6
#define COPCTL_BIT7                     _COPCTL.Bits.BIT7

#define COPCTL_BIT0_MASK                1
#define COPCTL_BIT1_MASK                2
#define COPCTL_BIT2_MASK                4
#define COPCTL_BIT3_MASK                8
#define COPCTL_BIT4_MASK                16
#define COPCTL_BIT5_MASK                32
#define COPCTL_BIT6_MASK                64
#define COPCTL_BIT7_MASK                128



/***********************************************/
/**   D E P R E C I A T E D   S Y M B O L S   **/
/***********************************************/
/* ---------------------------------------------------------------------------------------------------
Exceptions in bit names of timer status and control registers
due to backward compatibility with previous releases  */
#define TSC0_CHxMAX _TSC0.Bits.CH0MAX
#define TSC0_TOVx _TSC0.Bits.TOV0
#define TSC0_ELSxA _TSC0.Bits.ELS0A
#define TSC0_ELSxB _TSC0.Bits.ELS0B
#define TSC0_MSxA _TSC0.Bits.MS0A
#define TSC0_MSxB _TSC0.Bits.MS0B
#define TSC0_CHxIE _TSC0.Bits.CH0IE
#define TSC0_CHxF _TSC0.Bits.CH0F

#define TSC1_CHxMAX _TSC1.Bits.CH1MAX
#define TSC1_TOVx _TSC1.Bits.TOV1
#define TSC1_ELSxA _TSC1.Bits.ELS1A
#define TSC1_ELSxB _TSC1.Bits.ELS1B
#define TSC1_MSxA _TSC1.Bits.MS1A
#define TSC1_CHxIE _TSC1.Bits.CH1IE
#define TSC1_CHxF _TSC1.Bits.CH1F

/* --------------------------------------------------------------------------- */
/* The following symbols were removed, because they were invalid or irrelevant */
/* --------------------------------------------------------------------------- */


/* **** 11.9.2009 12:42:41 */

#define TCH_ARR                          This_symb_has_been_depreciated
#endif
