/* Based on CPU DB MC68HC908RF2, version 2.87.075 (RegistersPrg V2.30) */
/*
** ###################################################################
**     Filename  : mc68hc908rf2.h
**     Processor : MC68HC908RF2CFA
**     FileFormat: V2.30
**     DataSheet : MC68HC908RF2/D Rev. 4 5/2004
**     Compiler  : CodeWarrior compiler
**     Date/Time : 11.9.2009, 14:10
**     Abstract  :
**         This header implements the mapping of I/O devices.
**
**     Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved.
**     
**     http      : www.freescale.com
**     mail      : support@freescale.com
**
**     CPU Registers Revisions:
**               - none
**
**     File-Format-Revisions:
**      - 14.11.2005, V2.00 :
**               - Deprecated symbols added for backward compatibility (section at the end of this file)
**      - 15.11.2005, V2.01 :
**               - Changes have not affected this file (because they are related to another family)
**      - 17.12.2005, V2.02 :
**               - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778
**      - 16.01.2006, V2.03 :
**               - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920.
**               - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const")
**      - 08.03.2006, V2.04 :
**               - Support for bit(s) names duplicated with any register name in .h header files
**      - 24.03.2006, V2.05 :
**               - Changes have not affected this file (because they are related to another family)
**      - 26.04.2006, V2.06 :
**               - Absolute assembly supported (depreciated symbols are not defined)
**      - 27.04.2006, V2.07 :
**               - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA).
**      - 07.06.2006, V2.08 :
**               - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM.
**      - 03.07.2006, V2.09 :
**               - Flash commands constants supported
**      - 27.10.2006, V2.10 :
**               - __RESET_WATCHDOG improved formating and re-definition
**      - 23.11.2006, V2.11 :
**               - Changes have not affected this file (because they are related to another family)
**      - 22.01.2007, V2.12 :
**               - Changes have not affected this file (because they are related to another family)
**      - 01.03.2007, V2.13 :
**               - Flash commands constants values converted to HEX format
**      - 02.03.2007, V2.14 :
**               - Interrupt vector numbers added into .H, see VectorNumber_*
**      - 26.03.2007, V2.15 :
**               - Changes have not affected this file (because they are related to another family)
**      - 10.05.2007, V2.16 :
**               - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ)
**      - 05.06.2007, V2.17 :
**               - Changes have not affected this file (because they are related to another family)
**      - 19.07.2007, V2.18 :
**               - Improved number of blanked lines inside register structures
**      - 06.08.2007, V2.19 :
**               - CPUDB revisions generated ahead of the file-format revisions.
**      - 11.09.2007, V2.20 :
**               - Added comment about initialization of unbonded pins.
**      - 02.01.2008, V2.21 :
**               - Changes have not affected this file (because they are related to another family)
**      - 13.02.2008, V2.22 :
**               - Changes have not affected this file (because they are related to another family)
**      - 20.02.2008, V2.23 :
**               - Changes have not affected this file (because they are related to another family)
**      - 03.07.2008, V2.24 :
**               - Added support for bits with name starting with number (like "1HZ")
**      - 28.11.2008, V2.25 :
**               - StandBy RAM array declaration for ANSI-C added
**      - 1.12.2008, V2.26 :
**               - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map.
**      - 17.3.2009, V2.27 :
**               - Merged bit-group is not generated, if the name matches with another bit name in the register
**      - 6.4.2009, V2.28 :
**               - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB
**      - 3.8.2009, V2.29 :
**               - If there is just one bits group matching register name, single bits are not generated
**      - 10.9.2009, V2.30 :
**               - Fixed generation of registers arrays.
**
**     Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific
**     derivative device. To avoid extra current drain from floating input pins, the user’s reset
**     initialization routine in the application program must either enable on-chip pull-up devices
**     or change the direction of unconnected pins to outputs so the pins do not float.
** ###################################################################
*/

#ifndef _MC68HC908RF2_H
#define _MC68HC908RF2_H

/* Types definition */
typedef unsigned char byte;
typedef unsigned int word;
typedef unsigned long dword;
typedef unsigned long dlong[2];

/* Watchdog reset macro */
#ifndef __RESET_WATCHDOG
#ifdef _lint
  #define __RESET_WATCHDOG()  /* empty */
#else
  #define __RESET_WATCHDOG() {asm sta COPCTL;}
#endif
#endif /* __RESET_WATCHDOG */

#define REG_BASE 0x0000                /* Base address for the I/O register block */


#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */

/**************** interrupt vector numbers ****************/
#define VectorNumber_ICG                6
#define VectorNumber_TIMOvr             5
#define VectorNumber_TIMCH1             4
#define VectorNumber_TIMCH0             3
#define VectorNumber_KBI_IRQ1           2
#define VectorNumber_SWI                1
#define VectorNumber_RESET              0

/**************** interrupt vector table ****************/
#define INT_ICG                         0x0000FFF2
#define INT_TIMOvr                      0x0000FFF4
#define INT_TIMCH1                      0x0000FFF6
#define INT_TIMCH0                      0x0000FFF8
#define INT_KBI_IRQ1                    0x0000FFFA
#define INT_SWI                         0x0000FFFC
#define INT_RESET                       0x0000FFFE

/**************** registers I/O map ****************/

/*** PTA - Port A Data Register; 0x00000000 ***/
typedef union {
  byte Byte;
  struct {
    byte PTA0        :1;                                       /* Port A Data Bit 0 */
    byte PTA1        :1;                                       /* Port A Data Bit 1 */
    byte PTA2        :1;                                       /* Port A Data Bit 2 */
    byte PTA3        :1;                                       /* Port A Data Bit 3 */
    byte PTA4        :1;                                       /* Port A Data Bit 4 */
    byte PTA5        :1;                                       /* Port A Data Bit 5 */
    byte PTA6        :1;                                       /* Port A Data Bit 6 */
    byte PTA7        :1;                                       /* Port A Data Bit 7 */
  } Bits;
} PTASTR;
extern volatile PTASTR _PTA;
#define PTA                             _PTA.Byte
#define PTA_PTA0                        _PTA.Bits.PTA0
#define PTA_PTA1                        _PTA.Bits.PTA1
#define PTA_PTA2                        _PTA.Bits.PTA2
#define PTA_PTA3                        _PTA.Bits.PTA3
#define PTA_PTA4                        _PTA.Bits.PTA4
#define PTA_PTA5                        _PTA.Bits.PTA5
#define PTA_PTA6                        _PTA.Bits.PTA6
#define PTA_PTA7                        _PTA.Bits.PTA7

#define PTA_PTA0_MASK                   1
#define PTA_PTA1_MASK                   2
#define PTA_PTA2_MASK                   4
#define PTA_PTA3_MASK                   8
#define PTA_PTA4_MASK                   16
#define PTA_PTA5_MASK                   32
#define PTA_PTA6_MASK                   64
#define PTA_PTA7_MASK                   128


/*** PTB - Port B Data Register; 0x00000001 ***/
typedef union {
  byte Byte;
  struct {
    byte PTB0        :1;                                       /* Port B Data Bit 0 */
    byte PTB1        :1;                                       /* Port B Data Bit 1 */
    byte PTB2        :1;                                       /* Port B Data Bit 2 */
    byte PTB3        :1;                                       /* Port B Data Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpPTB  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} PTBSTR;
extern volatile PTBSTR _PTB;
#define PTB                             _PTB.Byte
#define PTB_PTB0                        _PTB.Bits.PTB0
#define PTB_PTB1                        _PTB.Bits.PTB1
#define PTB_PTB2                        _PTB.Bits.PTB2
#define PTB_PTB3                        _PTB.Bits.PTB3
#define PTB_PTB                         _PTB.MergedBits.grpPTB

#define PTB_PTB0_MASK                   1
#define PTB_PTB1_MASK                   2
#define PTB_PTB2_MASK                   4
#define PTB_PTB3_MASK                   8
#define PTB_PTB_MASK                    15
#define PTB_PTB_BITNUM                  0


/*** DDRA - Data Direction Register A; 0x00000004 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRA0       :1;                                       /* Data Direction Register A Bit 0 */
    byte DDRA1       :1;                                       /* Data Direction Register A Bit 1 */
    byte DDRA2       :1;                                       /* Data Direction Register A Bit 2 */
    byte DDRA3       :1;                                       /* Data Direction Register A Bit 3 */
    byte DDRA4       :1;                                       /* Data Direction Register A Bit 4 */
    byte DDRA5       :1;                                       /* Data Direction Register A Bit 5 */
    byte DDRA6       :1;                                       /* Data Direction Register A Bit 6 */
    byte DDRA7       :1;                                       /* Data Direction Register A Bit 7 */
  } Bits;
} DDRASTR;
extern volatile DDRASTR _DDRA;
#define DDRA                            _DDRA.Byte
#define DDRA_DDRA0                      _DDRA.Bits.DDRA0
#define DDRA_DDRA1                      _DDRA.Bits.DDRA1
#define DDRA_DDRA2                      _DDRA.Bits.DDRA2
#define DDRA_DDRA3                      _DDRA.Bits.DDRA3
#define DDRA_DDRA4                      _DDRA.Bits.DDRA4
#define DDRA_DDRA5                      _DDRA.Bits.DDRA5
#define DDRA_DDRA6                      _DDRA.Bits.DDRA6
#define DDRA_DDRA7                      _DDRA.Bits.DDRA7

#define DDRA_DDRA0_MASK                 1
#define DDRA_DDRA1_MASK                 2
#define DDRA_DDRA2_MASK                 4
#define DDRA_DDRA3_MASK                 8
#define DDRA_DDRA4_MASK                 16
#define DDRA_DDRA5_MASK                 32
#define DDRA_DDRA6_MASK                 64
#define DDRA_DDRA7_MASK                 128


/*** DDRB - Data Direction Register B; 0x00000005 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRB0       :1;                                       /* Data Direction Register B Bit 0 */
    byte DDRB1       :1;                                       /* Data Direction Register B Bit 1 */
    byte DDRB2       :1;                                       /* Data Direction Register B Bit 2 */
    byte DDRB3       :1;                                       /* Data Direction Register B Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte MCLKEN      :1;                                       /* MCLK Enable Bit */
  } Bits;
  struct {
    byte grpDDRB :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DDRBSTR;
extern volatile DDRBSTR _DDRB;
#define DDRB                            _DDRB.Byte
#define DDRB_DDRB0                      _DDRB.Bits.DDRB0
#define DDRB_DDRB1                      _DDRB.Bits.DDRB1
#define DDRB_DDRB2                      _DDRB.Bits.DDRB2
#define DDRB_DDRB3                      _DDRB.Bits.DDRB3
#define DDRB_MCLKEN                     _DDRB.Bits.MCLKEN
#define DDRB_DDRB                       _DDRB.MergedBits.grpDDRB

#define DDRB_DDRB0_MASK                 1
#define DDRB_DDRB1_MASK                 2
#define DDRB_DDRB2_MASK                 4
#define DDRB_DDRB3_MASK                 8
#define DDRB_MCLKEN_MASK                128
#define DDRB_DDRB_MASK                  15
#define DDRB_DDRB_BITNUM                0


/*** INTKBSCR - Keyboard Status and Control Register; 0x0000001A ***/
typedef union {
  byte Byte;
  struct {
    byte MODEK       :1;                                       /* Keyboard Triggering Sensitivity Bit */
    byte IMASKK      :1;                                       /* Keyboard Interrupt Mask Bit */
    byte ACKK        :1;                                       /* Keyboard Acknowledge Bit */
    byte KEYF        :1;                                       /* Keyboard Flag Bit */
    byte MODEI       :1;                                       /* IRQ Edge/Level Select Bit */
    byte IMASKI      :1;                                       /* IRQ Interrupt Mask Bit */
    byte ACKI        :1;                                       /* IRQ Interrupt Request Acknowledge Bit */
    byte IRQ1F       :1;                                       /* IRQ Flag Bit */
  } Bits;
} INTKBSCRSTR;
extern volatile INTKBSCRSTR _INTKBSCR;
#define INTKBSCR                        _INTKBSCR.Byte
#define INTKBSCR_MODEK                  _INTKBSCR.Bits.MODEK
#define INTKBSCR_IMASKK                 _INTKBSCR.Bits.IMASKK
#define INTKBSCR_ACKK                   _INTKBSCR.Bits.ACKK
#define INTKBSCR_KEYF                   _INTKBSCR.Bits.KEYF
#define INTKBSCR_MODEI                  _INTKBSCR.Bits.MODEI
#define INTKBSCR_IMASKI                 _INTKBSCR.Bits.IMASKI
#define INTKBSCR_ACKI                   _INTKBSCR.Bits.ACKI
#define INTKBSCR_IRQ1F                  _INTKBSCR.Bits.IRQ1F

#define INTKBSCR_MODEK_MASK             1
#define INTKBSCR_IMASKK_MASK            2
#define INTKBSCR_ACKK_MASK              4
#define INTKBSCR_KEYF_MASK              8
#define INTKBSCR_MODEI_MASK             16
#define INTKBSCR_IMASKI_MASK            32
#define INTKBSCR_ACKI_MASK              64
#define INTKBSCR_IRQ1F_MASK             128


/*** INTKBIER - Keyboard Interrrupt Enable Register KBIER; 0x0000001B ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte KBIE1       :1;                                       /* Keyboard Interrupt Enable Bit 1 */
    byte KBIE2       :1;                                       /* Keyboard Interrupt Enable Bit 2 */
    byte KBIE3       :1;                                       /* Keyboard Interrupt Enable Bit 3 */
    byte KBIE4       :1;                                       /* Keyboard Interrupt Enable Bit 4 */
    byte KBIE5       :1;                                       /* Keyboard Interrupt Enable Bit 5 */
    byte KBIE6       :1;                                       /* Keyboard Interrupt Enable Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte         :1;
    byte grpKBIE_1 :6;
    byte         :1;
  } MergedBits;
} INTKBIERSTR;
extern volatile INTKBIERSTR _INTKBIER;
#define INTKBIER                        _INTKBIER.Byte
#define INTKBIER_KBIE1                  _INTKBIER.Bits.KBIE1
#define INTKBIER_KBIE2                  _INTKBIER.Bits.KBIE2
#define INTKBIER_KBIE3                  _INTKBIER.Bits.KBIE3
#define INTKBIER_KBIE4                  _INTKBIER.Bits.KBIE4
#define INTKBIER_KBIE5                  _INTKBIER.Bits.KBIE5
#define INTKBIER_KBIE6                  _INTKBIER.Bits.KBIE6
#define INTKBIER_KBIE_1                 _INTKBIER.MergedBits.grpKBIE_1
#define INTKBIER_KBIE                   INTKBIER_KBIE_1

#define INTKBIER_KBIE1_MASK             2
#define INTKBIER_KBIE2_MASK             4
#define INTKBIER_KBIE3_MASK             8
#define INTKBIER_KBIE4_MASK             16
#define INTKBIER_KBIE5_MASK             32
#define INTKBIER_KBIE6_MASK             64
#define INTKBIER_KBIE_1_MASK            126
#define INTKBIER_KBIE_1_BITNUM          1


/*** CONFIG - Configuration Register; 0x0000001F ***/
typedef union {
  byte Byte;
  struct {
    byte COPD        :1;                                       /* COP Disable Bit */
    byte STOP        :1;                                       /* STOP Instruction Enable Bit */
    byte SSREC       :1;                                       /* Short Stop Recovery Bit */
    byte COPRS       :1;                                       /* COP Reset Period Selection Bit */
    byte LVIPWR      :1;                                       /* Low Voltage Inhibit Power Enable Bit */
    byte LVIRST      :1;                                       /* Low Voltage Inhibit Reset Enable Bit */
    byte LVISTOP     :1;                                       /* LVI Enable in Stop Mode Bit */
    byte EXTSLOW     :1;                                       /* Slow External Crystal Enable Bit */
  } Bits;
} CONFIGSTR;
extern volatile CONFIGSTR _CONFIG;
#define CONFIG                          _CONFIG.Byte
#define CONFIG_COPD                     _CONFIG.Bits.COPD
#define CONFIG_STOP                     _CONFIG.Bits.STOP
#define CONFIG_SSREC                    _CONFIG.Bits.SSREC
#define CONFIG_COPRS                    _CONFIG.Bits.COPRS
#define CONFIG_LVIPWR                   _CONFIG.Bits.LVIPWR
#define CONFIG_LVIRST                   _CONFIG.Bits.LVIRST
#define CONFIG_LVISTOP                  _CONFIG.Bits.LVISTOP
#define CONFIG_EXTSLOW                  _CONFIG.Bits.EXTSLOW

#define CONFIG_COPD_MASK                1
#define CONFIG_STOP_MASK                2
#define CONFIG_SSREC_MASK               4
#define CONFIG_COPRS_MASK               8
#define CONFIG_LVIPWR_MASK              16
#define CONFIG_LVIRST_MASK              32
#define CONFIG_LVISTOP_MASK             64
#define CONFIG_EXTSLOW_MASK             128


/*** TSC - TIM Status and Control Register TSC; 0x00000020 ***/
typedef union {
  byte Byte;
  struct {
    byte PS0         :1;                                       /* Prescaler Select Bit */
    byte PS1         :1;                                       /* Prescaler Select Bit */
    byte PS2         :1;                                       /* Prescaler Select Bit */
    byte             :1; 
    byte TRST        :1;                                       /* TIM Reset Bit */
    byte TSTOP       :1;                                       /* TIM Stop Bit */
    byte TOIE        :1;                                       /* TIM Overflow Interrupt Enable Bit */
    byte TOF         :1;                                       /* TIM Overflow Flag Bit */
  } Bits;
  struct {
    byte grpPS   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TSCSTR;
extern volatile TSCSTR _TSC;
#define TSC                             _TSC.Byte
#define TSC_PS0                         _TSC.Bits.PS0
#define TSC_PS1                         _TSC.Bits.PS1
#define TSC_PS2                         _TSC.Bits.PS2
#define TSC_TRST                        _TSC.Bits.TRST
#define TSC_TSTOP                       _TSC.Bits.TSTOP
#define TSC_TOIE                        _TSC.Bits.TOIE
#define TSC_TOF                         _TSC.Bits.TOF
#define TSC_PS                          _TSC.MergedBits.grpPS

#define TSC_PS0_MASK                    1
#define TSC_PS1_MASK                    2
#define TSC_PS2_MASK                    4
#define TSC_TRST_MASK                   16
#define TSC_TSTOP_MASK                  32
#define TSC_TOIE_MASK                   64
#define TSC_TOF_MASK                    128
#define TSC_PS_MASK                     7
#define TSC_PS_BITNUM                   0


/*** TCNT - TIM Counter Register; 0x00000021 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TCNTH - TIM Counter Register High; 0x00000021 ***/
    union {
      byte Byte;
    } TCNTHSTR;
    #define TCNTH                       _TCNT.Overlap_STR.TCNTHSTR.Byte
    

    /*** TCNTL - TIM Counter Register Low; 0x00000022 ***/
    union {
      byte Byte;
    } TCNTLSTR;
    #define TCNTL                       _TCNT.Overlap_STR.TCNTLSTR.Byte
    
  } Overlap_STR;

} TCNTSTR;
extern volatile TCNTSTR _TCNT;
#define TCNT                            _TCNT.Word


/*** TMOD - TIM Counter Modulo Register; 0x00000023 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TMODH - TIM Counter Modulo Register High; 0x00000023 ***/
    union {
      byte Byte;
    } TMODHSTR;
    #define TMODH                       _TMOD.Overlap_STR.TMODHSTR.Byte
    

    /*** TMODL - TIM Counter Modulo Register Low; 0x00000024 ***/
    union {
      byte Byte;
    } TMODLSTR;
    #define TMODL                       _TMOD.Overlap_STR.TMODLSTR.Byte
    
  } Overlap_STR;

} TMODSTR;
extern volatile TMODSTR _TMOD;
#define TMOD                            _TMOD.Word


/*** TSC0 - TIM Channel 0 Status and Control Register; 0x00000025 ***/
typedef union {
  byte Byte;
  struct {
    byte CH0MAX      :1;                                       /* Channel 0 Maximum Duty Cycle Bit */
    byte TOV0        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS0A       :1;                                       /* Edge/Level Select Bit */
    byte ELS0B       :1;                                       /* Edge/Level Select Bit */
    byte MS0A        :1;                                       /* Mode Select Bit A */
    byte MS0B        :1;                                       /* Mode Select Bit B */
    byte CH0IE       :1;                                       /* Channel 0 Interrupt Enable Bit */
    byte CH0F        :1;                                       /* Channel 0 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV  :1;
    byte grpELS0x :2;
    byte grpMS0x :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} TSC0STR;
extern volatile TSC0STR _TSC0;
#define TSC0                            _TSC0.Byte
#define TSC0_CH0MAX                     _TSC0.Bits.CH0MAX
#define TSC0_TOV0                       _TSC0.Bits.TOV0
#define TSC0_ELS0A                      _TSC0.Bits.ELS0A
#define TSC0_ELS0B                      _TSC0.Bits.ELS0B
#define TSC0_MS0A                       _TSC0.Bits.MS0A
#define TSC0_MS0B                       _TSC0.Bits.MS0B
#define TSC0_CH0IE                      _TSC0.Bits.CH0IE
#define TSC0_CH0F                       _TSC0.Bits.CH0F
#define TSC0_ELS0x                      _TSC0.MergedBits.grpELS0x
#define TSC0_MS0x                       _TSC0.MergedBits.grpMS0x

#define TSC0_CH0MAX_MASK                1
#define TSC0_TOV0_MASK                  2
#define TSC0_ELS0A_MASK                 4
#define TSC0_ELS0B_MASK                 8
#define TSC0_MS0A_MASK                  16
#define TSC0_MS0B_MASK                  32
#define TSC0_CH0IE_MASK                 64
#define TSC0_CH0F_MASK                  128
#define TSC0_ELS0x_MASK                 12
#define TSC0_ELS0x_BITNUM               2
#define TSC0_MS0x_MASK                  48
#define TSC0_MS0x_BITNUM                4


/*** TCH0 - TIM Channel 0 Register; 0x00000026 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TCH0H - TIM Channel 0 Register High; 0x00000026 ***/
    union {
      byte Byte;
    } TCH0HSTR;
    #define TCH0H                       _TCH0.Overlap_STR.TCH0HSTR.Byte
    

    /*** TCH0L - TIM Channel 0 Register Low; 0x00000027 ***/
    union {
      byte Byte;
    } TCH0LSTR;
    #define TCH0L                       _TCH0.Overlap_STR.TCH0LSTR.Byte
    
  } Overlap_STR;

} TCH0STR;
extern volatile TCH0STR _TCH0;
#define TCH0                            _TCH0.Word


/*** TSC1 - TIM Channel 1 Status and Control Register; 0x00000028 ***/
typedef union {
  byte Byte;
  struct {
    byte CH1MAX      :1;                                       /* Channel 1 Maximum Duty Cycle Bit */
    byte TOV1        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS1A       :1;                                       /* Edge/Level Select Bit */
    byte ELS1B       :1;                                       /* Edge/Level Select Bit */
    byte MS1A        :1;                                       /* Mode Select Bit A */
    byte             :1; 
    byte CH1IE       :1;                                       /* Channel 1 Interrupt Enable Bit */
    byte CH1F        :1;                                       /* Channel 1 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_1 :1;
    byte grpELS1x :2;
    byte grpMS1x :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TSC1STR;
extern volatile TSC1STR _TSC1;
#define TSC1                            _TSC1.Byte
#define TSC1_CH1MAX                     _TSC1.Bits.CH1MAX
#define TSC1_TOV1                       _TSC1.Bits.TOV1
#define TSC1_ELS1A                      _TSC1.Bits.ELS1A
#define TSC1_ELS1B                      _TSC1.Bits.ELS1B
#define TSC1_MS1A                       _TSC1.Bits.MS1A
#define TSC1_CH1IE                      _TSC1.Bits.CH1IE
#define TSC1_CH1F                       _TSC1.Bits.CH1F
#define TSC1_ELS1x                      _TSC1.MergedBits.grpELS1x

#define TSC1_CH1MAX_MASK                1
#define TSC1_TOV1_MASK                  2
#define TSC1_ELS1A_MASK                 4
#define TSC1_ELS1B_MASK                 8
#define TSC1_MS1A_MASK                  16
#define TSC1_CH1IE_MASK                 64
#define TSC1_CH1F_MASK                  128
#define TSC1_ELS1x_MASK                 12
#define TSC1_ELS1x_BITNUM               2


/*** TCH1 - TIM Channel 1 Register; 0x00000029 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TCH1H - TIM Channel 1 Register High; 0x00000029 ***/
    union {
      byte Byte;
    } TCH1HSTR;
    #define TCH1H                       _TCH1.Overlap_STR.TCH1HSTR.Byte
    

    /*** TCH1L - TIM Channel 1 Register Low; 0x0000002A ***/
    union {
      byte Byte;
    } TCH1LSTR;
    #define TCH1L                       _TCH1.Overlap_STR.TCH1LSTR.Byte
    
  } Overlap_STR;

} TCH1STR;
extern volatile TCH1STR _TCH1;
#define TCH1                            _TCH1.Word


/*** ICGCR - ICG Control Register; 0x00000036 ***/
typedef union {
  byte Byte;
  struct {
    byte ECGS        :1;                                       /* Extrernal Clock Generator Stable Bit */
    byte ECGON       :1;                                       /* External Clock Generator On Bit */
    byte ICGS        :1;                                       /* Internal Clock Generator Stable Bit */
    byte ICGON       :1;                                       /* Internal Clock Generator On Bit */
    byte CS          :1;                                       /* Clock Select Bit */
    byte CMON        :1;                                       /* Clock Monitor On Bit */
    byte CMF         :1;                                       /* Clock Monitor Interrupt Flag */
    byte CMIE        :1;                                       /* Clock Monitor Interrupt Enable Bit */
  } Bits;
} ICGCRSTR;
extern volatile ICGCRSTR _ICGCR;
#define ICGCR                           _ICGCR.Byte
#define ICGCR_ECGS                      _ICGCR.Bits.ECGS
#define ICGCR_ECGON                     _ICGCR.Bits.ECGON
#define ICGCR_ICGS                      _ICGCR.Bits.ICGS
#define ICGCR_ICGON                     _ICGCR.Bits.ICGON
#define ICGCR_CS                        _ICGCR.Bits.CS
#define ICGCR_CMON                      _ICGCR.Bits.CMON
#define ICGCR_CMF                       _ICGCR.Bits.CMF
#define ICGCR_CMIE                      _ICGCR.Bits.CMIE

#define ICGCR_ECGS_MASK                 1
#define ICGCR_ECGON_MASK                2
#define ICGCR_ICGS_MASK                 4
#define ICGCR_ICGON_MASK                8
#define ICGCR_CS_MASK                   16
#define ICGCR_CMON_MASK                 32
#define ICGCR_CMF_MASK                  64
#define ICGCR_CMIE_MASK                 128


/*** ICGMR - ICG Multiplier Register; 0x00000037 ***/
typedef union {
  byte Byte;
  struct {
    byte N0          :1;                                       /* ICG Multiplier Factor Bit */
    byte N1          :1;                                       /* ICG Multiplier Factor Bit */
    byte N2          :1;                                       /* ICG Multiplier Factor Bit */
    byte N3          :1;                                       /* ICG Multiplier Factor Bit */
    byte N4          :1;                                       /* ICG Multiplier Factor Bit */
    byte N5          :1;                                       /* ICG Multiplier Factor Bit */
    byte N6          :1;                                       /* ICG Multiplier Factor Bit */
    byte             :1; 
  } Bits;
  struct {
    byte grpN    :7;
    byte         :1;
  } MergedBits;
} ICGMRSTR;
extern volatile ICGMRSTR _ICGMR;
#define ICGMR                           _ICGMR.Byte
#define ICGMR_N0                        _ICGMR.Bits.N0
#define ICGMR_N1                        _ICGMR.Bits.N1
#define ICGMR_N2                        _ICGMR.Bits.N2
#define ICGMR_N3                        _ICGMR.Bits.N3
#define ICGMR_N4                        _ICGMR.Bits.N4
#define ICGMR_N5                        _ICGMR.Bits.N5
#define ICGMR_N6                        _ICGMR.Bits.N6
#define ICGMR_N                         _ICGMR.MergedBits.grpN

#define ICGMR_N0_MASK                   1
#define ICGMR_N1_MASK                   2
#define ICGMR_N2_MASK                   4
#define ICGMR_N3_MASK                   8
#define ICGMR_N4_MASK                   16
#define ICGMR_N5_MASK                   32
#define ICGMR_N6_MASK                   64
#define ICGMR_N_MASK                    127
#define ICGMR_N_BITNUM                  0


/*** ICGTR - ICG Trim Register; 0x00000038 ***/
typedef union {
  byte Byte;
  struct {
    byte TRIM0       :1;                                       /* ICG Trim Factor Bit */
    byte TRIM1       :1;                                       /* ICG Trim Factor Bit */
    byte TRIM2       :1;                                       /* ICG Trim Factor Bit */
    byte TRIM3       :1;                                       /* ICG Trim Factor Bit */
    byte TRIM4       :1;                                       /* ICG Trim Factor Bit */
    byte TRIM5       :1;                                       /* ICG Trim Factor Bit */
    byte TRIM6       :1;                                       /* ICG Trim Factor Bit */
    byte TRIM7       :1;                                       /* ICG Trim Factor Bit */
  } Bits;
} ICGTRSTR;
extern volatile ICGTRSTR _ICGTR;
#define ICGTR                           _ICGTR.Byte
#define ICGTR_TRIM0                     _ICGTR.Bits.TRIM0
#define ICGTR_TRIM1                     _ICGTR.Bits.TRIM1
#define ICGTR_TRIM2                     _ICGTR.Bits.TRIM2
#define ICGTR_TRIM3                     _ICGTR.Bits.TRIM3
#define ICGTR_TRIM4                     _ICGTR.Bits.TRIM4
#define ICGTR_TRIM5                     _ICGTR.Bits.TRIM5
#define ICGTR_TRIM6                     _ICGTR.Bits.TRIM6
#define ICGTR_TRIM7                     _ICGTR.Bits.TRIM7

#define ICGTR_TRIM0_MASK                1
#define ICGTR_TRIM1_MASK                2
#define ICGTR_TRIM2_MASK                4
#define ICGTR_TRIM3_MASK                8
#define ICGTR_TRIM4_MASK                16
#define ICGTR_TRIM5_MASK                32
#define ICGTR_TRIM6_MASK                64
#define ICGTR_TRIM7_MASK                128


/*** ICGDVR - ICG DCO Divider Control Register; 0x00000039 ***/
typedef union {
  byte Byte;
  struct {
    byte DDIV0       :1;                                       /* ICG DCO Divider Control Bit */
    byte DDIV1       :1;                                       /* ICG DCO Divider Control Bit */
    byte DDIV2       :1;                                       /* ICG DCO Divider Control Bit */
    byte DDIV3       :1;                                       /* ICG DCO Divider Control Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDDIV :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} ICGDVRSTR;
extern volatile ICGDVRSTR _ICGDVR;
#define ICGDVR                          _ICGDVR.Byte
#define ICGDVR_DDIV0                    _ICGDVR.Bits.DDIV0
#define ICGDVR_DDIV1                    _ICGDVR.Bits.DDIV1
#define ICGDVR_DDIV2                    _ICGDVR.Bits.DDIV2
#define ICGDVR_DDIV3                    _ICGDVR.Bits.DDIV3
#define ICGDVR_DDIV                     _ICGDVR.MergedBits.grpDDIV

#define ICGDVR_DDIV0_MASK               1
#define ICGDVR_DDIV1_MASK               2
#define ICGDVR_DDIV2_MASK               4
#define ICGDVR_DDIV3_MASK               8
#define ICGDVR_DDIV_MASK                15
#define ICGDVR_DDIV_BITNUM              0


/*** ICGDSR - ICG DCO Stage Control Register; 0x0000003A ***/
typedef union {
  byte Byte;
  struct {
    byte DSTG0       :1;                                       /* ICG DCO Stage Control Bit */
    byte DSTG1       :1;                                       /* ICG DCO Stage Control Bit */
    byte DSTG2       :1;                                       /* ICG DCO Stage Control Bit */
    byte DSTG3       :1;                                       /* ICG DCO Stage Control Bit */
    byte DSTG4       :1;                                       /* ICG DCO Stage Control Bit */
    byte DSTG5       :1;                                       /* ICG DCO Stage Control Bit */
    byte DSTG6       :1;                                       /* ICG DCO Stage Control Bit */
    byte DSTG7       :1;                                       /* ICG DCO Stage Control Bit */
  } Bits;
} ICGDSRSTR;
extern volatile ICGDSRSTR _ICGDSR;
#define ICGDSR                          _ICGDSR.Byte
#define ICGDSR_DSTG0                    _ICGDSR.Bits.DSTG0
#define ICGDSR_DSTG1                    _ICGDSR.Bits.DSTG1
#define ICGDSR_DSTG2                    _ICGDSR.Bits.DSTG2
#define ICGDSR_DSTG3                    _ICGDSR.Bits.DSTG3
#define ICGDSR_DSTG4                    _ICGDSR.Bits.DSTG4
#define ICGDSR_DSTG5                    _ICGDSR.Bits.DSTG5
#define ICGDSR_DSTG6                    _ICGDSR.Bits.DSTG6
#define ICGDSR_DSTG7                    _ICGDSR.Bits.DSTG7

#define ICGDSR_DSTG0_MASK               1
#define ICGDSR_DSTG1_MASK               2
#define ICGDSR_DSTG2_MASK               4
#define ICGDSR_DSTG3_MASK               8
#define ICGDSR_DSTG4_MASK               16
#define ICGDSR_DSTG5_MASK               32
#define ICGDSR_DSTG6_MASK               64
#define ICGDSR_DSTG7_MASK               128


/*** SBSR - SIM Break Status Register; 0x0000FE00 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte SBSW        :1;                                       /* Break Wait Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SBSRSTR;
extern volatile SBSRSTR _SBSR;
#define SBSR                            _SBSR.Byte
#define SBSR_SBSW                       _SBSR.Bits.SBSW

#define SBSR_SBSW_MASK                  2


/*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte LVI         :1;                                       /* Low-Voltage Inhibit Reset Bit */
    byte             :1; 
    byte ILAD        :1;                                       /* Illegal Address Reset Bit */
    byte ILOP        :1;                                       /* Illegal Opcode Reset Bit */
    byte COP         :1;                                       /* Computer Operating Properly Reset Bit */
    byte PIN         :1;                                       /* External Reset Bit */
    byte POR         :1;                                       /* Power-On Reset Bit */
  } Bits;
} SRSRSTR;
extern volatile SRSRSTR _SRSR;
#define SRSR                            _SRSR.Byte
#define SRSR_LVI                        _SRSR.Bits.LVI
#define SRSR_ILAD                       _SRSR.Bits.ILAD
#define SRSR_ILOP                       _SRSR.Bits.ILOP
#define SRSR_COP                        _SRSR.Bits.COP
#define SRSR_PIN                        _SRSR.Bits.PIN
#define SRSR_POR                        _SRSR.Bits.POR

#define SRSR_LVI_MASK                   2
#define SRSR_ILAD_MASK                  8
#define SRSR_ILOP_MASK                  16
#define SRSR_COP_MASK                   32
#define SRSR_PIN_MASK                   64
#define SRSR_POR_MASK                   128


/*** SBFCR - SIM Break Flag Control Register; 0x0000FE02 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BCFE        :1;                                       /* Break Clear Flag Enable Bit */
  } Bits;
} SBFCRSTR;
extern volatile SBFCRSTR _SBFCR;
#define SBFCR                           _SBFCR.Byte
#define SBFCR_BCFE                      _SBFCR.Bits.BCFE

#define SBFCR_BCFE_MASK                 128


/*** FLCR - FLASH 2TS Control Register; 0x0000FE08 ***/
typedef union {
  byte Byte;
  struct {
    byte PGM         :1;                                       /* Program Control Bit */
    byte ERASE       :1;                                       /* Erase Control Bit */
    byte MARGIN      :1;                                       /* Mass Erase Control Bit */
    byte HVEN        :1;                                       /* High-Voltage Enable Bit */
    byte BLK0        :1;                                       /* Block Erase Control Bit */
    byte BLK1        :1;                                       /* Block Erase Control Bit */
    byte FDIV0       :1;                                       /* Frequency Divide Control Bit */
    byte             :1; 
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpBLK  :2;
    byte grpFDIV :1;
    byte         :1;
  } MergedBits;
} FLCRSTR;
extern volatile FLCRSTR _FLCR;
#define FLCR                            _FLCR.Byte
#define FLCR_PGM                        _FLCR.Bits.PGM
#define FLCR_ERASE                      _FLCR.Bits.ERASE
#define FLCR_MARGIN                     _FLCR.Bits.MARGIN
#define FLCR_HVEN                       _FLCR.Bits.HVEN
#define FLCR_BLK0                       _FLCR.Bits.BLK0
#define FLCR_BLK1                       _FLCR.Bits.BLK1
#define FLCR_FDIV0                      _FLCR.Bits.FDIV0
#define FLCR_BLK                        _FLCR.MergedBits.grpBLK

#define FLCR_PGM_MASK                   1
#define FLCR_ERASE_MASK                 2
#define FLCR_MARGIN_MASK                4
#define FLCR_HVEN_MASK                  8
#define FLCR_BLK0_MASK                  16
#define FLCR_BLK1_MASK                  32
#define FLCR_FDIV0_MASK                 64
#define FLCR_BLK_MASK                   48
#define FLCR_BLK_BITNUM                 4


/*** BRK - Break Address Register; 0x0000FE0C ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** BRKH - Break Address Register High; 0x0000FE0C ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Break Address Register Bit */
        byte BIT9        :1;                                       /* Break Address Register Bit */
        byte BIT10       :1;                                       /* Break Address Register Bit */
        byte BIT11       :1;                                       /* Break Address Register Bit */
        byte BIT12       :1;                                       /* Break Address Register Bit */
        byte BIT13       :1;                                       /* Break Address Register Bit */
        byte BIT14       :1;                                       /* Break Address Register Bit */
        byte BIT15       :1;                                       /* Break Address Register Bit */
      } Bits;
    } BRKHSTR;
    #define BRKH                        _BRK.Overlap_STR.BRKHSTR.Byte
    #define BRKH_BIT8                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT8
    #define BRKH_BIT9                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT9
    #define BRKH_BIT10                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT10
    #define BRKH_BIT11                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT11
    #define BRKH_BIT12                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT12
    #define BRKH_BIT13                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT13
    #define BRKH_BIT14                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT14
    #define BRKH_BIT15                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT15
    
    #define BRKH_BIT8_MASK              1
    #define BRKH_BIT9_MASK              2
    #define BRKH_BIT10_MASK             4
    #define BRKH_BIT11_MASK             8
    #define BRKH_BIT12_MASK             16
    #define BRKH_BIT13_MASK             32
    #define BRKH_BIT14_MASK             64
    #define BRKH_BIT15_MASK             128
    

    /*** BRKL - Break Address Register Low; 0x0000FE0D ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Break Address Register Bit */
        byte BIT1        :1;                                       /* Break Address Register Bit */
        byte BIT2        :1;                                       /* Break Address Register Bit */
        byte BIT3        :1;                                       /* Break Address Register Bit */
        byte BIT4        :1;                                       /* Break Address Register Bit */
        byte BIT5        :1;                                       /* Break Address Register Bit */
        byte BIT6        :1;                                       /* Break Address Register Bit */
        byte BIT7        :1;                                       /* Break Address Register Bit */
      } Bits;
    } BRKLSTR;
    #define BRKL                        _BRK.Overlap_STR.BRKLSTR.Byte
    #define BRKL_BIT0                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT0
    #define BRKL_BIT1                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT1
    #define BRKL_BIT2                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT2
    #define BRKL_BIT3                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT3
    #define BRKL_BIT4                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT4
    #define BRKL_BIT5                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT5
    #define BRKL_BIT6                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT6
    #define BRKL_BIT7                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT7
    
    #define BRKL_BIT0_MASK              1
    #define BRKL_BIT1_MASK              2
    #define BRKL_BIT2_MASK              4
    #define BRKL_BIT3_MASK              8
    #define BRKL_BIT4_MASK              16
    #define BRKL_BIT5_MASK              32
    #define BRKL_BIT6_MASK              64
    #define BRKL_BIT7_MASK              128
    
  } Overlap_STR;

} BRKSTR;
extern volatile BRKSTR _BRK;
#define BRK                             _BRK.Word


/*** BRKSCR - Break Status and Control Register; 0x0000FE0E ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BRKA        :1;                                       /* Break Active Bit */
    byte BRKE        :1;                                       /* Break Enable Bit */
  } Bits;
} BRKSCRSTR;
extern volatile BRKSCRSTR _BRKSCR;
#define BRKSCR                          _BRKSCR.Byte
#define BRKSCR_BRKA                     _BRKSCR.Bits.BRKA
#define BRKSCR_BRKE                     _BRKSCR.Bits.BRKE

#define BRKSCR_BRKA_MASK                64
#define BRKSCR_BRKE_MASK                128


/*** LVISR - LVI Status Register; 0x0000FE0F ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte LOWV        :1;                                       /* LVI Low Indicator Bit */
    byte             :1; 
    byte LVIOUT      :1;                                       /* LVI Output Bit */
  } Bits;
} LVISRSTR;
extern volatile LVISRSTR _LVISR;
#define LVISR                           _LVISR.Byte
#define LVISR_LOWV                      _LVISR.Bits.LOWV
#define LVISR_LVIOUT                    _LVISR.Bits.LVIOUT

#define LVISR_LOWV_MASK                 32
#define LVISR_LVIOUT_MASK               128


/*** FLBPR - FLASH 2TS Block Protect Register; 0x0000FFF0 ***/
typedef union {
  byte Byte;
  struct {
    byte BPR0        :1;                                       /* Block Protect Register Bit 0 */
    byte BPR1        :1;                                       /* Block Protect Register Bit 1 */
    byte BPR2        :1;                                       /* Block Protect Register Bit 2 */
    byte BPR3        :1;                                       /* Block Protect Register Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpBPR  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} FLBPRSTR;
/* Tip for register initialization in the user code:  const byte FLBPR_INIT @0x0000FFF0 = <FLBPR_INITVAL>; */
#define _FLBPR (*(const FLBPRSTR * __far)0x0000FFF0)
#define FLBPR                           _FLBPR.Byte
#define FLBPR_BPR0                      _FLBPR.Bits.BPR0
#define FLBPR_BPR1                      _FLBPR.Bits.BPR1
#define FLBPR_BPR2                      _FLBPR.Bits.BPR2
#define FLBPR_BPR3                      _FLBPR.Bits.BPR3
#define FLBPR_BPR                       _FLBPR.MergedBits.grpBPR

#define FLBPR_BPR0_MASK                 1
#define FLBPR_BPR1_MASK                 2
#define FLBPR_BPR2_MASK                 4
#define FLBPR_BPR3_MASK                 8
#define FLBPR_BPR_MASK                  15
#define FLBPR_BPR_BITNUM                0


/*** COPCTL - COP Control Register; 0x0000FFFF ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Bit 0 */
    byte BIT1        :1;                                       /* Bit 1 */
    byte BIT2        :1;                                       /* Bit 2 */
    byte BIT3        :1;                                       /* Bit 3 */
    byte BIT4        :1;                                       /* Bit 4 */
    byte BIT5        :1;                                       /* Bit 5 */
    byte BIT6        :1;                                       /* Bit 6 */
    byte BIT7        :1;                                       /* Bit 7 */
  } Bits;
} COPCTLSTR;
extern volatile COPCTLSTR _COPCTL;
#define COPCTL                          _COPCTL.Byte
#define COPCTL_BIT0                     _COPCTL.Bits.BIT0
#define COPCTL_BIT1                     _COPCTL.Bits.BIT1
#define COPCTL_BIT2                     _COPCTL.Bits.BIT2
#define COPCTL_BIT3                     _COPCTL.Bits.BIT3
#define COPCTL_BIT4                     _COPCTL.Bits.BIT4
#define COPCTL_BIT5                     _COPCTL.Bits.BIT5
#define COPCTL_BIT6                     _COPCTL.Bits.BIT6
#define COPCTL_BIT7                     _COPCTL.Bits.BIT7

#define COPCTL_BIT0_MASK                1
#define COPCTL_BIT1_MASK                2
#define COPCTL_BIT2_MASK                4
#define COPCTL_BIT3_MASK                8
#define COPCTL_BIT4_MASK                16
#define COPCTL_BIT5_MASK                32
#define COPCTL_BIT6_MASK                64
#define COPCTL_BIT7_MASK                128



/***********************************************/
/**   D E P R E C I A T E D   S Y M B O L S   **/
/***********************************************/
/* ---------------------------------------------------------------------------------------------------
Exceptions in bit names of timer status and control registers
due to backward compatibility with previous releases  */
#define TSC0_CHxMAX _TSC0.Bits.CH0MAX
#define TSC0_TOVx _TSC0.Bits.TOV0
#define TSC0_ELSxA _TSC0.Bits.ELS0A
#define TSC0_ELSxB _TSC0.Bits.ELS0B
#define TSC0_MSxA _TSC0.Bits.MS0A
#define TSC0_MSxB _TSC0.Bits.MS0B
#define TSC0_CHxIE _TSC0.Bits.CH0IE
#define TSC0_CHxF _TSC0.Bits.CH0F

#define TSC1_CHxMAX _TSC1.Bits.CH1MAX
#define TSC1_TOVx _TSC1.Bits.TOV1
#define TSC1_ELSxA _TSC1.Bits.ELS1A
#define TSC1_ELSxB _TSC1.Bits.ELS1B
#define TSC1_MSxA _TSC1.Bits.MS1A
#define TSC1_CHxIE _TSC1.Bits.CH1IE
#define TSC1_CHxF _TSC1.Bits.CH1F

/* --------------------------------------------------------------------------- */
/* The following symbols were removed, because they were invalid or irrelevant */
/* --------------------------------------------------------------------------- */


/* **** 11.9.2009 12:42:45 */

#define TCH_ARR                          This_symb_has_been_depreciated
#endif
