/* Based on CPU DB MC68HC908SR12_48, version 2.89.088 (RegistersPrg V2.30) */
/*
** ###################################################################
**     Filename  : mc68hc908sr12.h
**     Processor : MC68HC908SR12CFA
**     FileFormat: V2.30
**     DataSheet : MC68HC908SR12 Rev. 5.0 07/2004
**     Compiler  : CodeWarrior compiler
**     Date/Time : 11.9.2009, 14:10
**     Abstract  :
**         This header implements the mapping of I/O devices.
**
**     Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved.
**     
**     http      : www.freescale.com
**     mail      : support@freescale.com
**
**     CPU Registers Revisions:
**      - 23.03.2006, V2.89.076:
**              - Renamed bits ADSCR_CHx ==> ADSCR_ADCHx. REASON: Bug-fix (#3140 in Issue Manager)
**
**     File-Format-Revisions:
**      - 14.11.2005, V2.00 :
**               - Deprecated symbols added for backward compatibility (section at the end of this file)
**      - 15.11.2005, V2.01 :
**               - Changes have not affected this file (because they are related to another family)
**      - 17.12.2005, V2.02 :
**               - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778
**      - 16.01.2006, V2.03 :
**               - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920.
**               - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const")
**      - 08.03.2006, V2.04 :
**               - Support for bit(s) names duplicated with any register name in .h header files
**      - 24.03.2006, V2.05 :
**               - Changes have not affected this file (because they are related to another family)
**      - 26.04.2006, V2.06 :
**               - Absolute assembly supported (depreciated symbols are not defined)
**      - 27.04.2006, V2.07 :
**               - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA).
**      - 07.06.2006, V2.08 :
**               - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM.
**      - 03.07.2006, V2.09 :
**               - Flash commands constants supported
**      - 27.10.2006, V2.10 :
**               - __RESET_WATCHDOG improved formating and re-definition
**      - 23.11.2006, V2.11 :
**               - Changes have not affected this file (because they are related to another family)
**      - 22.01.2007, V2.12 :
**               - Changes have not affected this file (because they are related to another family)
**      - 01.03.2007, V2.13 :
**               - Flash commands constants values converted to HEX format
**      - 02.03.2007, V2.14 :
**               - Interrupt vector numbers added into .H, see VectorNumber_*
**      - 26.03.2007, V2.15 :
**               - Changes have not affected this file (because they are related to another family)
**      - 10.05.2007, V2.16 :
**               - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ)
**      - 05.06.2007, V2.17 :
**               - Changes have not affected this file (because they are related to another family)
**      - 19.07.2007, V2.18 :
**               - Improved number of blanked lines inside register structures
**      - 06.08.2007, V2.19 :
**               - CPUDB revisions generated ahead of the file-format revisions.
**      - 11.09.2007, V2.20 :
**               - Added comment about initialization of unbonded pins.
**      - 02.01.2008, V2.21 :
**               - Changes have not affected this file (because they are related to another family)
**      - 13.02.2008, V2.22 :
**               - Changes have not affected this file (because they are related to another family)
**      - 20.02.2008, V2.23 :
**               - Changes have not affected this file (because they are related to another family)
**      - 03.07.2008, V2.24 :
**               - Added support for bits with name starting with number (like "1HZ")
**      - 28.11.2008, V2.25 :
**               - StandBy RAM array declaration for ANSI-C added
**      - 1.12.2008, V2.26 :
**               - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map.
**      - 17.3.2009, V2.27 :
**               - Merged bit-group is not generated, if the name matches with another bit name in the register
**      - 6.4.2009, V2.28 :
**               - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB
**      - 3.8.2009, V2.29 :
**               - If there is just one bits group matching register name, single bits are not generated
**      - 10.9.2009, V2.30 :
**               - Fixed generation of registers arrays.
**
**     Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific
**     derivative device. To avoid extra current drain from floating input pins, the user’s reset
**     initialization routine in the application program must either enable on-chip pull-up devices
**     or change the direction of unconnected pins to outputs so the pins do not float.
** ###################################################################
*/

#ifndef _MC68HC908SR12_H
#define _MC68HC908SR12_H

/* Types definition */
typedef unsigned char byte;
typedef unsigned int word;
typedef unsigned long dword;
typedef unsigned long dlong[2];

/* Watchdog reset macro */
#ifndef __RESET_WATCHDOG
#ifdef _lint
  #define __RESET_WATCHDOG()  /* empty */
#else
  #define __RESET_WATCHDOG() {asm sta COPCTL;}
#endif
#endif /* __RESET_WATCHDOG */

#define REG_BASE 0x0000                /* Base address for the I/O register block */


#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */

/**************** interrupt vector numbers ****************/
#define VectorNumber_TBM                18
#define VectorNumber_Analog             17
#define VectorNumber_ADC                16
#define VectorNumber_KBD                15
#define VectorNumber_SCITransmit        14
#define VectorNumber_SCIReceive         13
#define VectorNumber_SCIError           12
#define VectorNumber_MMIIC              11
#define VectorNumber_TIM2Ovr            10
#define VectorNumber_TIM2CH1            9
#define VectorNumber_TIM2CH0            8
#define VectorNumber_TIM1Ovr            7
#define VectorNumber_TIM1CH1            6
#define VectorNumber_TIM1CH0            5
#define VectorNumber_PLL                4
#define VectorNumber_IRQ2               3
#define VectorNumber_IRQ1               2
#define VectorNumber_SWI                1
#define VectorNumber_RESET              0

/**************** interrupt vector table ****************/
#define INT_TBM                         0x0000FFDA
#define INT_Analog                      0x0000FFDC
#define INT_ADC                         0x0000FFDE
#define INT_KBD                         0x0000FFE0
#define INT_SCITransmit                 0x0000FFE2
#define INT_SCIReceive                  0x0000FFE4
#define INT_SCIError                    0x0000FFE6
#define INT_MMIIC                       0x0000FFE8
#define INT_TIM2Ovr                     0x0000FFEA
#define INT_TIM2CH1                     0x0000FFEC
#define INT_TIM2CH0                     0x0000FFEE
#define INT_TIM1Ovr                     0x0000FFF0
#define INT_TIM1CH1                     0x0000FFF2
#define INT_TIM1CH0                     0x0000FFF4
#define INT_PLL                         0x0000FFF6
#define INT_IRQ2                        0x0000FFF8
#define INT_IRQ1                        0x0000FFFA
#define INT_SWI                         0x0000FFFC
#define INT_RESET                       0x0000FFFE

/**************** registers I/O map ****************/

/*** PTA - Port A Data Register; 0x00000000 ***/
typedef union {
  byte Byte;
  struct {
    byte PTA0        :1;                                       /* Port A Data Bit 0 */
    byte PTA1        :1;                                       /* Port A Data Bit 1 */
    byte PTA2        :1;                                       /* Port A Data Bit 2 */
    byte PTA3        :1;                                       /* Port A Data Bit 3 */
    byte PTA4        :1;                                       /* Port A Data Bit 4 */
    byte PTA5        :1;                                       /* Port A Data Bit 5 */
    byte PTA6        :1;                                       /* Port A Data Bit 6 */
    byte PTA7        :1;                                       /* Port A Data Bit 7 */
  } Bits;
} PTASTR;
extern volatile PTASTR _PTA;
#define PTA                             _PTA.Byte
#define PTA_PTA0                        _PTA.Bits.PTA0
#define PTA_PTA1                        _PTA.Bits.PTA1
#define PTA_PTA2                        _PTA.Bits.PTA2
#define PTA_PTA3                        _PTA.Bits.PTA3
#define PTA_PTA4                        _PTA.Bits.PTA4
#define PTA_PTA5                        _PTA.Bits.PTA5
#define PTA_PTA6                        _PTA.Bits.PTA6
#define PTA_PTA7                        _PTA.Bits.PTA7

#define PTA_PTA0_MASK                   1
#define PTA_PTA1_MASK                   2
#define PTA_PTA2_MASK                   4
#define PTA_PTA3_MASK                   8
#define PTA_PTA4_MASK                   16
#define PTA_PTA5_MASK                   32
#define PTA_PTA6_MASK                   64
#define PTA_PTA7_MASK                   128


/*** PTB - Port B Data Register; 0x00000001 ***/
typedef union {
  byte Byte;
  struct {
    byte PTB0        :1;                                       /* Port B Data Bit 0 */
    byte PTB1        :1;                                       /* Port B Data Bit 1 */
    byte PTB2        :1;                                       /* Port B Data Bit 2 */
    byte PTB3        :1;                                       /* Port B Data Bit 3 */
    byte PTB4        :1;                                       /* Port B Data Bit 4 */
    byte PTB5        :1;                                       /* Port B Data Bit 5 */
    byte PTB6        :1;                                       /* Port B Data Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpPTB  :7;
    byte         :1;
  } MergedBits;
} PTBSTR;
extern volatile PTBSTR _PTB;
#define PTB                             _PTB.Byte
#define PTB_PTB0                        _PTB.Bits.PTB0
#define PTB_PTB1                        _PTB.Bits.PTB1
#define PTB_PTB2                        _PTB.Bits.PTB2
#define PTB_PTB3                        _PTB.Bits.PTB3
#define PTB_PTB4                        _PTB.Bits.PTB4
#define PTB_PTB5                        _PTB.Bits.PTB5
#define PTB_PTB6                        _PTB.Bits.PTB6
#define PTB_PTB                         _PTB.MergedBits.grpPTB

#define PTB_PTB0_MASK                   1
#define PTB_PTB1_MASK                   2
#define PTB_PTB2_MASK                   4
#define PTB_PTB3_MASK                   8
#define PTB_PTB4_MASK                   16
#define PTB_PTB5_MASK                   32
#define PTB_PTB6_MASK                   64
#define PTB_PTB_MASK                    127
#define PTB_PTB_BITNUM                  0


/*** PTC - Port C Data Register; 0x00000002 ***/
typedef union {
  byte Byte;
  struct {
    byte PTC0        :1;                                       /* Port C Data Bit 0 */
    byte PTC1        :1;                                       /* Port C Data Bit 1 */
    byte PTC2        :1;                                       /* Port C Data Bit 2 */
    byte PTC3        :1;                                       /* Port C Data Bit 3 */
    byte PTC4        :1;                                       /* Port C Data Bit 4 */
    byte PTC5        :1;                                       /* Port C Data Bit 5 */
    byte PTC6        :1;                                       /* Port C Data Bit 6 */
    byte PTC7        :1;                                       /* Port C Data Bit 7 */
  } Bits;
} PTCSTR;
extern volatile PTCSTR _PTC;
#define PTC                             _PTC.Byte
#define PTC_PTC0                        _PTC.Bits.PTC0
#define PTC_PTC1                        _PTC.Bits.PTC1
#define PTC_PTC2                        _PTC.Bits.PTC2
#define PTC_PTC3                        _PTC.Bits.PTC3
#define PTC_PTC4                        _PTC.Bits.PTC4
#define PTC_PTC5                        _PTC.Bits.PTC5
#define PTC_PTC6                        _PTC.Bits.PTC6
#define PTC_PTC7                        _PTC.Bits.PTC7

#define PTC_PTC0_MASK                   1
#define PTC_PTC1_MASK                   2
#define PTC_PTC2_MASK                   4
#define PTC_PTC3_MASK                   8
#define PTC_PTC4_MASK                   16
#define PTC_PTC5_MASK                   32
#define PTC_PTC6_MASK                   64
#define PTC_PTC7_MASK                   128


/*** PTD - Port D Data Register; 0x00000003 ***/
typedef union {
  byte Byte;
  struct {
    byte PTD0        :1;                                       /* Port D Data Bit 0 */
    byte PTD1        :1;                                       /* Port D Data Bit 1 */
    byte PTD2        :1;                                       /* Port D Data Bit 2 */
    byte PTD3        :1;                                       /* Port D Data Bit 3 */
    byte PTD4        :1;                                       /* Port D Data Bit 4 */
    byte PTD5        :1;                                       /* Port D Data Bit 5 */
    byte PTD6        :1;                                       /* Port D Data Bit 6 */
    byte PTD7        :1;                                       /* Port D Data Bit 7 */
  } Bits;
} PTDSTR;
extern volatile PTDSTR _PTD;
#define PTD                             _PTD.Byte
#define PTD_PTD0                        _PTD.Bits.PTD0
#define PTD_PTD1                        _PTD.Bits.PTD1
#define PTD_PTD2                        _PTD.Bits.PTD2
#define PTD_PTD3                        _PTD.Bits.PTD3
#define PTD_PTD4                        _PTD.Bits.PTD4
#define PTD_PTD5                        _PTD.Bits.PTD5
#define PTD_PTD6                        _PTD.Bits.PTD6
#define PTD_PTD7                        _PTD.Bits.PTD7

#define PTD_PTD0_MASK                   1
#define PTD_PTD1_MASK                   2
#define PTD_PTD2_MASK                   4
#define PTD_PTD3_MASK                   8
#define PTD_PTD4_MASK                   16
#define PTD_PTD5_MASK                   32
#define PTD_PTD6_MASK                   64
#define PTD_PTD7_MASK                   128


/*** DDRA - Data Direction Register A; 0x00000004 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRA0       :1;                                       /* Data Direction Register A Bit 0 */
    byte DDRA1       :1;                                       /* Data Direction Register A Bit 1 */
    byte DDRA2       :1;                                       /* Data Direction Register A Bit 2 */
    byte DDRA3       :1;                                       /* Data Direction Register A Bit 3 */
    byte DDRA4       :1;                                       /* Data Direction Register A Bit 4 */
    byte DDRA5       :1;                                       /* Data Direction Register A Bit 5 */
    byte DDRA6       :1;                                       /* Data Direction Register A Bit 6 */
    byte DDRA7       :1;                                       /* Data Direction Register A Bit 7 */
  } Bits;
} DDRASTR;
extern volatile DDRASTR _DDRA;
#define DDRA                            _DDRA.Byte
#define DDRA_DDRA0                      _DDRA.Bits.DDRA0
#define DDRA_DDRA1                      _DDRA.Bits.DDRA1
#define DDRA_DDRA2                      _DDRA.Bits.DDRA2
#define DDRA_DDRA3                      _DDRA.Bits.DDRA3
#define DDRA_DDRA4                      _DDRA.Bits.DDRA4
#define DDRA_DDRA5                      _DDRA.Bits.DDRA5
#define DDRA_DDRA6                      _DDRA.Bits.DDRA6
#define DDRA_DDRA7                      _DDRA.Bits.DDRA7

#define DDRA_DDRA0_MASK                 1
#define DDRA_DDRA1_MASK                 2
#define DDRA_DDRA2_MASK                 4
#define DDRA_DDRA3_MASK                 8
#define DDRA_DDRA4_MASK                 16
#define DDRA_DDRA5_MASK                 32
#define DDRA_DDRA6_MASK                 64
#define DDRA_DDRA7_MASK                 128


/*** DDRB - Data Direction Register B; 0x00000005 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRB0       :1;                                       /* Data Direction Register B Bit 0 */
    byte DDRB1       :1;                                       /* Data Direction Register B Bit 1 */
    byte DDRB2       :1;                                       /* Data Direction Register B Bit 2 */
    byte DDRB3       :1;                                       /* Data Direction Register B Bit 3 */
    byte DDRB4       :1;                                       /* Data Direction Register B Bit 4 */
    byte DDRB5       :1;                                       /* Data Direction Register B Bit 5 */
    byte DDRB6       :1;                                       /* Data Direction Register B Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpDDRB :7;
    byte         :1;
  } MergedBits;
} DDRBSTR;
extern volatile DDRBSTR _DDRB;
#define DDRB                            _DDRB.Byte
#define DDRB_DDRB0                      _DDRB.Bits.DDRB0
#define DDRB_DDRB1                      _DDRB.Bits.DDRB1
#define DDRB_DDRB2                      _DDRB.Bits.DDRB2
#define DDRB_DDRB3                      _DDRB.Bits.DDRB3
#define DDRB_DDRB4                      _DDRB.Bits.DDRB4
#define DDRB_DDRB5                      _DDRB.Bits.DDRB5
#define DDRB_DDRB6                      _DDRB.Bits.DDRB6
#define DDRB_DDRB                       _DDRB.MergedBits.grpDDRB

#define DDRB_DDRB0_MASK                 1
#define DDRB_DDRB1_MASK                 2
#define DDRB_DDRB2_MASK                 4
#define DDRB_DDRB3_MASK                 8
#define DDRB_DDRB4_MASK                 16
#define DDRB_DDRB5_MASK                 32
#define DDRB_DDRB6_MASK                 64
#define DDRB_DDRB_MASK                  127
#define DDRB_DDRB_BITNUM                0


/*** DDRC - Data Direction Register C; 0x00000006 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRC0       :1;                                       /* Data Direction Register C Bit 0 */
    byte DDRC1       :1;                                       /* Data Direction Register C Bit 1 */
    byte DDRC2       :1;                                       /* Data Direction Register C Bit 2 */
    byte DDRC3       :1;                                       /* Data Direction Register C Bit 3 */
    byte DDRC4       :1;                                       /* Data Direction Register C Bit 4 */
    byte DDRC5       :1;                                       /* Data Direction Register C Bit 5 */
    byte DDRC6       :1;                                       /* Data Direction Register C Bit 6 */
    byte DDRC7       :1;                                       /* Data Direction Register C Bit 7 */
  } Bits;
} DDRCSTR;
extern volatile DDRCSTR _DDRC;
#define DDRC                            _DDRC.Byte
#define DDRC_DDRC0                      _DDRC.Bits.DDRC0
#define DDRC_DDRC1                      _DDRC.Bits.DDRC1
#define DDRC_DDRC2                      _DDRC.Bits.DDRC2
#define DDRC_DDRC3                      _DDRC.Bits.DDRC3
#define DDRC_DDRC4                      _DDRC.Bits.DDRC4
#define DDRC_DDRC5                      _DDRC.Bits.DDRC5
#define DDRC_DDRC6                      _DDRC.Bits.DDRC6
#define DDRC_DDRC7                      _DDRC.Bits.DDRC7

#define DDRC_DDRC0_MASK                 1
#define DDRC_DDRC1_MASK                 2
#define DDRC_DDRC2_MASK                 4
#define DDRC_DDRC3_MASK                 8
#define DDRC_DDRC4_MASK                 16
#define DDRC_DDRC5_MASK                 32
#define DDRC_DDRC6_MASK                 64
#define DDRC_DDRC7_MASK                 128


/*** DDRD - Data Direction Register D; 0x00000007 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRD0       :1;                                       /* Data Direction Register D Bit 0 */
    byte DDRD1       :1;                                       /* Data Direction Register D Bit 1 */
    byte DDRD2       :1;                                       /* Data Direction Register D Bit 2 */
    byte DDRD3       :1;                                       /* Data Direction Register D Bit 3 */
    byte DDRD4       :1;                                       /* Data Direction Register D Bit 4 */
    byte DDRD5       :1;                                       /* Data Direction Register D Bit 5 */
    byte DDRD6       :1;                                       /* Data Direction Register D Bit 6 */
    byte DDRD7       :1;                                       /* Data Direction Register D Bit 7 */
  } Bits;
} DDRDSTR;
extern volatile DDRDSTR _DDRD;
#define DDRD                            _DDRD.Byte
#define DDRD_DDRD0                      _DDRD.Bits.DDRD0
#define DDRD_DDRD1                      _DDRD.Bits.DDRD1
#define DDRD_DDRD2                      _DDRD.Bits.DDRD2
#define DDRD_DDRD3                      _DDRD.Bits.DDRD3
#define DDRD_DDRD4                      _DDRD.Bits.DDRD4
#define DDRD_DDRD5                      _DDRD.Bits.DDRD5
#define DDRD_DDRD6                      _DDRD.Bits.DDRD6
#define DDRD_DDRD7                      _DDRD.Bits.DDRD7

#define DDRD_DDRD0_MASK                 1
#define DDRD_DDRD1_MASK                 2
#define DDRD_DDRD2_MASK                 4
#define DDRD_DDRD3_MASK                 8
#define DDRD_DDRD4_MASK                 16
#define DDRD_DDRD5_MASK                 32
#define DDRD_DDRD6_MASK                 64
#define DDRD_DDRD7_MASK                 128


/*** LEDA - Port-A LED Control; 0x0000000C ***/
typedef union {
  byte Byte;
  struct {
    byte LEDA0       :1;                                       /* Port A LED Drive Enable Bit 0 */
    byte LEDA1       :1;                                       /* Port A LED Drive Enable Bit 1 */
    byte LEDA2       :1;                                       /* Port A LED Drive Enable Bit 2 */
    byte LEDA3       :1;                                       /* Port A LED Drive Enable Bit 3 */
    byte LEDA4       :1;                                       /* Port A LED Drive Enable Bit 4 */
    byte LEDA5       :1;                                       /* Port A LED Drive Enable Bit 5 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpLEDA :6;
    byte         :1;
    byte         :1;
  } MergedBits;
} LEDASTR;
extern volatile LEDASTR _LEDA;
#define LEDA                            _LEDA.Byte
#define LEDA_LEDA0                      _LEDA.Bits.LEDA0
#define LEDA_LEDA1                      _LEDA.Bits.LEDA1
#define LEDA_LEDA2                      _LEDA.Bits.LEDA2
#define LEDA_LEDA3                      _LEDA.Bits.LEDA3
#define LEDA_LEDA4                      _LEDA.Bits.LEDA4
#define LEDA_LEDA5                      _LEDA.Bits.LEDA5
#define LEDA_LEDA                       _LEDA.MergedBits.grpLEDA

#define LEDA_LEDA0_MASK                 1
#define LEDA_LEDA1_MASK                 2
#define LEDA_LEDA2_MASK                 4
#define LEDA_LEDA3_MASK                 8
#define LEDA_LEDA4_MASK                 16
#define LEDA_LEDA5_MASK                 32
#define LEDA_LEDA_MASK                  63
#define LEDA_LEDA_BITNUM                0


/*** LEDC - Port-C LED Control; 0x0000000D ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte LEDC3       :1;                                       /* Port C LED Drive Enable Bit 3 */
    byte LEDC4       :1;                                       /* Port C LED Drive Enable Bit 4 */
    byte LEDC5       :1;                                       /* Port C LED Drive Enable Bit 5 */
    byte LEDC6       :1;                                       /* Port C LED Drive Enable Bit 6 */
    byte LEDC7       :1;                                       /* Port C LED Drive Enable Bit 7 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpLEDC_3 :5;
  } MergedBits;
} LEDCSTR;
extern volatile LEDCSTR _LEDC;
#define LEDC                            _LEDC.Byte
#define LEDC_LEDC3                      _LEDC.Bits.LEDC3
#define LEDC_LEDC4                      _LEDC.Bits.LEDC4
#define LEDC_LEDC5                      _LEDC.Bits.LEDC5
#define LEDC_LEDC6                      _LEDC.Bits.LEDC6
#define LEDC_LEDC7                      _LEDC.Bits.LEDC7
#define LEDC_LEDC_3                     _LEDC.MergedBits.grpLEDC_3

#define LEDC_LEDC3_MASK                 8
#define LEDC_LEDC4_MASK                 16
#define LEDC_LEDC5_MASK                 32
#define LEDC_LEDC6_MASK                 64
#define LEDC_LEDC7_MASK                 128
#define LEDC_LEDC_3_MASK                248
#define LEDC_LEDC_3_BITNUM              3


/*** AMCR - Analog Module Control; 0x0000000E ***/
typedef union {
  byte Byte;
  struct {
    byte DO0         :1;                                       /* DC Offset Control Bit 0 */
    byte DO1         :1;                                       /* DC Offset Control Bit 1 */
    byte DO2         :1;                                       /* DC Offset Control Bit 2 */
    byte AMIEN       :1;                                       /* Analog Module Interrupt Enable */
    byte OPCH0       :1;                                       /* Amplifier Channel Select Control Bit 0 */
    byte OPCH1       :1;                                       /* Amplifier Channel Select Control Bit 1 */
    byte PWR0        :1;                                       /* Analog Module Power Control Bit 0 */
    byte PWR1        :1;                                       /* Analog Module Power Control Bit 1 */
  } Bits;
  struct {
    byte grpDO   :3;
    byte         :1;
    byte grpOPCH :2;
    byte grpPWR  :2;
  } MergedBits;
} AMCRSTR;
extern volatile AMCRSTR _AMCR;
#define AMCR                            _AMCR.Byte
#define AMCR_DO0                        _AMCR.Bits.DO0
#define AMCR_DO1                        _AMCR.Bits.DO1
#define AMCR_DO2                        _AMCR.Bits.DO2
#define AMCR_AMIEN                      _AMCR.Bits.AMIEN
#define AMCR_OPCH0                      _AMCR.Bits.OPCH0
#define AMCR_OPCH1                      _AMCR.Bits.OPCH1
#define AMCR_PWR0                       _AMCR.Bits.PWR0
#define AMCR_PWR1                       _AMCR.Bits.PWR1
#define AMCR_DO                         _AMCR.MergedBits.grpDO
#define AMCR_OPCH                       _AMCR.MergedBits.grpOPCH
#define AMCR_PWR                        _AMCR.MergedBits.grpPWR

#define AMCR_DO0_MASK                   1
#define AMCR_DO1_MASK                   2
#define AMCR_DO2_MASK                   4
#define AMCR_AMIEN_MASK                 8
#define AMCR_OPCH0_MASK                 16
#define AMCR_OPCH1_MASK                 32
#define AMCR_PWR0_MASK                  64
#define AMCR_PWR1_MASK                  128
#define AMCR_DO_MASK                    7
#define AMCR_DO_BITNUM                  0
#define AMCR_OPCH_MASK                  48
#define AMCR_OPCH_BITNUM                4
#define AMCR_PWR_MASK                   192
#define AMCR_PWR_BITNUM                 6


/*** AMGCR - Analog Module Gain Control Register; 0x0000000F ***/
typedef union {
  byte Byte;
  struct {
    byte GAINA0      :1;                                       /* Analog Module 1nd-stage Gain Control Bit 0 */
    byte GAINA1      :1;                                       /* Analog Module 1nd-stage Gain Control Bit 1 */
    byte GAINA2      :1;                                       /* Analog Module 1nd-stage Gain Control Bit 2 */
    byte GAINA3      :1;                                       /* Analog Module 1nd-stage Gain Control Bit 3 */
    byte GAINB0      :1;                                       /* Analog Module 2nd-stage Gain Control Bit 0 */
    byte GAINB1      :1;                                       /* Analog Module 2nd-stage Gain Control Bit 1 */
    byte GAINB2      :1;                                       /* Analog Module 2nd-stage Gain Control Bit 2 */
    byte GAINB3      :1;                                       /* Analog Module 2nd-stage Gain Control Bit 3 */
  } Bits;
  struct {
    byte grpGAINA :4;
    byte grpGAINB :4;
  } MergedBits;
} AMGCRSTR;
extern volatile AMGCRSTR _AMGCR;
#define AMGCR                           _AMGCR.Byte
#define AMGCR_GAINA0                    _AMGCR.Bits.GAINA0
#define AMGCR_GAINA1                    _AMGCR.Bits.GAINA1
#define AMGCR_GAINA2                    _AMGCR.Bits.GAINA2
#define AMGCR_GAINA3                    _AMGCR.Bits.GAINA3
#define AMGCR_GAINB0                    _AMGCR.Bits.GAINB0
#define AMGCR_GAINB1                    _AMGCR.Bits.GAINB1
#define AMGCR_GAINB2                    _AMGCR.Bits.GAINB2
#define AMGCR_GAINB3                    _AMGCR.Bits.GAINB3
#define AMGCR_GAINA                     _AMGCR.MergedBits.grpGAINA
#define AMGCR_GAINB                     _AMGCR.MergedBits.grpGAINB

#define AMGCR_GAINA0_MASK               1
#define AMGCR_GAINA1_MASK               2
#define AMGCR_GAINA2_MASK               4
#define AMGCR_GAINA3_MASK               8
#define AMGCR_GAINB0_MASK               16
#define AMGCR_GAINB1_MASK               32
#define AMGCR_GAINB2_MASK               64
#define AMGCR_GAINB3_MASK               128
#define AMGCR_GAINA_MASK                15
#define AMGCR_GAINA_BITNUM              0
#define AMGCR_GAINB_MASK                240
#define AMGCR_GAINB_BITNUM              4


/*** AMSCR - Analog Module Status and Control Register; 0x00000010 ***/
typedef union {
  byte Byte;
  struct {
    byte CDIF        :1;                                       /* Current Detect Interrupt Flag */
    byte CDIFR       :1;                                       /* Current Detect Interrupt Flag Reset */
    byte DOF         :1;                                       /* DC Offset Flag */
    byte             :1; 
    byte OPIF        :1;                                       /* Amplifier Ready Interrupt Flag */
    byte OPIFR       :1;                                       /* Amplifier Ready Interrupt Flag Reset */
    byte AMCDIV0     :1;                                       /* Analog Module Clock Divider Control Bit 0 */
    byte AMCDIV1     :1;                                       /* Analog Module Clock Divider Control Bit 1 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpAMCDIV :2;
  } MergedBits;
} AMSCRSTR;
extern volatile AMSCRSTR _AMSCR;
#define AMSCR                           _AMSCR.Byte
#define AMSCR_CDIF                      _AMSCR.Bits.CDIF
#define AMSCR_CDIFR                     _AMSCR.Bits.CDIFR
#define AMSCR_DOF                       _AMSCR.Bits.DOF
#define AMSCR_OPIF                      _AMSCR.Bits.OPIF
#define AMSCR_OPIFR                     _AMSCR.Bits.OPIFR
#define AMSCR_AMCDIV0                   _AMSCR.Bits.AMCDIV0
#define AMSCR_AMCDIV1                   _AMSCR.Bits.AMCDIV1
#define AMSCR_AMCDIV                    _AMSCR.MergedBits.grpAMCDIV

#define AMSCR_CDIF_MASK                 1
#define AMSCR_CDIFR_MASK                2
#define AMSCR_DOF_MASK                  4
#define AMSCR_OPIF_MASK                 16
#define AMSCR_OPIFR_MASK                32
#define AMSCR_AMCDIV0_MASK              64
#define AMSCR_AMCDIV1_MASK              128
#define AMSCR_AMCDIV_MASK               192
#define AMSCR_AMCDIV_BITNUM             6


/*** SCC1 - SCI Control Register 1; 0x00000013 ***/
typedef union {
  byte Byte;
  struct {
    byte PTY         :1;                                       /* Parity Bit */
    byte PEN         :1;                                       /* Parity Enable Bit */
    byte ILTY        :1;                                       /* Idle Line Type Bit */
    byte WAKE        :1;                                       /* Wakeup Condition Bit */
    byte M           :1;                                       /* Mode (Character Length) Bit */
    byte TXINV       :1;                                       /* Transmit Inversion Bit */
    byte ENSCI       :1;                                       /* Enable SCI Bit */
    byte LOOPS       :1;                                       /* Loop Mode Select Bit */
  } Bits;
} SCC1STR;
extern volatile SCC1STR _SCC1;
#define SCC1                            _SCC1.Byte
#define SCC1_PTY                        _SCC1.Bits.PTY
#define SCC1_PEN                        _SCC1.Bits.PEN
#define SCC1_ILTY                       _SCC1.Bits.ILTY
#define SCC1_WAKE                       _SCC1.Bits.WAKE
#define SCC1_M                          _SCC1.Bits.M
#define SCC1_TXINV                      _SCC1.Bits.TXINV
#define SCC1_ENSCI                      _SCC1.Bits.ENSCI
#define SCC1_LOOPS                      _SCC1.Bits.LOOPS

#define SCC1_PTY_MASK                   1
#define SCC1_PEN_MASK                   2
#define SCC1_ILTY_MASK                  4
#define SCC1_WAKE_MASK                  8
#define SCC1_M_MASK                     16
#define SCC1_TXINV_MASK                 32
#define SCC1_ENSCI_MASK                 64
#define SCC1_LOOPS_MASK                 128


/*** SCC2 - SCI Control Register 2; 0x00000014 ***/
typedef union {
  byte Byte;
  struct {
    byte SBK         :1;                                       /* Send Break Bit */
    byte RWU         :1;                                       /* Receiver Wakeup Bit */
    byte RE          :1;                                       /* Receiver Enable Bit */
    byte TE          :1;                                       /* Transmitter Enable Bit */
    byte ILIE        :1;                                       /* Idle Line Interrupt Enable Bit */
    byte SCRIE       :1;                                       /* SCI Receive Interrupt Enable Bit */
    byte TCIE        :1;                                       /* Transmission Complete Interrupt Enable Bit */
    byte SCTIE       :1;                                       /* SCI Transmit Interrupt Enable Bit */
  } Bits;
} SCC2STR;
extern volatile SCC2STR _SCC2;
#define SCC2                            _SCC2.Byte
#define SCC2_SBK                        _SCC2.Bits.SBK
#define SCC2_RWU                        _SCC2.Bits.RWU
#define SCC2_RE                         _SCC2.Bits.RE
#define SCC2_TE                         _SCC2.Bits.TE
#define SCC2_ILIE                       _SCC2.Bits.ILIE
#define SCC2_SCRIE                      _SCC2.Bits.SCRIE
#define SCC2_TCIE                       _SCC2.Bits.TCIE
#define SCC2_SCTIE                      _SCC2.Bits.SCTIE

#define SCC2_SBK_MASK                   1
#define SCC2_RWU_MASK                   2
#define SCC2_RE_MASK                    4
#define SCC2_TE_MASK                    8
#define SCC2_ILIE_MASK                  16
#define SCC2_SCRIE_MASK                 32
#define SCC2_TCIE_MASK                  64
#define SCC2_SCTIE_MASK                 128


/*** SCC3 - SCI Control Register 3; 0x00000015 ***/
typedef union {
  byte Byte;
  struct {
    byte PEIE        :1;                                       /* Receiver Parity Error Interrupt Enable Bit */
    byte FEIE        :1;                                       /* Receiver Framing Error Interrupt Enable Bit */
    byte NEIE        :1;                                       /* Receiver Noise Error Interrupt Enable Bit */
    byte ORIE        :1;                                       /* Receiver Overrun Interrupt Enable Bit */
    byte             :1; 
    byte             :1; 
    byte T8          :1;                                       /* Transmitted Bit 8 */
    byte R8          :1;                                       /* Received Bit 8 */
  } Bits;
} SCC3STR;
extern volatile SCC3STR _SCC3;
#define SCC3                            _SCC3.Byte
#define SCC3_PEIE                       _SCC3.Bits.PEIE
#define SCC3_FEIE                       _SCC3.Bits.FEIE
#define SCC3_NEIE                       _SCC3.Bits.NEIE
#define SCC3_ORIE                       _SCC3.Bits.ORIE
#define SCC3_T8                         _SCC3.Bits.T8
#define SCC3_R8                         _SCC3.Bits.R8

#define SCC3_PEIE_MASK                  1
#define SCC3_FEIE_MASK                  2
#define SCC3_NEIE_MASK                  4
#define SCC3_ORIE_MASK                  8
#define SCC3_T8_MASK                    64
#define SCC3_R8_MASK                    128


/*** SCS1 - SCI Status Register 1; 0x00000016 ***/
typedef union {
  byte Byte;
  struct {
    byte PE          :1;                                       /* Receiver Parity Error Bit */
    byte FE          :1;                                       /* Receiver Framing Error Bit */
    byte NF          :1;                                       /* Receiver Noise Flag Bit */
    byte OR          :1;                                       /* Receiver Overrun Bit */
    byte IDLE        :1;                                       /* Receiver Idle Bit */
    byte SCRF        :1;                                       /* SCI Receiver Full Bit */
    byte TC          :1;                                       /* Transmission Complete Bit */
    byte SCTE        :1;                                       /* SCI Transmitter Empty Bit */
  } Bits;
} SCS1STR;
extern volatile SCS1STR _SCS1;
#define SCS1                            _SCS1.Byte
#define SCS1_PE                         _SCS1.Bits.PE
#define SCS1_FE                         _SCS1.Bits.FE
#define SCS1_NF                         _SCS1.Bits.NF
#define SCS1_OR                         _SCS1.Bits.OR
#define SCS1_IDLE                       _SCS1.Bits.IDLE
#define SCS1_SCRF                       _SCS1.Bits.SCRF
#define SCS1_TC                         _SCS1.Bits.TC
#define SCS1_SCTE                       _SCS1.Bits.SCTE

#define SCS1_PE_MASK                    1
#define SCS1_FE_MASK                    2
#define SCS1_NF_MASK                    4
#define SCS1_OR_MASK                    8
#define SCS1_IDLE_MASK                  16
#define SCS1_SCRF_MASK                  32
#define SCS1_TC_MASK                    64
#define SCS1_SCTE_MASK                  128


/*** SCS2 - SCI Status Register 2; 0x00000017 ***/
typedef union {
  byte Byte;
  struct {
    byte RPF         :1;                                       /* Reception in Progress Flag Bit */
    byte BKF         :1;                                       /* Break Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SCS2STR;
extern volatile SCS2STR _SCS2;
#define SCS2                            _SCS2.Byte
#define SCS2_RPF                        _SCS2.Bits.RPF
#define SCS2_BKF                        _SCS2.Bits.BKF

#define SCS2_RPF_MASK                   1
#define SCS2_BKF_MASK                   2


/*** SCDR - SCI Data Register; 0x00000018 ***/
typedef union {
  byte Byte;
  struct {
    byte R0_T0       :1;                                       /* Receive/Transmit Data Bit 0 */
    byte R1_T1       :1;                                       /* Receive/Transmit Data Bit 1 */
    byte R2_T2       :1;                                       /* Receive/Transmit Data Bit 2 */
    byte R3_T3       :1;                                       /* Receive/Transmit Data Bit 3 */
    byte R4_T4       :1;                                       /* Receive/Transmit Data Bit 4 */
    byte R5_T5       :1;                                       /* Receive/Transmit Data Bit 5 */
    byte R6_T6       :1;                                       /* Receive/Transmit Data Bit 6 */
    byte R7_T7       :1;                                       /* Receive/Transmit Data Bit 7 */
  } Bits;
} SCDRSTR;
extern volatile SCDRSTR _SCDR;
#define SCDR                            _SCDR.Byte
#define SCDR_R0_T0                      _SCDR.Bits.R0_T0
#define SCDR_R1_T1                      _SCDR.Bits.R1_T1
#define SCDR_R2_T2                      _SCDR.Bits.R2_T2
#define SCDR_R3_T3                      _SCDR.Bits.R3_T3
#define SCDR_R4_T4                      _SCDR.Bits.R4_T4
#define SCDR_R5_T5                      _SCDR.Bits.R5_T5
#define SCDR_R6_T6                      _SCDR.Bits.R6_T6
#define SCDR_R7_T7                      _SCDR.Bits.R7_T7

#define SCDR_R0_T0_MASK                 1
#define SCDR_R1_T1_MASK                 2
#define SCDR_R2_T2_MASK                 4
#define SCDR_R3_T3_MASK                 8
#define SCDR_R4_T4_MASK                 16
#define SCDR_R5_T5_MASK                 32
#define SCDR_R6_T6_MASK                 64
#define SCDR_R7_T7_MASK                 128


/*** SCBR - SCI Baud Rate Register; 0x00000019 ***/
typedef union {
  byte Byte;
  struct {
    byte SCR0        :1;                                       /* SCI Baud Rate Select Bit 0 */
    byte SCR1        :1;                                       /* SCI Baud Rate Select Bit 1 */
    byte SCR2        :1;                                       /* SCI Baud Rate Select Bit 2 */
    byte             :1; 
    byte SCP0        :1;                                       /* SCI Baud Rate Prescaler Bit 0 */
    byte SCP1        :1;                                       /* SCI Baud Rate Prescaler Bit 1 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpSCR  :3;
    byte         :1;
    byte grpSCP  :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} SCBRSTR;
extern volatile SCBRSTR _SCBR;
#define SCBR                            _SCBR.Byte
#define SCBR_SCR0                       _SCBR.Bits.SCR0
#define SCBR_SCR1                       _SCBR.Bits.SCR1
#define SCBR_SCR2                       _SCBR.Bits.SCR2
#define SCBR_SCP0                       _SCBR.Bits.SCP0
#define SCBR_SCP1                       _SCBR.Bits.SCP1
#define SCBR_SCR                        _SCBR.MergedBits.grpSCR
#define SCBR_SCP                        _SCBR.MergedBits.grpSCP

#define SCBR_SCR0_MASK                  1
#define SCBR_SCR1_MASK                  2
#define SCBR_SCR2_MASK                  4
#define SCBR_SCP0_MASK                  16
#define SCBR_SCP1_MASK                  32
#define SCBR_SCR_MASK                   7
#define SCBR_SCR_BITNUM                 0
#define SCBR_SCP_MASK                   48
#define SCBR_SCP_BITNUM                 4


/*** KBSCR - Keyboard Status and Control Register; 0x0000001A ***/
typedef union {
  byte Byte;
  struct {
    byte MODEK       :1;                                       /* Keyboard Triggering Sensitivity Bit */
    byte IMASKK      :1;                                       /* Keyboard Interrupt Mask Bit */
    byte ACKK        :1;                                       /* Keyboard Acknowledge Bit */
    byte KEYF        :1;                                       /* Keyboard Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} KBSCRSTR;
extern volatile KBSCRSTR _KBSCR;
#define KBSCR                           _KBSCR.Byte
#define KBSCR_MODEK                     _KBSCR.Bits.MODEK
#define KBSCR_IMASKK                    _KBSCR.Bits.IMASKK
#define KBSCR_ACKK                      _KBSCR.Bits.ACKK
#define KBSCR_KEYF                      _KBSCR.Bits.KEYF

#define KBSCR_MODEK_MASK                1
#define KBSCR_IMASKK_MASK               2
#define KBSCR_ACKK_MASK                 4
#define KBSCR_KEYF_MASK                 8


/*** KBIER - Keyobard Interrupt Enable Register; 0x0000001B ***/
typedef union {
  byte Byte;
  struct {
    byte KBIE0       :1;                                       /* Keyboard Interrut Enable Bit */
    byte KBIE1       :1;                                       /* Keyboard Interrut Enable Bit */
    byte KBIE2       :1;                                       /* Keyboard Interrut Enable Bit */
    byte KBIE3       :1;                                       /* Keyboard Interrut Enable Bit */
    byte KBIE4       :1;                                       /* Keyboard Interrut Enable Bit */
    byte KBIE5       :1;                                       /* Keyboard Interrut Enable Bit */
    byte KBIE6       :1;                                       /* Keyboard Interrut Enable Bit */
    byte KBIE7       :1;                                       /* Keyboard Interrut Enable Bit */
  } Bits;
} KBIERSTR;
extern volatile KBIERSTR _KBIER;
#define KBIER                           _KBIER.Byte
#define KBIER_KBIE0                     _KBIER.Bits.KBIE0
#define KBIER_KBIE1                     _KBIER.Bits.KBIE1
#define KBIER_KBIE2                     _KBIER.Bits.KBIE2
#define KBIER_KBIE3                     _KBIER.Bits.KBIE3
#define KBIER_KBIE4                     _KBIER.Bits.KBIE4
#define KBIER_KBIE5                     _KBIER.Bits.KBIE5
#define KBIER_KBIE6                     _KBIER.Bits.KBIE6
#define KBIER_KBIE7                     _KBIER.Bits.KBIE7

#define KBIER_KBIE0_MASK                1
#define KBIER_KBIE1_MASK                2
#define KBIER_KBIE2_MASK                4
#define KBIER_KBIE3_MASK                8
#define KBIER_KBIE4_MASK                16
#define KBIER_KBIE5_MASK                32
#define KBIER_KBIE6_MASK                64
#define KBIER_KBIE7_MASK                128


/*** INTSCR2 - IRQ2 Status and Control Register; 0x0000001C ***/
typedef union {
  byte Byte;
  struct {
    byte MODE2       :1;                                       /* IRQ2 Edge/Level Select Bit */
    byte IMASK2      :1;                                       /* IRQ2 Interrupt Mask Bit */
    byte ACK2        :1;                                       /* IRQ2 Interrupt Request Acknowledge Bit */
    byte IRQ2F       :1;                                       /* IRQ2 Flag Bit */
    byte             :1; 
    byte             :1; 
    byte PTBPUE6     :1;                                       /* IRQ2 Pin Pullup Enable Bit */
    byte             :1; 
  } Bits;
} INTSCR2STR;
extern volatile INTSCR2STR _INTSCR2;
#define INTSCR2                         _INTSCR2.Byte
#define INTSCR2_MODE2                   _INTSCR2.Bits.MODE2
#define INTSCR2_IMASK2                  _INTSCR2.Bits.IMASK2
#define INTSCR2_ACK2                    _INTSCR2.Bits.ACK2
#define INTSCR2_IRQ2F                   _INTSCR2.Bits.IRQ2F
#define INTSCR2_PTBPUE6                 _INTSCR2.Bits.PTBPUE6

#define INTSCR2_MODE2_MASK              1
#define INTSCR2_IMASK2_MASK             2
#define INTSCR2_ACK2_MASK               4
#define INTSCR2_IRQ2F_MASK              8
#define INTSCR2_PTBPUE6_MASK            64


/*** CONFIG2 - Configuration Register 2; 0x0000001D ***/
typedef union {
  byte Byte;
  struct {
    byte SCIBDSRC    :1;                                       /* SCI Baud Rate Clock Source Bit */
    byte CDOEN       :1;                                       /* Current-Flow Detect Output Enable */
    byte             :1; 
    byte OSCCLK0     :1;                                       /* Oscillator Output Control Bit 0 */
    byte OSCCLK1     :1;                                       /* Oscillator Output Control Bit 1 */
    byte STOPXCLKEN  :1;                                       /* Crystal Oscillator Stop Mode Enable */
    byte STOPRCLKEN  :1;                                       /* RC Oscillator Stop Mode Enable */
    byte STOPICLKEN  :1;                                       /* Internal Oscillator Stop Mode Enable */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpOSCCLK :2;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CONFIG2STR;
extern volatile CONFIG2STR _CONFIG2;
#define CONFIG2                         _CONFIG2.Byte
#define CONFIG2_SCIBDSRC                _CONFIG2.Bits.SCIBDSRC
#define CONFIG2_CDOEN                   _CONFIG2.Bits.CDOEN
#define CONFIG2_OSCCLK0                 _CONFIG2.Bits.OSCCLK0
#define CONFIG2_OSCCLK1                 _CONFIG2.Bits.OSCCLK1
#define CONFIG2_STOPXCLKEN              _CONFIG2.Bits.STOPXCLKEN
#define CONFIG2_STOPRCLKEN              _CONFIG2.Bits.STOPRCLKEN
#define CONFIG2_STOPICLKEN              _CONFIG2.Bits.STOPICLKEN
#define CONFIG2_OSCCLK                  _CONFIG2.MergedBits.grpOSCCLK

#define CONFIG2_SCIBDSRC_MASK           1
#define CONFIG2_CDOEN_MASK              2
#define CONFIG2_OSCCLK0_MASK            8
#define CONFIG2_OSCCLK1_MASK            16
#define CONFIG2_STOPXCLKEN_MASK         32
#define CONFIG2_STOPRCLKEN_MASK         64
#define CONFIG2_STOPICLKEN_MASK         128
#define CONFIG2_OSCCLK_MASK             24
#define CONFIG2_OSCCLK_BITNUM           3


/*** INTSCR1 - IRQ1 Status and Control Register; 0x0000001E ***/
typedef union {
  byte Byte;
  struct {
    byte MODE1       :1;                                       /* IRQ1 Edge/Level Select Bit */
    byte IMASK1      :1;                                       /* IRQ1 Interrupt Mask Bit */
    byte ACK1        :1;                                       /* IRQ1 Interrupt Request Acknowledge Bit */
    byte IRQ1F       :1;                                       /* IRQ1 Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} INTSCR1STR;
extern volatile INTSCR1STR _INTSCR1;
#define INTSCR1                         _INTSCR1.Byte
#define INTSCR1_MODE1                   _INTSCR1.Bits.MODE1
#define INTSCR1_IMASK1                  _INTSCR1.Bits.IMASK1
#define INTSCR1_ACK1                    _INTSCR1.Bits.ACK1
#define INTSCR1_IRQ1F                   _INTSCR1.Bits.IRQ1F

#define INTSCR1_MODE1_MASK              1
#define INTSCR1_IMASK1_MASK             2
#define INTSCR1_ACK1_MASK               4
#define INTSCR1_IRQ1F_MASK              8


/*** CONFIG1 - Configuration Register 1; 0x0000001F ***/
typedef union {
  byte Byte;
  struct {
    byte COPD        :1;                                       /* COP Disable Bit */
    byte STOP        :1;                                       /* STOP Instruction Enable Bit */
    byte SSREC       :1;                                       /* Short Stop Recovery Bit */
    byte LVI5OR3     :1;                                       /* LVI 5-V or 3-V Operating Mode Bit */
    byte LVIPWRD     :1;                                       /* LVI Power Disable Bit */
    byte LVIRSTD     :1;                                       /* LVI Reset Disable Bit */
    byte LVISTOP     :1;                                       /* LVI Enable in Stop Mode Bit */
    byte COPRS       :1;                                       /* COP rate Select Bit */
  } Bits;
} CONFIG1STR;
extern volatile CONFIG1STR _CONFIG1;
#define CONFIG1                         _CONFIG1.Byte
#define CONFIG1_COPD                    _CONFIG1.Bits.COPD
#define CONFIG1_STOP                    _CONFIG1.Bits.STOP
#define CONFIG1_SSREC                   _CONFIG1.Bits.SSREC
#define CONFIG1_LVI5OR3                 _CONFIG1.Bits.LVI5OR3
#define CONFIG1_LVIPWRD                 _CONFIG1.Bits.LVIPWRD
#define CONFIG1_LVIRSTD                 _CONFIG1.Bits.LVIRSTD
#define CONFIG1_LVISTOP                 _CONFIG1.Bits.LVISTOP
#define CONFIG1_COPRS                   _CONFIG1.Bits.COPRS

#define CONFIG1_COPD_MASK               1
#define CONFIG1_STOP_MASK               2
#define CONFIG1_SSREC_MASK              4
#define CONFIG1_LVI5OR3_MASK            8
#define CONFIG1_LVIPWRD_MASK            16
#define CONFIG1_LVIRSTD_MASK            32
#define CONFIG1_LVISTOP_MASK            64
#define CONFIG1_COPRS_MASK              128


/*** T1SC - TIM1 Status and Control Register; 0x00000020 ***/
typedef union {
  byte Byte;
  struct {
    byte PS0         :1;                                       /* Prescaler Select Bit 0 */
    byte PS1         :1;                                       /* Prescaler Select Bit 1 */
    byte PS2         :1;                                       /* Prescaler Select Bit 2 */
    byte             :1; 
    byte TRST        :1;                                       /* TIM1 Reset Bit */
    byte TSTOP       :1;                                       /* TIM1 Stop Bit */
    byte TOIE        :1;                                       /* TIM1 Overflow Interrupt Enable Bit */
    byte TOF         :1;                                       /* TIM1 Overflow Flag Bit */
  } Bits;
  struct {
    byte grpPS   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} T1SCSTR;
extern volatile T1SCSTR _T1SC;
#define T1SC                            _T1SC.Byte
#define T1SC_PS0                        _T1SC.Bits.PS0
#define T1SC_PS1                        _T1SC.Bits.PS1
#define T1SC_PS2                        _T1SC.Bits.PS2
#define T1SC_TRST                       _T1SC.Bits.TRST
#define T1SC_TSTOP                      _T1SC.Bits.TSTOP
#define T1SC_TOIE                       _T1SC.Bits.TOIE
#define T1SC_TOF                        _T1SC.Bits.TOF
#define T1SC_PS                         _T1SC.MergedBits.grpPS

#define T1SC_PS0_MASK                   1
#define T1SC_PS1_MASK                   2
#define T1SC_PS2_MASK                   4
#define T1SC_TRST_MASK                  16
#define T1SC_TSTOP_MASK                 32
#define T1SC_TOIE_MASK                  64
#define T1SC_TOF_MASK                   128
#define T1SC_PS_MASK                    7
#define T1SC_PS_BITNUM                  0


/*** T1CNT - TIM1 Counter Register; 0x00000021 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T1CNTH - TIM1 Counter Register; 0x00000021 ***/
    union {
      byte Byte;
    } T1CNTHSTR;
    #define T1CNTH                      _T1CNT.Overlap_STR.T1CNTHSTR.Byte
    

    /*** T1CNTL - TIM1 Counter Register; 0x00000022 ***/
    union {
      byte Byte;
    } T1CNTLSTR;
    #define T1CNTL                      _T1CNT.Overlap_STR.T1CNTLSTR.Byte
    
  } Overlap_STR;

} T1CNTSTR;
extern volatile T1CNTSTR _T1CNT;
#define T1CNT                           _T1CNT.Word


/*** T1MOD - TIM1 Counter Modulo Register; 0x00000023 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T1MODH - TIM1 Counter Modulo Register; 0x00000023 ***/
    union {
      byte Byte;
    } T1MODHSTR;
    #define T1MODH                      _T1MOD.Overlap_STR.T1MODHSTR.Byte
    

    /*** T1MODL - TIM1 Counter Modulo Register; 0x00000024 ***/
    union {
      byte Byte;
    } T1MODLSTR;
    #define T1MODL                      _T1MOD.Overlap_STR.T1MODLSTR.Byte
    
  } Overlap_STR;

} T1MODSTR;
extern volatile T1MODSTR _T1MOD;
#define T1MOD                           _T1MOD.Word


/*** T1SC0 - TIM1 Channel Status and Control Register; 0x00000025 ***/
typedef union {
  byte Byte;
  struct {
    byte CH0MAX      :1;                                       /* Channel 0 Maximum Duty Cycle Bit */
    byte TOV0        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS0A       :1;                                       /* Edge/Level Select Bit */
    byte ELS0B       :1;                                       /* Edge/Level Select Bit */
    byte MS0A        :1;                                       /* Mode Select Bit A */
    byte MS0B        :1;                                       /* Mode Select Bit B */
    byte CH0IE       :1;                                       /* Channel 0 Interrupt Enable Bit */
    byte CH0F        :1;                                       /* Channel 0 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV  :1;
    byte grpELS0x :2;
    byte grpMS0x :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} T1SC0STR;
extern volatile T1SC0STR _T1SC0;
#define T1SC0                           _T1SC0.Byte
#define T1SC0_CH0MAX                    _T1SC0.Bits.CH0MAX
#define T1SC0_TOV0                      _T1SC0.Bits.TOV0
#define T1SC0_ELS0A                     _T1SC0.Bits.ELS0A
#define T1SC0_ELS0B                     _T1SC0.Bits.ELS0B
#define T1SC0_MS0A                      _T1SC0.Bits.MS0A
#define T1SC0_MS0B                      _T1SC0.Bits.MS0B
#define T1SC0_CH0IE                     _T1SC0.Bits.CH0IE
#define T1SC0_CH0F                      _T1SC0.Bits.CH0F
#define T1SC0_ELS0x                     _T1SC0.MergedBits.grpELS0x
#define T1SC0_MS0x                      _T1SC0.MergedBits.grpMS0x

#define T1SC0_CH0MAX_MASK               1
#define T1SC0_TOV0_MASK                 2
#define T1SC0_ELS0A_MASK                4
#define T1SC0_ELS0B_MASK                8
#define T1SC0_MS0A_MASK                 16
#define T1SC0_MS0B_MASK                 32
#define T1SC0_CH0IE_MASK                64
#define T1SC0_CH0F_MASK                 128
#define T1SC0_ELS0x_MASK                12
#define T1SC0_ELS0x_BITNUM              2
#define T1SC0_MS0x_MASK                 48
#define T1SC0_MS0x_BITNUM               4


/*** T1CH0 - TIM1 Channel Register; 0x00000026 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T1CH0H - TIM1 Channel Register; 0x00000026 ***/
    union {
      byte Byte;
    } T1CH0HSTR;
    #define T1CH0H                      _T1CH0.Overlap_STR.T1CH0HSTR.Byte
    

    /*** T1CH0L - TIM1 Channel Register; 0x00000027 ***/
    union {
      byte Byte;
    } T1CH0LSTR;
    #define T1CH0L                      _T1CH0.Overlap_STR.T1CH0LSTR.Byte
    
  } Overlap_STR;

} T1CH0STR;
extern volatile T1CH0STR _T1CH0;
#define T1CH0                           _T1CH0.Word


/*** T1SC1 - TIM1 Channel Status and Control Register; 0x00000028 ***/
typedef union {
  byte Byte;
  struct {
    byte CH1MAX      :1;                                       /* Channel 1 Maximum Duty Cycle Bit */
    byte TOV1        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS1A       :1;                                       /* Edge/Level Select Bit */
    byte ELS1B       :1;                                       /* Edge/Level Select Bit */
    byte MS1A        :1;                                       /* Mode Select Bit A */
    byte             :1; 
    byte CH1IE       :1;                                       /* Channel 1 Interrupt Enable Bit */
    byte CH1F        :1;                                       /* Channel 1 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_1 :1;
    byte grpELS1x :2;
    byte grpMS1x :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} T1SC1STR;
extern volatile T1SC1STR _T1SC1;
#define T1SC1                           _T1SC1.Byte
#define T1SC1_CH1MAX                    _T1SC1.Bits.CH1MAX
#define T1SC1_TOV1                      _T1SC1.Bits.TOV1
#define T1SC1_ELS1A                     _T1SC1.Bits.ELS1A
#define T1SC1_ELS1B                     _T1SC1.Bits.ELS1B
#define T1SC1_MS1A                      _T1SC1.Bits.MS1A
#define T1SC1_CH1IE                     _T1SC1.Bits.CH1IE
#define T1SC1_CH1F                      _T1SC1.Bits.CH1F
#define T1SC1_ELS1x                     _T1SC1.MergedBits.grpELS1x

#define T1SC1_CH1MAX_MASK               1
#define T1SC1_TOV1_MASK                 2
#define T1SC1_ELS1A_MASK                4
#define T1SC1_ELS1B_MASK                8
#define T1SC1_MS1A_MASK                 16
#define T1SC1_CH1IE_MASK                64
#define T1SC1_CH1F_MASK                 128
#define T1SC1_ELS1x_MASK                12
#define T1SC1_ELS1x_BITNUM              2


/*** T1CH1 - TIM1 Channel Register; 0x00000029 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T1CH1H - TIM1 Channel Register; 0x00000029 ***/
    union {
      byte Byte;
    } T1CH1HSTR;
    #define T1CH1H                      _T1CH1.Overlap_STR.T1CH1HSTR.Byte
    

    /*** T1CH1L - TIM1 Channel Register; 0x0000002A ***/
    union {
      byte Byte;
    } T1CH1LSTR;
    #define T1CH1L                      _T1CH1.Overlap_STR.T1CH1LSTR.Byte
    
  } Overlap_STR;

} T1CH1STR;
extern volatile T1CH1STR _T1CH1;
#define T1CH1                           _T1CH1.Word


/*** T2SC - TIM2 Status and Control Register; 0x0000002B ***/
typedef union {
  byte Byte;
  struct {
    byte PS0         :1;                                       /* Prescaler Select Bit */
    byte PS1         :1;                                       /* Prescaler Select Bit */
    byte PS2         :1;                                       /* Prescaler Select Bit */
    byte             :1; 
    byte TRST        :1;                                       /* TIM2 Reset Bit */
    byte TSTOP       :1;                                       /* TIM2 Stop Bit */
    byte TOIE        :1;                                       /* TIM2 Overflow Interrupt Enable Bit */
    byte TOF         :1;                                       /* TIM2 Overflow Flag Bit */
  } Bits;
  struct {
    byte grpPS   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} T2SCSTR;
extern volatile T2SCSTR _T2SC;
#define T2SC                            _T2SC.Byte
#define T2SC_PS0                        _T2SC.Bits.PS0
#define T2SC_PS1                        _T2SC.Bits.PS1
#define T2SC_PS2                        _T2SC.Bits.PS2
#define T2SC_TRST                       _T2SC.Bits.TRST
#define T2SC_TSTOP                      _T2SC.Bits.TSTOP
#define T2SC_TOIE                       _T2SC.Bits.TOIE
#define T2SC_TOF                        _T2SC.Bits.TOF
#define T2SC_PS                         _T2SC.MergedBits.grpPS

#define T2SC_PS0_MASK                   1
#define T2SC_PS1_MASK                   2
#define T2SC_PS2_MASK                   4
#define T2SC_TRST_MASK                  16
#define T2SC_TSTOP_MASK                 32
#define T2SC_TOIE_MASK                  64
#define T2SC_TOF_MASK                   128
#define T2SC_PS_MASK                    7
#define T2SC_PS_BITNUM                  0


/*** T2CNT - TIM2 Counter Register; 0x0000002C ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T2CNTH - TIM2 Counter Register; 0x0000002C ***/
    union {
      byte Byte;
    } T2CNTHSTR;
    #define T2CNTH                      _T2CNT.Overlap_STR.T2CNTHSTR.Byte
    

    /*** T2CNTL - TIM2 Counter Register; 0x0000002D ***/
    union {
      byte Byte;
    } T2CNTLSTR;
    #define T2CNTL                      _T2CNT.Overlap_STR.T2CNTLSTR.Byte
    
  } Overlap_STR;

} T2CNTSTR;
extern volatile T2CNTSTR _T2CNT;
#define T2CNT                           _T2CNT.Word


/*** T2MOD - TIM2 Counter Modulo Register; 0x0000002E ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T2MODH - TIM2 Counter Modulo Register; 0x0000002E ***/
    union {
      byte Byte;
    } T2MODHSTR;
    #define T2MODH                      _T2MOD.Overlap_STR.T2MODHSTR.Byte
    

    /*** T2MODL - TIM2 Counter Modulo Register; 0x0000002F ***/
    union {
      byte Byte;
    } T2MODLSTR;
    #define T2MODL                      _T2MOD.Overlap_STR.T2MODLSTR.Byte
    
  } Overlap_STR;

} T2MODSTR;
extern volatile T2MODSTR _T2MOD;
#define T2MOD                           _T2MOD.Word


/*** T2SC0 - TIM2 Channel Status and Control Register; 0x00000030 ***/
typedef union {
  byte Byte;
  struct {
    byte CH0MAX      :1;                                       /* Channel 0 Maximum Duty Cycle Bit */
    byte TOV0        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS0A       :1;                                       /* Edge/Level Select Bit */
    byte ELS0B       :1;                                       /* Edge/Level Select Bit */
    byte MS0A        :1;                                       /* Mode Select Bit A */
    byte MS0B        :1;                                       /* Mode Select Bit B */
    byte CH0IE       :1;                                       /* Channel 0 Interrupt Enable Bit */
    byte CH0F        :1;                                       /* Channel 0 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV  :1;
    byte grpELS0x :2;
    byte grpMS0x :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} T2SC0STR;
extern volatile T2SC0STR _T2SC0;
#define T2SC0                           _T2SC0.Byte
#define T2SC0_CH0MAX                    _T2SC0.Bits.CH0MAX
#define T2SC0_TOV0                      _T2SC0.Bits.TOV0
#define T2SC0_ELS0A                     _T2SC0.Bits.ELS0A
#define T2SC0_ELS0B                     _T2SC0.Bits.ELS0B
#define T2SC0_MS0A                      _T2SC0.Bits.MS0A
#define T2SC0_MS0B                      _T2SC0.Bits.MS0B
#define T2SC0_CH0IE                     _T2SC0.Bits.CH0IE
#define T2SC0_CH0F                      _T2SC0.Bits.CH0F
#define T2SC0_ELS0x                     _T2SC0.MergedBits.grpELS0x
#define T2SC0_MS0x                      _T2SC0.MergedBits.grpMS0x

#define T2SC0_CH0MAX_MASK               1
#define T2SC0_TOV0_MASK                 2
#define T2SC0_ELS0A_MASK                4
#define T2SC0_ELS0B_MASK                8
#define T2SC0_MS0A_MASK                 16
#define T2SC0_MS0B_MASK                 32
#define T2SC0_CH0IE_MASK                64
#define T2SC0_CH0F_MASK                 128
#define T2SC0_ELS0x_MASK                12
#define T2SC0_ELS0x_BITNUM              2
#define T2SC0_MS0x_MASK                 48
#define T2SC0_MS0x_BITNUM               4


/*** T2CH0 - TIM2 Channel Register; 0x00000031 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T2CH0H - TIM2 Channel Register; 0x00000031 ***/
    union {
      byte Byte;
    } T2CH0HSTR;
    #define T2CH0H                      _T2CH0.Overlap_STR.T2CH0HSTR.Byte
    

    /*** T2CH0L - TIM2 Channel Register; 0x00000032 ***/
    union {
      byte Byte;
    } T2CH0LSTR;
    #define T2CH0L                      _T2CH0.Overlap_STR.T2CH0LSTR.Byte
    
  } Overlap_STR;

} T2CH0STR;
extern volatile T2CH0STR _T2CH0;
#define T2CH0                           _T2CH0.Word


/*** T2SC1 - TIM2 Channel Status and Control Register; 0x00000033 ***/
typedef union {
  byte Byte;
  struct {
    byte CH1MAX      :1;                                       /* Channel 1 Maximum Duty Cycle Bit */
    byte TOV1        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS1A       :1;                                       /* Edge/Level Select Bit */
    byte ELS1B       :1;                                       /* Edge/Level Select Bit */
    byte MS1A        :1;                                       /* Mode Select Bit A */
    byte             :1; 
    byte CH1IE       :1;                                       /* Channel 1 Interrupt Enable Bit */
    byte CH1F        :1;                                       /* Channel 1 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_1 :1;
    byte grpELS1x :2;
    byte grpMS1x :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} T2SC1STR;
extern volatile T2SC1STR _T2SC1;
#define T2SC1                           _T2SC1.Byte
#define T2SC1_CH1MAX                    _T2SC1.Bits.CH1MAX
#define T2SC1_TOV1                      _T2SC1.Bits.TOV1
#define T2SC1_ELS1A                     _T2SC1.Bits.ELS1A
#define T2SC1_ELS1B                     _T2SC1.Bits.ELS1B
#define T2SC1_MS1A                      _T2SC1.Bits.MS1A
#define T2SC1_CH1IE                     _T2SC1.Bits.CH1IE
#define T2SC1_CH1F                      _T2SC1.Bits.CH1F
#define T2SC1_ELS1x                     _T2SC1.MergedBits.grpELS1x

#define T2SC1_CH1MAX_MASK               1
#define T2SC1_TOV1_MASK                 2
#define T2SC1_ELS1A_MASK                4
#define T2SC1_ELS1B_MASK                8
#define T2SC1_MS1A_MASK                 16
#define T2SC1_CH1IE_MASK                64
#define T2SC1_CH1F_MASK                 128
#define T2SC1_ELS1x_MASK                12
#define T2SC1_ELS1x_BITNUM              2


/*** T2CH1 - TIM2 Channel Register; 0x00000034 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** T2CH1H - TIM2 Channel Register; 0x00000034 ***/
    union {
      byte Byte;
    } T2CH1HSTR;
    #define T2CH1H                      _T2CH1.Overlap_STR.T2CH1HSTR.Byte
    

    /*** T2CH1L - TIM2 Channel Register; 0x00000035 ***/
    union {
      byte Byte;
    } T2CH1LSTR;
    #define T2CH1L                      _T2CH1.Overlap_STR.T2CH1LSTR.Byte
    
  } Overlap_STR;

} T2CH1STR;
extern volatile T2CH1STR _T2CH1;
#define T2CH1                           _T2CH1.Word


/*** PCTL - PLL Bandwidth Control Register; 0x00000036 ***/
typedef union {
  byte Byte;
  struct {
    byte VPR0        :1;                                       /* VCO Power-of-Two Range Select Bits */
    byte VPR1        :1;                                       /* VCO Power-of-Two Range Select Bits */
    byte PRE0        :1;                                       /* Prescaler Program Bits */
    byte PRE1        :1;                                       /* Prescaler Program Bits */
    byte BCS         :1;                                       /* Base Clock Select Bit */
    byte PLLON       :1;                                       /* PLL On Bit */
    byte PLLF        :1;                                       /* PLL Flag Bit */
    byte PLLIE       :1;                                       /* PLL Interrupt Enable Bit */
  } Bits;
  struct {
    byte grpVPR  :2;
    byte grpPRE  :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} PCTLSTR;
extern volatile PCTLSTR _PCTL;
#define PCTL                            _PCTL.Byte
#define PCTL_VPR0                       _PCTL.Bits.VPR0
#define PCTL_VPR1                       _PCTL.Bits.VPR1
#define PCTL_PRE0                       _PCTL.Bits.PRE0
#define PCTL_PRE1                       _PCTL.Bits.PRE1
#define PCTL_BCS                        _PCTL.Bits.BCS
#define PCTL_PLLON                      _PCTL.Bits.PLLON
#define PCTL_PLLF                       _PCTL.Bits.PLLF
#define PCTL_PLLIE                      _PCTL.Bits.PLLIE
#define PCTL_VPR                        _PCTL.MergedBits.grpVPR
#define PCTL_PRE                        _PCTL.MergedBits.grpPRE

#define PCTL_VPR0_MASK                  1
#define PCTL_VPR1_MASK                  2
#define PCTL_PRE0_MASK                  4
#define PCTL_PRE1_MASK                  8
#define PCTL_BCS_MASK                   16
#define PCTL_PLLON_MASK                 32
#define PCTL_PLLF_MASK                  64
#define PCTL_PLLIE_MASK                 128
#define PCTL_VPR_MASK                   3
#define PCTL_VPR_BITNUM                 0
#define PCTL_PRE_MASK                   12
#define PCTL_PRE_BITNUM                 2


/*** PBWC - PLL Bandwidth Control Register; 0x00000037 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte ACQ         :1;                                       /* Automatic Bandwidth Control Bit */
    byte LOCK        :1;                                       /* Lock Indicator Bit */
    byte AUTO        :1;                                       /* Acquisiton Mode Bit */
  } Bits;
} PBWCSTR;
extern volatile PBWCSTR _PBWC;
#define PBWC                            _PBWC.Byte
#define PBWC_ACQ                        _PBWC.Bits.ACQ
#define PBWC_LOCK                       _PBWC.Bits.LOCK
#define PBWC_AUTO                       _PBWC.Bits.AUTO

#define PBWC_ACQ_MASK                   32
#define PBWC_LOCK_MASK                  64
#define PBWC_AUTO_MASK                  128


/*** PMS - PLL Multiplier Select Register; 0x00000038 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PMSH - PLL Multiplier Select Register High; 0x00000038 ***/
    union {
      byte Byte;
      struct {
        byte MUL8        :1;                                       /* PLL Multiplier Select Bit */
        byte MUL9        :1;                                       /* PLL Multiplier Select Bit */
        byte MUL10       :1;                                       /* PLL Multiplier Select Bit */
        byte MUL11       :1;                                       /* PLL Multiplier Select Bit */
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
      } Bits;
      struct {
        byte grpMUL_8 :4;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
      } MergedBits;
    } PMSHSTR;
    #define PMSH                        _PMS.Overlap_STR.PMSHSTR.Byte
    #define PMSH_MUL8                   _PMS.Overlap_STR.PMSHSTR.Bits.MUL8
    #define PMSH_MUL9                   _PMS.Overlap_STR.PMSHSTR.Bits.MUL9
    #define PMSH_MUL10                  _PMS.Overlap_STR.PMSHSTR.Bits.MUL10
    #define PMSH_MUL11                  _PMS.Overlap_STR.PMSHSTR.Bits.MUL11
    #define PMSH_MUL_8                  _PMS.Overlap_STR.PMSHSTR.MergedBits.grpMUL_8
    #define PMSH_MUL                    PMSH_MUL_8
    
    #define PMSH_MUL8_MASK              1
    #define PMSH_MUL9_MASK              2
    #define PMSH_MUL10_MASK             4
    #define PMSH_MUL11_MASK             8
    #define PMSH_MUL_8_MASK             15
    #define PMSH_MUL_8_BITNUM           0
    

    /*** PMSL - PLL Multiplier Select Register Low; 0x00000039 ***/
    union {
      byte Byte;
      struct {
        byte MUL0        :1;                                       /* PLL Multiplier Select Bit */
        byte MUL1        :1;                                       /* PLL Multiplier Select Bit */
        byte MUL2        :1;                                       /* PLL Multiplier Select Bit */
        byte MUL3        :1;                                       /* PLL Multiplier Select Bit */
        byte MUL4        :1;                                       /* PLL Multiplier Select Bit */
        byte MUL5        :1;                                       /* PLL Multiplier Select Bit */
        byte MUL6        :1;                                       /* PLL Multiplier Select Bit */
        byte MUL7        :1;                                       /* PLL Multiplier Select Bit */
      } Bits;
    } PMSLSTR;
    #define PMSL                        _PMS.Overlap_STR.PMSLSTR.Byte
    #define PMSL_MUL0                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL0
    #define PMSL_MUL1                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL1
    #define PMSL_MUL2                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL2
    #define PMSL_MUL3                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL3
    #define PMSL_MUL4                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL4
    #define PMSL_MUL5                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL5
    #define PMSL_MUL6                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL6
    #define PMSL_MUL7                   _PMS.Overlap_STR.PMSLSTR.Bits.MUL7
    
    #define PMSL_MUL0_MASK              1
    #define PMSL_MUL1_MASK              2
    #define PMSL_MUL2_MASK              4
    #define PMSL_MUL3_MASK              8
    #define PMSL_MUL4_MASK              16
    #define PMSL_MUL5_MASK              32
    #define PMSL_MUL6_MASK              64
    #define PMSL_MUL7_MASK              128
    
  } Overlap_STR;

} PMSSTR;
extern volatile PMSSTR _PMS;
#define PMS                             _PMS.Word


/*** PMRS - PLL VCO Range Select; 0x0000003A ***/
typedef union {
  byte Byte;
  struct {
    byte VRS0        :1;                                       /* VCO Range Select Bit */
    byte VRS1        :1;                                       /* VCO Range Select Bit */
    byte VRS2        :1;                                       /* VCO Range Select Bit */
    byte VRS3        :1;                                       /* VCO Range Select Bit */
    byte VRS4        :1;                                       /* VCO Range Select Bit */
    byte VRS5        :1;                                       /* VCO Range Select Bit */
    byte VRS6        :1;                                       /* VCO Range Select Bit */
    byte VRS7        :1;                                       /* VCO Range Select Bit */
  } Bits;
} PMRSSTR;
extern volatile PMRSSTR _PMRS;
#define PMRS                            _PMRS.Byte
#define PMRS_VRS0                       _PMRS.Bits.VRS0
#define PMRS_VRS1                       _PMRS.Bits.VRS1
#define PMRS_VRS2                       _PMRS.Bits.VRS2
#define PMRS_VRS3                       _PMRS.Bits.VRS3
#define PMRS_VRS4                       _PMRS.Bits.VRS4
#define PMRS_VRS5                       _PMRS.Bits.VRS5
#define PMRS_VRS6                       _PMRS.Bits.VRS6
#define PMRS_VRS7                       _PMRS.Bits.VRS7

#define PMRS_VRS0_MASK                  1
#define PMRS_VRS1_MASK                  2
#define PMRS_VRS2_MASK                  4
#define PMRS_VRS3_MASK                  8
#define PMRS_VRS4_MASK                  16
#define PMRS_VRS5_MASK                  32
#define PMRS_VRS6_MASK                  64
#define PMRS_VRS7_MASK                  128


/*** PMDS - PLL Reference Divider Select Register; 0x0000003B ***/
typedef union {
  byte Byte;
  struct {
    byte RDS0        :1;                                       /* Reference Divider Select Bit */
    byte RDS1        :1;                                       /* Reference Divider Select Bit */
    byte RDS2        :1;                                       /* Reference Divider Select Bit */
    byte RDS3        :1;                                       /* Reference Divider Select Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpRDS  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} PMDSSTR;
extern volatile PMDSSTR _PMDS;
#define PMDS                            _PMDS.Byte
#define PMDS_RDS0                       _PMDS.Bits.RDS0
#define PMDS_RDS1                       _PMDS.Bits.RDS1
#define PMDS_RDS2                       _PMDS.Bits.RDS2
#define PMDS_RDS3                       _PMDS.Bits.RDS3
#define PMDS_RDS                        _PMDS.MergedBits.grpRDS

#define PMDS_RDS0_MASK                  1
#define PMDS_RDS1_MASK                  2
#define PMDS_RDS2_MASK                  4
#define PMDS_RDS3_MASK                  8
#define PMDS_RDS_MASK                   15
#define PMDS_RDS_BITNUM                 0


/*** TBCR - Timebase Control Register; 0x00000046 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte TBON        :1;                                       /* Timebase Enabled */
    byte TBIE        :1;                                       /* Timebase Interrupt Enable */
    byte TACK        :1;                                       /* Timebase ACKnowledge */
    byte TBR0        :1;                                       /* Timebase Rate Selection */
    byte TBR1        :1;                                       /* Timebase Rate Selection */
    byte TBR2        :1;                                       /* Timebase Rate Selection */
    byte TBIF        :1;                                       /* Timebase Interrupt Flag */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpTBR  :3;
    byte         :1;
  } MergedBits;
} TBCRSTR;
extern volatile TBCRSTR _TBCR;
#define TBCR                            _TBCR.Byte
#define TBCR_TBON                       _TBCR.Bits.TBON
#define TBCR_TBIE                       _TBCR.Bits.TBIE
#define TBCR_TACK                       _TBCR.Bits.TACK
#define TBCR_TBR0                       _TBCR.Bits.TBR0
#define TBCR_TBR1                       _TBCR.Bits.TBR1
#define TBCR_TBR2                       _TBCR.Bits.TBR2
#define TBCR_TBIF                       _TBCR.Bits.TBIF
#define TBCR_TBR                        _TBCR.MergedBits.grpTBR

#define TBCR_TBON_MASK                  2
#define TBCR_TBIE_MASK                  4
#define TBCR_TACK_MASK                  8
#define TBCR_TBR0_MASK                  16
#define TBCR_TBR1_MASK                  32
#define TBCR_TBR2_MASK                  64
#define TBCR_TBIF_MASK                  128
#define TBCR_TBR_MASK                   112
#define TBCR_TBR_BITNUM                 4


/*** MMADR - Multi-Master IIC Address Register; 0x00000048 ***/
typedef union {
  byte Byte;
  struct {
    byte MMEXTAD     :1;                                       /* Multi-Master Expanded Address */
    byte MMAD1       :1;                                       /* Multi-Master Address Bit 1 */
    byte MMAD2       :1;                                       /* Multi-Master Address Bit 2 */
    byte MMAD3       :1;                                       /* Multi-Master Address Bit 3 */
    byte MMAD4       :1;                                       /* Multi-Master Address Bit 4 */
    byte MMAD5       :1;                                       /* Multi-Master Address Bit 5 */
    byte MMAD6       :1;                                       /* Multi-Master Address Bit 6 */
    byte MMAD7       :1;                                       /* Multi-Master Address Bit 7 */
  } Bits;
  struct {
    byte         :1;
    byte grpMMAD_1 :7;
  } MergedBits;
} MMADRSTR;
extern volatile MMADRSTR _MMADR;
#define MMADR                           _MMADR.Byte
#define MMADR_MMEXTAD                   _MMADR.Bits.MMEXTAD
#define MMADR_MMAD1                     _MMADR.Bits.MMAD1
#define MMADR_MMAD2                     _MMADR.Bits.MMAD2
#define MMADR_MMAD3                     _MMADR.Bits.MMAD3
#define MMADR_MMAD4                     _MMADR.Bits.MMAD4
#define MMADR_MMAD5                     _MMADR.Bits.MMAD5
#define MMADR_MMAD6                     _MMADR.Bits.MMAD6
#define MMADR_MMAD7                     _MMADR.Bits.MMAD7
#define MMADR_MMAD_1                    _MMADR.MergedBits.grpMMAD_1
#define MMADR_MMAD                      MMADR_MMAD_1

#define MMADR_MMEXTAD_MASK              1
#define MMADR_MMAD1_MASK                2
#define MMADR_MMAD2_MASK                4
#define MMADR_MMAD3_MASK                8
#define MMADR_MMAD4_MASK                16
#define MMADR_MMAD5_MASK                32
#define MMADR_MMAD6_MASK                64
#define MMADR_MMAD7_MASK                128
#define MMADR_MMAD_1_MASK               254
#define MMADR_MMAD_1_BITNUM             1


/*** MMCR1 - Multi-Master IIC Control Register 1; 0x00000049 ***/
typedef union {
  byte Byte;
  struct {
    byte SDASCL1     :1;                                       /* SDA and SCL I/O Pin Select */
    byte MMCRCBYTE   :1;                                       /* Multi-Master IIC CRC Byte */
    byte REPSEN      :1;                                       /* Repeated Start Enable */
    byte MMTXAK      :1;                                       /* Transmit Acknowledge Enable */
    byte             :1; 
    byte MMCLRBB     :1;                                       /* Multi-Master IIC Clear Busy Bit */
    byte MMIEN       :1;                                       /* Multi-Master IIC Interrupt Enable */
    byte MMEN        :1;                                       /* Multi-Master IIC Enable */
  } Bits;
} MMCR1STR;
extern volatile MMCR1STR _MMCR1;
#define MMCR1                           _MMCR1.Byte
#define MMCR1_SDASCL1                   _MMCR1.Bits.SDASCL1
#define MMCR1_MMCRCBYTE                 _MMCR1.Bits.MMCRCBYTE
#define MMCR1_REPSEN                    _MMCR1.Bits.REPSEN
#define MMCR1_MMTXAK                    _MMCR1.Bits.MMTXAK
#define MMCR1_MMCLRBB                   _MMCR1.Bits.MMCLRBB
#define MMCR1_MMIEN                     _MMCR1.Bits.MMIEN
#define MMCR1_MMEN                      _MMCR1.Bits.MMEN

#define MMCR1_SDASCL1_MASK              1
#define MMCR1_MMCRCBYTE_MASK            2
#define MMCR1_REPSEN_MASK               4
#define MMCR1_MMTXAK_MASK               8
#define MMCR1_MMCLRBB_MASK              32
#define MMCR1_MMIEN_MASK                64
#define MMCR1_MMEN_MASK                 128


/*** MMCR2 - Multi-Master IIC Control Register 2; 0x0000004A ***/
typedef union {
  byte Byte;
  struct {
    byte MMCRCEF     :1;                                       /* Multi-Master IIC CRC Error Flag */
    byte             :1; 
    byte             :1; 
    byte MMRW        :1;                                       /* Multi-Master IIC Master Read/Write */
    byte MMAST       :1;                                       /* Multi-Master IIC Master Control */
    byte MMBB        :1;                                       /* Multi-Master IIC Bus Busy Flag */
    byte MMNAKIF     :1;                                       /* No Acnknowledge Interrupt Flag */
    byte MMALIF      :1;                                       /* Arbitration Loss Interrupt Flag */
  } Bits;
} MMCR2STR;
extern volatile MMCR2STR _MMCR2;
#define MMCR2                           _MMCR2.Byte
#define MMCR2_MMCRCEF                   _MMCR2.Bits.MMCRCEF
#define MMCR2_MMRW                      _MMCR2.Bits.MMRW
#define MMCR2_MMAST                     _MMCR2.Bits.MMAST
#define MMCR2_MMBB                      _MMCR2.Bits.MMBB
#define MMCR2_MMNAKIF                   _MMCR2.Bits.MMNAKIF
#define MMCR2_MMALIF                    _MMCR2.Bits.MMALIF

#define MMCR2_MMCRCEF_MASK              1
#define MMCR2_MMRW_MASK                 8
#define MMCR2_MMAST_MASK                16
#define MMCR2_MMBB_MASK                 32
#define MMCR2_MMNAKIF_MASK              64
#define MMCR2_MMALIF_MASK               128


/*** MMSR - Multi-Master IIC Status Register; 0x0000004B ***/
typedef union {
  byte Byte;
  struct {
    byte MMRXBF      :1;                                       /* Multi-Master Receive Buffer Full */
    byte MMTXBE      :1;                                       /* Multi-Master Transmit Buffer Empty */
    byte MMCRCBF     :1;                                       /* CRC Data Buffer Full Flag */
    byte MMRXAK      :1;                                       /* Multi-Master Receive Acknowledge */
    byte MMSRW       :1;                                       /* Multi-Master Slave Read/Write */
    byte MMATCH      :1;                                       /* Multi-Master Address Match */
    byte MMTXIF      :1;                                       /* Multi-Master Transmit Interrupt Flag */
    byte MMRXIF      :1;                                       /* Multi-Master IIC Receive Interrupt Flag */
  } Bits;
} MMSRSTR;
extern volatile MMSRSTR _MMSR;
#define MMSR                            _MMSR.Byte
#define MMSR_MMRXBF                     _MMSR.Bits.MMRXBF
#define MMSR_MMTXBE                     _MMSR.Bits.MMTXBE
#define MMSR_MMCRCBF                    _MMSR.Bits.MMCRCBF
#define MMSR_MMRXAK                     _MMSR.Bits.MMRXAK
#define MMSR_MMSRW                      _MMSR.Bits.MMSRW
#define MMSR_MMATCH                     _MMSR.Bits.MMATCH
#define MMSR_MMTXIF                     _MMSR.Bits.MMTXIF
#define MMSR_MMRXIF                     _MMSR.Bits.MMRXIF

#define MMSR_MMRXBF_MASK                1
#define MMSR_MMTXBE_MASK                2
#define MMSR_MMCRCBF_MASK               4
#define MMSR_MMRXAK_MASK                8
#define MMSR_MMSRW_MASK                 16
#define MMSR_MMATCH_MASK                32
#define MMSR_MMTXIF_MASK                64
#define MMSR_MMRXIF_MASK                128


/*** MMDTR - Multi-Master IIC Data Transmit Register; 0x0000004C ***/
typedef union {
  byte Byte;
  struct {
    byte MMTD0       :1;                                       /* Multi-Master IIC Transmit Data Bit 0 */
    byte MMTD1       :1;                                       /* Multi-Master IIC Transmit Data Bit 1 */
    byte MMTD2       :1;                                       /* Multi-Master IIC Transmit Data Bit 2 */
    byte MMTD3       :1;                                       /* Multi-Master IIC Transmit Data Bit 3 */
    byte MMTD4       :1;                                       /* Multi-Master IIC Transmit Data Bit 4 */
    byte MMTD5       :1;                                       /* Multi-Master IIC Transmit Data Bit 5 */
    byte MMTD6       :1;                                       /* Multi-Master IIC Transmit Data Bit 6 */
    byte MMTD7       :1;                                       /* Multi-Master IIC Transmit Data Bit 7 */
  } Bits;
} MMDTRSTR;
extern volatile MMDTRSTR _MMDTR;
#define MMDTR                           _MMDTR.Byte
#define MMDTR_MMTD0                     _MMDTR.Bits.MMTD0
#define MMDTR_MMTD1                     _MMDTR.Bits.MMTD1
#define MMDTR_MMTD2                     _MMDTR.Bits.MMTD2
#define MMDTR_MMTD3                     _MMDTR.Bits.MMTD3
#define MMDTR_MMTD4                     _MMDTR.Bits.MMTD4
#define MMDTR_MMTD5                     _MMDTR.Bits.MMTD5
#define MMDTR_MMTD6                     _MMDTR.Bits.MMTD6
#define MMDTR_MMTD7                     _MMDTR.Bits.MMTD7

#define MMDTR_MMTD0_MASK                1
#define MMDTR_MMTD1_MASK                2
#define MMDTR_MMTD2_MASK                4
#define MMDTR_MMTD3_MASK                8
#define MMDTR_MMTD4_MASK                16
#define MMDTR_MMTD5_MASK                32
#define MMDTR_MMTD6_MASK                64
#define MMDTR_MMTD7_MASK                128


/*** MMDRR - Multi-Master IIC Data Receive Register; 0x0000004D ***/
typedef union {
  byte Byte;
  struct {
    byte MMRD0       :1;                                       /* Multi-Master IIC Receive Data Bit 0 */
    byte MMRD1       :1;                                       /* Multi-Master IIC Receive Data Bit 1 */
    byte MMRD2       :1;                                       /* Multi-Master IIC Receive Data Bit 2 */
    byte MMRD3       :1;                                       /* Multi-Master IIC Receive Data Bit 3 */
    byte MMRD4       :1;                                       /* Multi-Master IIC Receive Data Bit 4 */
    byte MMRD5       :1;                                       /* Multi-Master IIC Receive Data Bit 5 */
    byte MMRD6       :1;                                       /* Multi-Master IIC Receive Data Bit 6 */
    byte MMRD7       :1;                                       /* Multi-Master IIC Receive Data Bit 7 */
  } Bits;
} MMDRRSTR;
extern volatile MMDRRSTR _MMDRR;
#define MMDRR                           _MMDRR.Byte
#define MMDRR_MMRD0                     _MMDRR.Bits.MMRD0
#define MMDRR_MMRD1                     _MMDRR.Bits.MMRD1
#define MMDRR_MMRD2                     _MMDRR.Bits.MMRD2
#define MMDRR_MMRD3                     _MMDRR.Bits.MMRD3
#define MMDRR_MMRD4                     _MMDRR.Bits.MMRD4
#define MMDRR_MMRD5                     _MMDRR.Bits.MMRD5
#define MMDRR_MMRD6                     _MMDRR.Bits.MMRD6
#define MMDRR_MMRD7                     _MMDRR.Bits.MMRD7

#define MMDRR_MMRD0_MASK                1
#define MMDRR_MMRD1_MASK                2
#define MMDRR_MMRD2_MASK                4
#define MMDRR_MMRD3_MASK                8
#define MMDRR_MMRD4_MASK                16
#define MMDRR_MMRD5_MASK                32
#define MMDRR_MMRD6_MASK                64
#define MMDRR_MMRD7_MASK                128


/*** MMCRDR - Multi-Master IIC CRC Data Register; 0x0000004E ***/
typedef union {
  byte Byte;
  struct {
    byte MMCRCD0     :1;                                       /* Multi-Master IIC CRC Data Bit 0 */
    byte MMCRCD1     :1;                                       /* Multi-Master IIC CRC Data Bit 1 */
    byte MMCRCD2     :1;                                       /* Multi-Master IIC CRC Data Bit 2 */
    byte MMCRCD3     :1;                                       /* Multi-Master IIC CRC Data Bit 3 */
    byte MMCRCD4     :1;                                       /* Multi-Master IIC CRC Data Bit 4 */
    byte MMCRCD5     :1;                                       /* Multi-Master IIC CRC Data Bit 5 */
    byte MMCRCD6     :1;                                       /* Multi-Master IIC CRC Data Bit 6 */
    byte MMCRCD7     :1;                                       /* Multi-Master IIC CRC Data Bit 7 */
  } Bits;
} MMCRDRSTR;
extern volatile MMCRDRSTR _MMCRDR;
#define MMCRDR                          _MMCRDR.Byte
#define MMCRDR_MMCRCD0                  _MMCRDR.Bits.MMCRCD0
#define MMCRDR_MMCRCD1                  _MMCRDR.Bits.MMCRCD1
#define MMCRDR_MMCRCD2                  _MMCRDR.Bits.MMCRCD2
#define MMCRDR_MMCRCD3                  _MMCRDR.Bits.MMCRCD3
#define MMCRDR_MMCRCD4                  _MMCRDR.Bits.MMCRCD4
#define MMCRDR_MMCRCD5                  _MMCRDR.Bits.MMCRCD5
#define MMCRDR_MMCRCD6                  _MMCRDR.Bits.MMCRCD6
#define MMCRDR_MMCRCD7                  _MMCRDR.Bits.MMCRCD7

#define MMCRDR_MMCRCD0_MASK             1
#define MMCRDR_MMCRCD1_MASK             2
#define MMCRDR_MMCRCD2_MASK             4
#define MMCRDR_MMCRCD3_MASK             8
#define MMCRDR_MMCRCD4_MASK             16
#define MMCRDR_MMCRCD5_MASK             32
#define MMCRDR_MMCRCD6_MASK             64
#define MMCRDR_MMCRCD7_MASK             128


/*** MMFDR - Multi-Master IIC Frequency Divider Register; 0x0000004F ***/
typedef union {
  byte Byte;
  struct {
    byte MMBR0       :1;                                       /* Frequency Divider Bit 0 */
    byte MMBR1       :1;                                       /* Frequency Divider Bit 1 */
    byte MMBR2       :1;                                       /* Frequency Divider Bit 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpMMBR :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} MMFDRSTR;
extern volatile MMFDRSTR _MMFDR;
#define MMFDR                           _MMFDR.Byte
#define MMFDR_MMBR0                     _MMFDR.Bits.MMBR0
#define MMFDR_MMBR1                     _MMFDR.Bits.MMBR1
#define MMFDR_MMBR2                     _MMFDR.Bits.MMBR2
#define MMFDR_MMBR                      _MMFDR.MergedBits.grpMMBR

#define MMFDR_MMBR0_MASK                1
#define MMFDR_MMBR1_MASK                2
#define MMFDR_MMBR2_MASK                4
#define MMFDR_MMBR_MASK                 7
#define MMFDR_MMBR_BITNUM               0


/*** PWMCR - PWM Control Register; 0x00000051 ***/
typedef union {
  byte Byte;
  struct {
    byte PCH0        :1;                                       /* PWM Channel Enable Bit 0 */
    byte PCH1        :1;                                       /* PWM Channel Enable Bit 1 */
    byte PCH2        :1;                                       /* PWM Channel Enable Bit 2 */
    byte             :1; 
    byte             :1; 
    byte PWMEN0      :1;                                       /* PWM Enable Bit 0 */
    byte PWMEN1      :1;                                       /* PWM Enable Bit 1 */
    byte PWMEN2      :1;                                       /* PWM Enable Bit 2 */
  } Bits;
  struct {
    byte grpPCH  :3;
    byte         :1;
    byte         :1;
    byte grpPWMEN :3;
  } MergedBits;
} PWMCRSTR;
extern volatile PWMCRSTR _PWMCR;
#define PWMCR                           _PWMCR.Byte
#define PWMCR_PCH0                      _PWMCR.Bits.PCH0
#define PWMCR_PCH1                      _PWMCR.Bits.PCH1
#define PWMCR_PCH2                      _PWMCR.Bits.PCH2
#define PWMCR_PWMEN0                    _PWMCR.Bits.PWMEN0
#define PWMCR_PWMEN1                    _PWMCR.Bits.PWMEN1
#define PWMCR_PWMEN2                    _PWMCR.Bits.PWMEN2
#define PWMCR_PCH                       _PWMCR.MergedBits.grpPCH
#define PWMCR_PWMEN                     _PWMCR.MergedBits.grpPWMEN

#define PWMCR_PCH0_MASK                 1
#define PWMCR_PCH1_MASK                 2
#define PWMCR_PCH2_MASK                 4
#define PWMCR_PWMEN0_MASK               32
#define PWMCR_PWMEN1_MASK               64
#define PWMCR_PWMEN2_MASK               128
#define PWMCR_PCH_MASK                  7
#define PWMCR_PCH_BITNUM                0
#define PWMCR_PWMEN_MASK                224
#define PWMCR_PWMEN_BITNUM              5


/*** PWMCCR - PWM Clock Control Register; 0x00000052 ***/
typedef union {
  byte Byte;
  struct {
    byte PCLK0       :1;                                       /* PWM Clock Prescaler Bit 0 */
    byte PCLK1       :1;                                       /* PWM Clock Prescaler Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte PCLKSEL     :1;                                       /* PWM Input Clock Select Bit */
  } Bits;
  struct {
    byte grpPCLK :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} PWMCCRSTR;
extern volatile PWMCCRSTR _PWMCCR;
#define PWMCCR                          _PWMCCR.Byte
#define PWMCCR_PCLK0                    _PWMCCR.Bits.PCLK0
#define PWMCCR_PCLK1                    _PWMCCR.Bits.PCLK1
#define PWMCCR_PCLKSEL                  _PWMCCR.Bits.PCLKSEL
#define PWMCCR_PCLK                     _PWMCCR.MergedBits.grpPCLK

#define PWMCCR_PCLK0_MASK               1
#define PWMCCR_PCLK1_MASK               2
#define PWMCCR_PCLKSEL_MASK             128
#define PWMCCR_PCLK_MASK                3
#define PWMCCR_PCLK_BITNUM              0


/*** PWMDR0 - PWM Data Register 0; 0x00000053 ***/
typedef union {
  byte Byte;
} PWMDR0STR;
extern volatile PWMDR0STR _PWMDR0;
#define PWMDR0                          _PWMDR0.Byte
/* PWMDR_ARR: Access 3 PWMDRx registers in an array */
#define PWMDR_ARR                       ((volatile byte * __far) &PWMDR0)


/*** PWMDR1 - PWM Data Register 0; 0x00000054 ***/
typedef union {
  byte Byte;
} PWMDR1STR;
extern volatile PWMDR1STR _PWMDR1;
#define PWMDR1                          _PWMDR1.Byte


/*** PWMDR2 - PWM Data Register 0; 0x00000055 ***/
typedef union {
  byte Byte;
} PWMDR2STR;
extern volatile PWMDR2STR _PWMDR2;
#define PWMDR2                          _PWMDR2.Byte


/*** PWMPCR - PWM Phase Control Register; 0x00000056 ***/
typedef union {
  byte Byte;
  struct {
    byte PHD0        :1;                                       /* PWM Phase Value Bit 0 */
    byte PHD1        :1;                                       /* PWM Phase Value Bit 1 */
    byte PHD2        :1;                                       /* PWM Phase Value Bit 2 */
    byte PHD3        :1;                                       /* PWM Phase Value Bit 3 */
    byte PHD4        :1;                                       /* PWM Phase Value Bit 4 */
    byte PHD5        :1;                                       /* PWM Phase Value Bit 5 */
    byte PHD6        :1;                                       /* PWM Phase Value Bit 6 */
    byte PHEN        :1;                                       /* PWM Automatic Phase Control Enable Bit */
  } Bits;
  struct {
    byte grpPHD  :7;
    byte         :1;
  } MergedBits;
} PWMPCRSTR;
extern volatile PWMPCRSTR _PWMPCR;
#define PWMPCR                          _PWMPCR.Byte
#define PWMPCR_PHD0                     _PWMPCR.Bits.PHD0
#define PWMPCR_PHD1                     _PWMPCR.Bits.PHD1
#define PWMPCR_PHD2                     _PWMPCR.Bits.PHD2
#define PWMPCR_PHD3                     _PWMPCR.Bits.PHD3
#define PWMPCR_PHD4                     _PWMPCR.Bits.PHD4
#define PWMPCR_PHD5                     _PWMPCR.Bits.PHD5
#define PWMPCR_PHD6                     _PWMPCR.Bits.PHD6
#define PWMPCR_PHEN                     _PWMPCR.Bits.PHEN
#define PWMPCR_PHD                      _PWMPCR.MergedBits.grpPHD

#define PWMPCR_PHD0_MASK                1
#define PWMPCR_PHD1_MASK                2
#define PWMPCR_PHD2_MASK                4
#define PWMPCR_PHD3_MASK                8
#define PWMPCR_PHD4_MASK                16
#define PWMPCR_PHD5_MASK                32
#define PWMPCR_PHD6_MASK                64
#define PWMPCR_PHEN_MASK                128
#define PWMPCR_PHD_MASK                 127
#define PWMPCR_PHD_BITNUM               0


/*** ADSCR - ADC Status and Control Register; 0x00000057 ***/
typedef union {
  byte Byte;
  struct {
    byte ADCH0       :1;                                       /* ADC Channel Select Bit 0 */
    byte ADCH1       :1;                                       /* ADC Channel Select Bit 1 */
    byte ADCH2       :1;                                       /* ADC Channel Select Bit 2 */
    byte ADCH3       :1;                                       /* ADC Channel Select Bit 3 */
    byte ADCH4       :1;                                       /* ADC Channel Select Bit 4 */
    byte ADCO        :1;                                       /* ADC Continuous Conversion Bit */
    byte AIEN        :1;                                       /* ADC Interrupt Enable Bit */
    byte COCO        :1;                                       /* Conversions Complete Bit */
  } Bits;
  struct {
    byte grpADCH :5;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} ADSCRSTR;
extern volatile ADSCRSTR _ADSCR;
#define ADSCR                           _ADSCR.Byte
#define ADSCR_ADCH0                     _ADSCR.Bits.ADCH0
#define ADSCR_ADCH1                     _ADSCR.Bits.ADCH1
#define ADSCR_ADCH2                     _ADSCR.Bits.ADCH2
#define ADSCR_ADCH3                     _ADSCR.Bits.ADCH3
#define ADSCR_ADCH4                     _ADSCR.Bits.ADCH4
#define ADSCR_ADCO                      _ADSCR.Bits.ADCO
#define ADSCR_AIEN                      _ADSCR.Bits.AIEN
#define ADSCR_COCO                      _ADSCR.Bits.COCO
#define ADSCR_ADCH                      _ADSCR.MergedBits.grpADCH

#define ADSCR_ADCH0_MASK                1
#define ADSCR_ADCH1_MASK                2
#define ADSCR_ADCH2_MASK                4
#define ADSCR_ADCH3_MASK                8
#define ADSCR_ADCH4_MASK                16
#define ADSCR_ADCO_MASK                 32
#define ADSCR_AIEN_MASK                 64
#define ADSCR_COCO_MASK                 128
#define ADSCR_ADCH_MASK                 31
#define ADSCR_ADCH_BITNUM               0


/*** ADICLK - ADC Input Clock Register; 0x00000058 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte MODE0       :1;                                       /* Mode of Result Justification */
    byte MODE1       :1;                                       /* Mode of Result Justification */
    byte ADICLK_BIT  :1;                                       /* ADC Input Clock Register Bit */
    byte ADIV0       :1;                                       /* ADC Clock Prescaler Bit 0 */
    byte ADIV1       :1;                                       /* ADC Clock Prescaler Bit 1 */
    byte ADIV2       :1;                                       /* ADC Clock Prescaler Bit 2 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpMODE :2;
    byte         :1;
    byte grpADIV :3;
  } MergedBits;
} ADICLKSTR;
extern volatile ADICLKSTR _ADICLK;
#define ADICLK                          _ADICLK.Byte
#define ADICLK_MODE0                    _ADICLK.Bits.MODE0
#define ADICLK_MODE1                    _ADICLK.Bits.MODE1
#define ADICLK_ADICLK_BIT               _ADICLK.Bits.ADICLK_BIT
#define ADICLK_ADIV0                    _ADICLK.Bits.ADIV0
#define ADICLK_ADIV1                    _ADICLK.Bits.ADIV1
#define ADICLK_ADIV2                    _ADICLK.Bits.ADIV2
#define ADICLK_MODE                     _ADICLK.MergedBits.grpMODE
#define ADICLK_ADIV                     _ADICLK.MergedBits.grpADIV

#define ADICLK_MODE0_MASK               4
#define ADICLK_MODE1_MASK               8
#define ADICLK_ADICLK_BIT_MASK          16
#define ADICLK_ADIV0_MASK               32
#define ADICLK_ADIV1_MASK               64
#define ADICLK_ADIV2_MASK               128
#define ADICLK_MODE_MASK                12
#define ADICLK_MODE_BITNUM              2
#define ADICLK_ADIV_MASK                224
#define ADICLK_ADIV_BITNUM              5


/*** ADR0 - ADC Data Register High; 0x00000059 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ADR0H - ADC Data Register High 0; 0x00000059 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* ADC Data Bit 8 */
        byte BIT9        :1;                                       /* ADC Data Bit 9 */
        byte BIT10       :1;                                       /* ADC Data Bit 10 */
        byte BIT11       :1;                                       /* ADC Data Bit 11 */
        byte BIT12       :1;                                       /* ADC Data Bit 12 */
        byte BIT13       :1;                                       /* ADC Data Bit 13 */
        byte BIT14       :1;                                       /* ADC Data Bit 14 */
        byte BIT15       :1;                                       /* ADC Data Bit 15 */
      } Bits;
    } ADR0HSTR;
    #define ADR0H                       _ADR0.Overlap_STR.ADR0HSTR.Byte
    #define ADR0H_BIT8                  _ADR0.Overlap_STR.ADR0HSTR.Bits.BIT8
    #define ADR0H_BIT9                  _ADR0.Overlap_STR.ADR0HSTR.Bits.BIT9
    #define ADR0H_BIT10                 _ADR0.Overlap_STR.ADR0HSTR.Bits.BIT10
    #define ADR0H_BIT11                 _ADR0.Overlap_STR.ADR0HSTR.Bits.BIT11
    #define ADR0H_BIT12                 _ADR0.Overlap_STR.ADR0HSTR.Bits.BIT12
    #define ADR0H_BIT13                 _ADR0.Overlap_STR.ADR0HSTR.Bits.BIT13
    #define ADR0H_BIT14                 _ADR0.Overlap_STR.ADR0HSTR.Bits.BIT14
    #define ADR0H_BIT15                 _ADR0.Overlap_STR.ADR0HSTR.Bits.BIT15
    
    #define ADR0H_BIT8_MASK             1
    #define ADR0H_BIT9_MASK             2
    #define ADR0H_BIT10_MASK            4
    #define ADR0H_BIT11_MASK            8
    #define ADR0H_BIT12_MASK            16
    #define ADR0H_BIT13_MASK            32
    #define ADR0H_BIT14_MASK            64
    #define ADR0H_BIT15_MASK            128
    

    /*** ADR0L - ADC Data Register Low 0; 0x0000005A ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* ADC Data Bit 0 */
        byte BIT1        :1;                                       /* ADC Data Bit 1 */
        byte BIT2        :1;                                       /* ADC Data Bit 2 */
        byte BIT3        :1;                                       /* ADC Data Bit 3 */
        byte BIT4        :1;                                       /* ADC Data Bit 4 */
        byte BIT5        :1;                                       /* ADC Data Bit 5 */
        byte BIT6        :1;                                       /* ADC Data Bit 6 */
        byte BIT7        :1;                                       /* ADC Data Bit 7 */
      } Bits;
    } ADR0LSTR;
    #define ADR0L                       _ADR0.Overlap_STR.ADR0LSTR.Byte
    #define ADR0L_BIT0                  _ADR0.Overlap_STR.ADR0LSTR.Bits.BIT0
    #define ADR0L_BIT1                  _ADR0.Overlap_STR.ADR0LSTR.Bits.BIT1
    #define ADR0L_BIT2                  _ADR0.Overlap_STR.ADR0LSTR.Bits.BIT2
    #define ADR0L_BIT3                  _ADR0.Overlap_STR.ADR0LSTR.Bits.BIT3
    #define ADR0L_BIT4                  _ADR0.Overlap_STR.ADR0LSTR.Bits.BIT4
    #define ADR0L_BIT5                  _ADR0.Overlap_STR.ADR0LSTR.Bits.BIT5
    #define ADR0L_BIT6                  _ADR0.Overlap_STR.ADR0LSTR.Bits.BIT6
    #define ADR0L_BIT7                  _ADR0.Overlap_STR.ADR0LSTR.Bits.BIT7
    
    #define ADR0L_BIT0_MASK             1
    #define ADR0L_BIT1_MASK             2
    #define ADR0L_BIT2_MASK             4
    #define ADR0L_BIT3_MASK             8
    #define ADR0L_BIT4_MASK             16
    #define ADR0L_BIT5_MASK             32
    #define ADR0L_BIT6_MASK             64
    #define ADR0L_BIT7_MASK             128
    
  } Overlap_STR;

} ADR0STR;
extern volatile ADR0STR _ADR0;
#define ADR0                            _ADR0.Word


/*** ADR1L - ADC Data Register Low 1; 0x0000005B ***/
typedef union {
  byte Byte;
  struct {
    byte AD2         :1;                                       /* ADC Data Bit 2 */
    byte AD3         :1;                                       /* ADC Data Bit 3 */
    byte AD4         :1;                                       /* ADC Data Bit 4 */
    byte AD5         :1;                                       /* ADC Data Bit 5 */
    byte AD6         :1;                                       /* ADC Data Bit 6 */
    byte AD7         :1;                                       /* ADC Data Bit 7 */
    byte AD8         :1;                                       /* ADC Data Bit 8 */
    byte AD9         :1;                                       /* ADC Data Bit 9 */
  } Bits;
} ADR1LSTR;
extern volatile ADR1LSTR _ADR1L;
#define ADR1L                           _ADR1L.Byte
#define ADR1L_AD2                       _ADR1L.Bits.AD2
#define ADR1L_AD3                       _ADR1L.Bits.AD3
#define ADR1L_AD4                       _ADR1L.Bits.AD4
#define ADR1L_AD5                       _ADR1L.Bits.AD5
#define ADR1L_AD6                       _ADR1L.Bits.AD6
#define ADR1L_AD7                       _ADR1L.Bits.AD7
#define ADR1L_AD8                       _ADR1L.Bits.AD8
#define ADR1L_AD9                       _ADR1L.Bits.AD9

#define ADR1L_AD2_MASK                  1
#define ADR1L_AD3_MASK                  2
#define ADR1L_AD4_MASK                  4
#define ADR1L_AD5_MASK                  8
#define ADR1L_AD6_MASK                  16
#define ADR1L_AD7_MASK                  32
#define ADR1L_AD8_MASK                  64
#define ADR1L_AD9_MASK                  128


/*** ADR2L - ADC Data Register Low 2; 0x0000005C ***/
typedef union {
  byte Byte;
  struct {
    byte AD2         :1;                                       /* ADC Data Bit 2 */
    byte AD3         :1;                                       /* ADC Data Bit 3 */
    byte AD4         :1;                                       /* ADC Data Bit 4 */
    byte AD5         :1;                                       /* ADC Data Bit 5 */
    byte AD6         :1;                                       /* ADC Data Bit 6 */
    byte AD7         :1;                                       /* ADC Data Bit 7 */
    byte AD8         :1;                                       /* ADC Data Bit 8 */
    byte AD9         :1;                                       /* ADC Data Bit 9 */
  } Bits;
} ADR2LSTR;
extern volatile ADR2LSTR _ADR2L;
#define ADR2L                           _ADR2L.Byte
#define ADR2L_AD2                       _ADR2L.Bits.AD2
#define ADR2L_AD3                       _ADR2L.Bits.AD3
#define ADR2L_AD4                       _ADR2L.Bits.AD4
#define ADR2L_AD5                       _ADR2L.Bits.AD5
#define ADR2L_AD6                       _ADR2L.Bits.AD6
#define ADR2L_AD7                       _ADR2L.Bits.AD7
#define ADR2L_AD8                       _ADR2L.Bits.AD8
#define ADR2L_AD9                       _ADR2L.Bits.AD9

#define ADR2L_AD2_MASK                  1
#define ADR2L_AD3_MASK                  2
#define ADR2L_AD4_MASK                  4
#define ADR2L_AD5_MASK                  8
#define ADR2L_AD6_MASK                  16
#define ADR2L_AD7_MASK                  32
#define ADR2L_AD8_MASK                  64
#define ADR2L_AD9_MASK                  128


/*** ADR3L - ADC Data Register Low 3; 0x0000005D ***/
typedef union {
  byte Byte;
  struct {
    byte AD2         :1;                                       /* ADC Data Bit 2 */
    byte AD3         :1;                                       /* ADC Data Bit 3 */
    byte AD4         :1;                                       /* ADC Data Bit 4 */
    byte AD5         :1;                                       /* ADC Data Bit 5 */
    byte AD6         :1;                                       /* ADC Data Bit 6 */
    byte AD7         :1;                                       /* ADC Data Bit 7 */
    byte AD8         :1;                                       /* ADC Data Bit 8 */
    byte AD9         :1;                                       /* ADC Data Bit 9 */
  } Bits;
} ADR3LSTR;
extern volatile ADR3LSTR _ADR3L;
#define ADR3L                           _ADR3L.Byte
#define ADR3L_AD2                       _ADR3L.Bits.AD2
#define ADR3L_AD3                       _ADR3L.Bits.AD3
#define ADR3L_AD4                       _ADR3L.Bits.AD4
#define ADR3L_AD5                       _ADR3L.Bits.AD5
#define ADR3L_AD6                       _ADR3L.Bits.AD6
#define ADR3L_AD7                       _ADR3L.Bits.AD7
#define ADR3L_AD8                       _ADR3L.Bits.AD8
#define ADR3L_AD9                       _ADR3L.Bits.AD9

#define ADR3L_AD2_MASK                  1
#define ADR3L_AD3_MASK                  2
#define ADR3L_AD4_MASK                  4
#define ADR3L_AD5_MASK                  8
#define ADR3L_AD6_MASK                  16
#define ADR3L_AD7_MASK                  32
#define ADR3L_AD8_MASK                  64
#define ADR3L_AD9_MASK                  128


/*** ADASCR - ADC Auto-Scan Control Register; 0x0000005E ***/
typedef union {
  byte Byte;
  struct {
    byte ASCAN       :1;                                       /* Auto-Scan Mode Enable */
    byte AUTO0       :1;                                       /* Auto-Scan Mode Channerl Select Bit 0 */
    byte AUTO1       :1;                                       /* Auto-Scan Mode Channerl Select Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte         :1;
    byte grpAUTO :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} ADASCRSTR;
extern volatile ADASCRSTR _ADASCR;
#define ADASCR                          _ADASCR.Byte
#define ADASCR_ASCAN                    _ADASCR.Bits.ASCAN
#define ADASCR_AUTO0                    _ADASCR.Bits.AUTO0
#define ADASCR_AUTO1                    _ADASCR.Bits.AUTO1
#define ADASCR_AUTO                     _ADASCR.MergedBits.grpAUTO

#define ADASCR_ASCAN_MASK               1
#define ADASCR_AUTO0_MASK               2
#define ADASCR_AUTO1_MASK               4
#define ADASCR_AUTO_MASK                6
#define ADASCR_AUTO_BITNUM              1


/*** SBSR - SIM Break Status Register; 0x0000FE00 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte SBSW        :1;                                       /* SIM Break Stop/Wait */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SBSRSTR;
extern volatile SBSRSTR _SBSR;
#define SBSR                            _SBSR.Byte
#define SBSR_SBSW                       _SBSR.Bits.SBSW

#define SBSR_SBSW_MASK                  2


/*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte LVI         :1;                                       /* Low-Voltage Inhibit Reset Bit */
    byte MODRST      :1;                                       /* Monitor Mode Entry Module Reset Bit */
    byte ILAD        :1;                                       /* Illegal Address Reset Bit */
    byte ILOP        :1;                                       /* Illegal Opcode Reset Bit */
    byte COP         :1;                                       /* Computer Operating Properly Reset Bit */
    byte PIN         :1;                                       /* External Reset Bit */
    byte POR         :1;                                       /* Power-On Reset Bit */
  } Bits;
} SRSRSTR;
extern volatile SRSRSTR _SRSR;
#define SRSR                            _SRSR.Byte
#define SRSR_LVI                        _SRSR.Bits.LVI
#define SRSR_MODRST                     _SRSR.Bits.MODRST
#define SRSR_ILAD                       _SRSR.Bits.ILAD
#define SRSR_ILOP                       _SRSR.Bits.ILOP
#define SRSR_COP                        _SRSR.Bits.COP
#define SRSR_PIN                        _SRSR.Bits.PIN
#define SRSR_POR                        _SRSR.Bits.POR

#define SRSR_LVI_MASK                   2
#define SRSR_MODRST_MASK                4
#define SRSR_ILAD_MASK                  8
#define SRSR_ILOP_MASK                  16
#define SRSR_COP_MASK                   32
#define SRSR_PIN_MASK                   64
#define SRSR_POR_MASK                   128


/*** SBFCR - SIM Break Flag Control Register; 0x0000FE03 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BCFE        :1;                                       /* Break Clear Flag Enable Bit */
  } Bits;
} SBFCRSTR;
extern volatile SBFCRSTR _SBFCR;
#define SBFCR                           _SBFCR.Byte
#define SBFCR_BCFE                      _SBFCR.Bits.BCFE

#define SBFCR_BCFE_MASK                 128


/*** INT1 - Interrupt Status Register 1; 0x0000FE04 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte IF1         :1;                                       /* Interrupt Flag 1 */
    byte IF2         :1;                                       /* Interrupt Flag 2 */
    byte IF3         :1;                                       /* Interrupt Flag 3 */
    byte IF4         :1;                                       /* Interrupt Flag 4 */
    byte IF5         :1;                                       /* Interrupt Flag 5 */
    byte IF6         :1;                                       /* Interrupt Flag 6 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpIF_1 :6;
  } MergedBits;
} INT1STR;
extern volatile INT1STR _INT1;
#define INT1                            _INT1.Byte
#define INT1_IF1                        _INT1.Bits.IF1
#define INT1_IF2                        _INT1.Bits.IF2
#define INT1_IF3                        _INT1.Bits.IF3
#define INT1_IF4                        _INT1.Bits.IF4
#define INT1_IF5                        _INT1.Bits.IF5
#define INT1_IF6                        _INT1.Bits.IF6
#define INT1_IF_1                       _INT1.MergedBits.grpIF_1
#define INT1_IF                         INT1_IF_1

#define INT1_IF1_MASK                   4
#define INT1_IF2_MASK                   8
#define INT1_IF3_MASK                   16
#define INT1_IF4_MASK                   32
#define INT1_IF5_MASK                   64
#define INT1_IF6_MASK                   128
#define INT1_IF_1_MASK                  252
#define INT1_IF_1_BITNUM                2


/*** INT2 - Interrupt Status Register 2; 0x0000FE05 ***/
typedef union {
  byte Byte;
  struct {
    byte IF7         :1;                                       /* Interrupt Flag 7 */
    byte IF8         :1;                                       /* Interrupt Flag 8 */
    byte IF9         :1;                                       /* Interrupt Flag 9 */
    byte IF10        :1;                                       /* Interrupt Flag 10 */
    byte IF11        :1;                                       /* Interrupt Flag 11 */
    byte IF12        :1;                                       /* Interrupt Flag 12 */
    byte IF13        :1;                                       /* Interrupt Flag 13 */
    byte IF14        :1;                                       /* Interrupt Flag 14 */
  } Bits;
} INT2STR;
extern volatile INT2STR _INT2;
#define INT2                            _INT2.Byte
#define INT2_IF7                        _INT2.Bits.IF7
#define INT2_IF8                        _INT2.Bits.IF8
#define INT2_IF9                        _INT2.Bits.IF9
#define INT2_IF10                       _INT2.Bits.IF10
#define INT2_IF11                       _INT2.Bits.IF11
#define INT2_IF12                       _INT2.Bits.IF12
#define INT2_IF13                       _INT2.Bits.IF13
#define INT2_IF14                       _INT2.Bits.IF14

#define INT2_IF7_MASK                   1
#define INT2_IF8_MASK                   2
#define INT2_IF9_MASK                   4
#define INT2_IF10_MASK                  8
#define INT2_IF11_MASK                  16
#define INT2_IF12_MASK                  32
#define INT2_IF13_MASK                  64
#define INT2_IF14_MASK                  128


/*** INT3 - Interrupt Status Register 3; 0x0000FE06 ***/
typedef union {
  byte Byte;
  struct {
    byte IF15        :1;                                       /* Interrupt Flag 15 */
    byte IF16        :1;                                       /* Interrupt Flag 16 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpIF_15 :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} INT3STR;
extern volatile INT3STR _INT3;
#define INT3                            _INT3.Byte
#define INT3_IF15                       _INT3.Bits.IF15
#define INT3_IF16                       _INT3.Bits.IF16
#define INT3_IF_15                      _INT3.MergedBits.grpIF_15
#define INT3_IF                         INT3_IF_15

#define INT3_IF15_MASK                  1
#define INT3_IF16_MASK                  2
#define INT3_IF_15_MASK                 3
#define INT3_IF_15_BITNUM               0


/*** FLCR - FLASH Control Register; 0x0000FE08 ***/
typedef union {
  byte Byte;
  struct {
    byte PGM         :1;                                       /* Program Control Bit */
    byte ERASE       :1;                                       /* Erase Control Bit */
    byte MASS        :1;                                       /* Mass Erase Control Bit */
    byte HVEN        :1;                                       /* High-Voltage Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} FLCRSTR;
extern volatile FLCRSTR _FLCR;
#define FLCR                            _FLCR.Byte
#define FLCR_PGM                        _FLCR.Bits.PGM
#define FLCR_ERASE                      _FLCR.Bits.ERASE
#define FLCR_MASS                       _FLCR.Bits.MASS
#define FLCR_HVEN                       _FLCR.Bits.HVEN

#define FLCR_PGM_MASK                   1
#define FLCR_ERASE_MASK                 2
#define FLCR_MASS_MASK                  4
#define FLCR_HVEN_MASK                  8


/*** FLBPR - FLASH Block Protect Register; 0x0000FE09 ***/
typedef union {
  byte Byte;
  struct {
    byte BPR0        :1;                                       /* Block Protect Register Bit 0 */
    byte BPR1        :1;                                       /* Block Protect Register Bit 1 */
    byte BPR2        :1;                                       /* Block Protect Register Bit 2 */
    byte BPR3        :1;                                       /* Block Protect Register Bit 3 */
    byte BPR4        :1;                                       /* Block Protect Register Bit 4 */
    byte BPR5        :1;                                       /* Block Protect Register Bit 5 */
    byte BPR6        :1;                                       /* Block Protect Register Bit 6 */
    byte BPR7        :1;                                       /* Block Protect Register Bit 7 */
  } Bits;
} FLBPRSTR;
extern volatile FLBPRSTR _FLBPR;
#define FLBPR                           _FLBPR.Byte
#define FLBPR_BPR0                      _FLBPR.Bits.BPR0
#define FLBPR_BPR1                      _FLBPR.Bits.BPR1
#define FLBPR_BPR2                      _FLBPR.Bits.BPR2
#define FLBPR_BPR3                      _FLBPR.Bits.BPR3
#define FLBPR_BPR4                      _FLBPR.Bits.BPR4
#define FLBPR_BPR5                      _FLBPR.Bits.BPR5
#define FLBPR_BPR6                      _FLBPR.Bits.BPR6
#define FLBPR_BPR7                      _FLBPR.Bits.BPR7

#define FLBPR_BPR0_MASK                 1
#define FLBPR_BPR1_MASK                 2
#define FLBPR_BPR2_MASK                 4
#define FLBPR_BPR3_MASK                 8
#define FLBPR_BPR4_MASK                 16
#define FLBPR_BPR5_MASK                 32
#define FLBPR_BPR6_MASK                 64
#define FLBPR_BPR7_MASK                 128


/*** BRK - Break Address Register; 0x0000FE0C ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** BRKH - Break Address Register; 0x0000FE0C ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Break Address Register Bit */
        byte BIT9        :1;                                       /* Break Address Register Bit */
        byte BIT10       :1;                                       /* Break Address Register Bit */
        byte BIT11       :1;                                       /* Break Address Register Bit */
        byte BIT12       :1;                                       /* Break Address Register Bit */
        byte BIT13       :1;                                       /* Break Address Register Bit */
        byte BIT14       :1;                                       /* Break Address Register Bit */
        byte BIT15       :1;                                       /* Break Address Register Bit */
      } Bits;
    } BRKHSTR;
    #define BRKH                        _BRK.Overlap_STR.BRKHSTR.Byte
    #define BRKH_BIT8                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT8
    #define BRKH_BIT9                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT9
    #define BRKH_BIT10                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT10
    #define BRKH_BIT11                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT11
    #define BRKH_BIT12                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT12
    #define BRKH_BIT13                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT13
    #define BRKH_BIT14                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT14
    #define BRKH_BIT15                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT15
    
    #define BRKH_BIT8_MASK              1
    #define BRKH_BIT9_MASK              2
    #define BRKH_BIT10_MASK             4
    #define BRKH_BIT11_MASK             8
    #define BRKH_BIT12_MASK             16
    #define BRKH_BIT13_MASK             32
    #define BRKH_BIT14_MASK             64
    #define BRKH_BIT15_MASK             128
    

    /*** BRKL - Break Address Register; 0x0000FE0D ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Break Address Register Bit */
        byte BIT1        :1;                                       /* Break Address Register Bit */
        byte BIT2        :1;                                       /* Break Address Register Bit */
        byte BIT3        :1;                                       /* Break Address Register Bit */
        byte BIT4        :1;                                       /* Break Address Register Bit */
        byte BIT5        :1;                                       /* Break Address Register Bit */
        byte BIT6        :1;                                       /* Break Address Register Bit */
        byte BIT7        :1;                                       /* Break Address Register Bit */
      } Bits;
    } BRKLSTR;
    #define BRKL                        _BRK.Overlap_STR.BRKLSTR.Byte
    #define BRKL_BIT0                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT0
    #define BRKL_BIT1                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT1
    #define BRKL_BIT2                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT2
    #define BRKL_BIT3                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT3
    #define BRKL_BIT4                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT4
    #define BRKL_BIT5                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT5
    #define BRKL_BIT6                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT6
    #define BRKL_BIT7                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT7
    
    #define BRKL_BIT0_MASK              1
    #define BRKL_BIT1_MASK              2
    #define BRKL_BIT2_MASK              4
    #define BRKL_BIT3_MASK              8
    #define BRKL_BIT4_MASK              16
    #define BRKL_BIT5_MASK              32
    #define BRKL_BIT6_MASK              64
    #define BRKL_BIT7_MASK              128
    
  } Overlap_STR;

} BRKSTR;
extern volatile BRKSTR _BRK;
#define BRK                             _BRK.Word


/*** BRKSCR - Break Status and Control Register; 0x0000FE0E ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BRKA        :1;                                       /* Break Active Bit */
    byte BRKE        :1;                                       /* Break Enable Bit */
  } Bits;
} BRKSCRSTR;
extern volatile BRKSCRSTR _BRKSCR;
#define BRKSCR                          _BRKSCR.Byte
#define BRKSCR_BRKA                     _BRKSCR.Bits.BRKA
#define BRKSCR_BRKE                     _BRKSCR.Bits.BRKE

#define BRKSCR_BRKA_MASK                64
#define BRKSCR_BRKE_MASK                128


/*** LVISR - LVI Status Register; 0x0000FE0F ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte LVIOUT      :1;                                       /* LVI Output Bit */
  } Bits;
} LVISRSTR;
extern volatile LVISRSTR _LVISR;
#define LVISR                           _LVISR.Byte
#define LVISR_LVIOUT                    _LVISR.Bits.LVIOUT

#define LVISR_LVIOUT_MASK               128


/*** MOR - Mask Option Register; 0x0000FF80 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte OSCSEL0     :1;                                       /* Oscillator Selection Bit 0 */
    byte OSCSEL1     :1;                                       /* Oscillator Selection Bit 1 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpOSCSEL :2;
  } MergedBits;
} MORSTR;
/* Tip for register initialization in the user code:  const byte MOR_INIT @0x0000FF80 = <MOR_INITVAL>; */
#define _MOR (*(const MORSTR * __far)0x0000FF80)
#define MOR                             _MOR.Byte
#define MOR_OSCSEL0                     _MOR.Bits.OSCSEL0
#define MOR_OSCSEL1                     _MOR.Bits.OSCSEL1
#define MOR_OSCSEL                      _MOR.MergedBits.grpOSCSEL

#define MOR_OSCSEL0_MASK                64
#define MOR_OSCSEL1_MASK                128
#define MOR_OSCSEL_MASK                 192
#define MOR_OSCSEL_BITNUM               6


/*** COPCTL - COP Control Register; 0x0000FFFF ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Bit 0 */
    byte BIT1        :1;                                       /* Bit 1 */
    byte BIT2        :1;                                       /* Bit 2 */
    byte BIT3        :1;                                       /* Bit 3 */
    byte BIT4        :1;                                       /* Bit 4 */
    byte BIT5        :1;                                       /* Bit 5 */
    byte BIT6        :1;                                       /* Bit 6 */
    byte BIT7        :1;                                       /* Bit 7 */
  } Bits;
} COPCTLSTR;
extern volatile COPCTLSTR _COPCTL;
#define COPCTL                          _COPCTL.Byte
#define COPCTL_BIT0                     _COPCTL.Bits.BIT0
#define COPCTL_BIT1                     _COPCTL.Bits.BIT1
#define COPCTL_BIT2                     _COPCTL.Bits.BIT2
#define COPCTL_BIT3                     _COPCTL.Bits.BIT3
#define COPCTL_BIT4                     _COPCTL.Bits.BIT4
#define COPCTL_BIT5                     _COPCTL.Bits.BIT5
#define COPCTL_BIT6                     _COPCTL.Bits.BIT6
#define COPCTL_BIT7                     _COPCTL.Bits.BIT7

#define COPCTL_BIT0_MASK                1
#define COPCTL_BIT1_MASK                2
#define COPCTL_BIT2_MASK                4
#define COPCTL_BIT3_MASK                8
#define COPCTL_BIT4_MASK                16
#define COPCTL_BIT5_MASK                32
#define COPCTL_BIT6_MASK                64
#define COPCTL_BIT7_MASK                128



/***********************************************/
/**   D E P R E C I A T E D   S Y M B O L S   **/
/***********************************************/
/* ---------------------------------------------------------------------------------------------------
Exceptions in bit names of timer status and control registers
due to backward compatibility with previous releases  */
#define T1SC0_CHxMAX _T1SC0.Bits.CH0MAX
#define T1SC0_TOVx _T1SC0.Bits.TOV0
#define T1SC0_ELSxA _T1SC0.Bits.ELS0A
#define T1SC0_ELSxB _T1SC0.Bits.ELS0B
#define T1SC0_MSxA _T1SC0.Bits.MS0A
#define T1SC0_MSxB _T1SC0.Bits.MS0B
#define T1SC0_CHxIE _T1SC0.Bits.CH0IE
#define T1SC0_CHxF _T1SC0.Bits.CH0F

#define T1SC1_CHxMAX _T1SC1.Bits.CH1MAX
#define T1SC1_TOVx _T1SC1.Bits.TOV1
#define T1SC1_ELSxA _T1SC1.Bits.ELS1A
#define T1SC1_ELSxB _T1SC1.Bits.ELS1B
#define T1SC1_MSxA _T1SC1.Bits.MS1A
#define T1SC1_CHxIE _T1SC1.Bits.CH1IE
#define T1SC1_CHxF _T1SC1.Bits.CH1F

#define T2SC0_CHxMAX _T2SC0.Bits.CH0MAX
#define T2SC0_TOVx _T2SC0.Bits.TOV0
#define T2SC0_ELSxA _T2SC0.Bits.ELS0A
#define T2SC0_ELSxB _T2SC0.Bits.ELS0B
#define T2SC0_MSxA _T2SC0.Bits.MS0A
#define T2SC0_MSxB _T2SC0.Bits.MS0B
#define T2SC0_CHxIE _T2SC0.Bits.CH0IE
#define T2SC0_CHxF _T2SC0.Bits.CH0F

#define T2SC1_CHxMAX _T2SC1.Bits.CH1MAX
#define T2SC1_TOVx _T2SC1.Bits.TOV1
#define T2SC1_ELSxA _T2SC1.Bits.ELS1A
#define T2SC1_ELSxB _T2SC1.Bits.ELS1B
#define T2SC1_MSxA _T2SC1.Bits.MS1A
#define T2SC1_CHxIE _T2SC1.Bits.CH1IE
#define T2SC1_CHxF _T2SC1.Bits.CH1F

/* --------------------------------------------------------------------------- */
/* The following symbols were removed, because they were invalid or irrelevant */
/* --------------------------------------------------------------------------- */
/*
 * Follows changes from the database 2.89.075 version */
#define ADSCR_CH0                        ADSCR_ADCH0
#define ADSCR_CH0_MASK                   ADSCR_ADCH0_MASK
#define ADSCR_CH1                        ADSCR_ADCH1
#define ADSCR_CH1_MASK                   ADSCR_ADCH1_MASK
#define ADSCR_CH2                        ADSCR_ADCH2
#define ADSCR_CH2_MASK                   ADSCR_ADCH2_MASK
#define ADSCR_CH3                        ADSCR_ADCH3
#define ADSCR_CH3_MASK                   ADSCR_ADCH3_MASK
#define ADSCR_CH4                        ADSCR_ADCH4
#define ADSCR_CH4_MASK                   ADSCR_ADCH4_MASK
#define ADSCR_CH                         ADSCR_ADCH
#define ADSCR_CH_BITNUM                  ADSCR_ADCH_BITNUM
#define ADSCR_CH_MASK                    ADSCR_ADCH_MASK


/* **** 11.9.2009 12:42:45 */

#define T1CH_ARR                         This_symb_has_been_depreciated
#define T2CH_ARR                         This_symb_has_been_depreciated
#endif
