/* Based on CPU DB MC68HC908EY16, version 2.89.092 (RegistersPrg V2.30) */
/*
** ###################################################################
**     Filename  : mc68hc908ey8.h
**     Processor : MC68HC908EY8KFA
**     FileFormat: V2.30
**     DataSheet : MC68HC908EY16 Rev. Rev. 10 10/2005
**     Compiler  : CodeWarrior compiler
**     Date/Time : 11.9.2009, 14:07
**     Abstract  :
**         This header implements the mapping of I/O devices.
**
**     Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved.
**     
**     http      : www.freescale.com
**     mail      : support@freescale.com
**
**     CPU Registers Revisions:
**               - none
**
**     File-Format-Revisions:
**      - 14.11.2005, V2.00 :
**               - Deprecated symbols added for backward compatibility (section at the end of this file)
**      - 15.11.2005, V2.01 :
**               - Changes have not affected this file (because they are related to another family)
**      - 17.12.2005, V2.02 :
**               - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778
**      - 16.01.2006, V2.03 :
**               - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920.
**               - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const")
**      - 08.03.2006, V2.04 :
**               - Support for bit(s) names duplicated with any register name in .h header files
**      - 24.03.2006, V2.05 :
**               - Changes have not affected this file (because they are related to another family)
**      - 26.04.2006, V2.06 :
**               - Absolute assembly supported (depreciated symbols are not defined)
**      - 27.04.2006, V2.07 :
**               - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA).
**      - 07.06.2006, V2.08 :
**               - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM.
**      - 03.07.2006, V2.09 :
**               - Flash commands constants supported
**      - 27.10.2006, V2.10 :
**               - __RESET_WATCHDOG improved formating and re-definition
**      - 23.11.2006, V2.11 :
**               - Changes have not affected this file (because they are related to another family)
**      - 22.01.2007, V2.12 :
**               - Changes have not affected this file (because they are related to another family)
**      - 01.03.2007, V2.13 :
**               - Flash commands constants values converted to HEX format
**      - 02.03.2007, V2.14 :
**               - Interrupt vector numbers added into .H, see VectorNumber_*
**      - 26.03.2007, V2.15 :
**               - Changes have not affected this file (because they are related to another family)
**      - 10.05.2007, V2.16 :
**               - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ)
**      - 05.06.2007, V2.17 :
**               - Changes have not affected this file (because they are related to another family)
**      - 19.07.2007, V2.18 :
**               - Improved number of blanked lines inside register structures
**      - 06.08.2007, V2.19 :
**               - CPUDB revisions generated ahead of the file-format revisions.
**      - 11.09.2007, V2.20 :
**               - Added comment about initialization of unbonded pins.
**      - 02.01.2008, V2.21 :
**               - Changes have not affected this file (because they are related to another family)
**      - 13.02.2008, V2.22 :
**               - Changes have not affected this file (because they are related to another family)
**      - 20.02.2008, V2.23 :
**               - Changes have not affected this file (because they are related to another family)
**      - 03.07.2008, V2.24 :
**               - Added support for bits with name starting with number (like "1HZ")
**      - 28.11.2008, V2.25 :
**               - StandBy RAM array declaration for ANSI-C added
**      - 1.12.2008, V2.26 :
**               - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map.
**      - 17.3.2009, V2.27 :
**               - Merged bit-group is not generated, if the name matches with another bit name in the register
**      - 6.4.2009, V2.28 :
**               - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB
**      - 3.8.2009, V2.29 :
**               - If there is just one bits group matching register name, single bits are not generated
**      - 10.9.2009, V2.30 :
**               - Fixed generation of registers arrays.
**
**     Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific
**     derivative device. To avoid extra current drain from floating input pins, the user’s reset
**     initialization routine in the application program must either enable on-chip pull-up devices
**     or change the direction of unconnected pins to outputs so the pins do not float.
** ###################################################################
*/

#ifndef _MC68HC908EY8_H
#define _MC68HC908EY8_H

/* Types definition */
typedef unsigned char byte;
typedef unsigned int word;
typedef unsigned long dword;
typedef unsigned long dlong[2];

/* Watchdog reset macro */
#ifndef __RESET_WATCHDOG
#ifdef _lint
  #define __RESET_WATCHDOG()  /* empty */
#else
  #define __RESET_WATCHDOG() {asm sta COPCTL;}
#endif
#endif /* __RESET_WATCHDOG */

#define REG_BASE 0x0000                /* Base address for the I/O register block */


#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */

/**************** interrupt vector numbers ****************/
#define VectorNumber_TBM                17
#define VectorNumber_SPITransmit        16
#define VectorNumber_SPIReceive         15
#define VectorNumber_ADC                14
#define VectorNumber_KBI                13
#define VectorNumber_SCITransmit        12
#define VectorNumber_SCIReceive         11
#define VectorNumber_SCIError           10
#define VectorNumber_TIMBOvr            9
#define VectorNumber_TIMBCH1            8
#define VectorNumber_TIMBCH0            7
#define VectorNumber_TIMAOvr            6
#define VectorNumber_TIMACH1            5
#define VectorNumber_TIMACH0            4
#define VectorNumber_ICG                3
#define VectorNumber_IRQ1               2
#define VectorNumber_SWI                1
#define VectorNumber_RESET              0

/**************** interrupt vector table ****************/
#define INT_TBM                         0x0000FFDC
#define INT_SPITransmit                 0x0000FFDE
#define INT_SPIReceive                  0x0000FFE0
#define INT_ADC                         0x0000FFE2
#define INT_KBI                         0x0000FFE4
#define INT_SCITransmit                 0x0000FFE6
#define INT_SCIReceive                  0x0000FFE8
#define INT_SCIError                    0x0000FFEA
#define INT_TIMBOvr                     0x0000FFEC
#define INT_TIMBCH1                     0x0000FFEE
#define INT_TIMBCH0                     0x0000FFF0
#define INT_TIMAOvr                     0x0000FFF2
#define INT_TIMACH1                     0x0000FFF4
#define INT_TIMACH0                     0x0000FFF6
#define INT_ICG                         0x0000FFF8
#define INT_IRQ1                        0x0000FFFA
#define INT_SWI                         0x0000FFFC
#define INT_RESET                       0x0000FFFE

/**************** registers I/O map ****************/

/*** PTA - Port A Data Register; 0x00000000 ***/
typedef union {
  byte Byte;
  struct {
    byte PTA0        :1;                                       /* Port A Data Bit 0 */
    byte PTA1        :1;                                       /* Port A Data Bit 1 */
    byte PTA2        :1;                                       /* Port A Data Bit 2 */
    byte PTA3        :1;                                       /* Port A Data Bit 3 */
    byte PTA4        :1;                                       /* Port A Data Bit 4 */
    byte PTA5        :1;                                       /* Port A Data Bit 5 */
    byte PTA6        :1;                                       /* Port A Data Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpPTA  :7;
    byte         :1;
  } MergedBits;
} PTASTR;
extern volatile PTASTR _PTA;
#define PTA                             _PTA.Byte
#define PTA_PTA0                        _PTA.Bits.PTA0
#define PTA_PTA1                        _PTA.Bits.PTA1
#define PTA_PTA2                        _PTA.Bits.PTA2
#define PTA_PTA3                        _PTA.Bits.PTA3
#define PTA_PTA4                        _PTA.Bits.PTA4
#define PTA_PTA5                        _PTA.Bits.PTA5
#define PTA_PTA6                        _PTA.Bits.PTA6
#define PTA_PTA                         _PTA.MergedBits.grpPTA

#define PTA_PTA0_MASK                   1
#define PTA_PTA1_MASK                   2
#define PTA_PTA2_MASK                   4
#define PTA_PTA3_MASK                   8
#define PTA_PTA4_MASK                   16
#define PTA_PTA5_MASK                   32
#define PTA_PTA6_MASK                   64
#define PTA_PTA_MASK                    127
#define PTA_PTA_BITNUM                  0


/*** PTB - Port B Data Register; 0x00000001 ***/
typedef union {
  byte Byte;
  struct {
    byte PTB0        :1;                                       /* Port B Data Bit 0 */
    byte PTB1        :1;                                       /* Port B Data Bit 1 */
    byte PTB2        :1;                                       /* Port B Data Bit 2 */
    byte PTB3        :1;                                       /* Port B Data Bit 3 */
    byte PTB4        :1;                                       /* Port B Data Bit 4 */
    byte PTB5        :1;                                       /* Port B Data Bit 5 */
    byte PTB6        :1;                                       /* Port B Data Bit 6 */
    byte PTB7        :1;                                       /* Port B Data Bit 7 */
  } Bits;
} PTBSTR;
extern volatile PTBSTR _PTB;
#define PTB                             _PTB.Byte
#define PTB_PTB0                        _PTB.Bits.PTB0
#define PTB_PTB1                        _PTB.Bits.PTB1
#define PTB_PTB2                        _PTB.Bits.PTB2
#define PTB_PTB3                        _PTB.Bits.PTB3
#define PTB_PTB4                        _PTB.Bits.PTB4
#define PTB_PTB5                        _PTB.Bits.PTB5
#define PTB_PTB6                        _PTB.Bits.PTB6
#define PTB_PTB7                        _PTB.Bits.PTB7

#define PTB_PTB0_MASK                   1
#define PTB_PTB1_MASK                   2
#define PTB_PTB2_MASK                   4
#define PTB_PTB3_MASK                   8
#define PTB_PTB4_MASK                   16
#define PTB_PTB5_MASK                   32
#define PTB_PTB6_MASK                   64
#define PTB_PTB7_MASK                   128


/*** PTC - Port C Data Register; 0x00000002 ***/
typedef union {
  byte Byte;
  struct {
    byte PTC0        :1;                                       /* Port C Data Bit 0 */
    byte PTC1        :1;                                       /* Port C Data Bit 1 */
    byte PTC2        :1;                                       /* Port C Data Bit 2 */
    byte PTC3        :1;                                       /* Port C Data Bit 3 */
    byte PTC4        :1;                                       /* Port C Data Bit 4 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpPTC  :5;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} PTCSTR;
extern volatile PTCSTR _PTC;
#define PTC                             _PTC.Byte
#define PTC_PTC0                        _PTC.Bits.PTC0
#define PTC_PTC1                        _PTC.Bits.PTC1
#define PTC_PTC2                        _PTC.Bits.PTC2
#define PTC_PTC3                        _PTC.Bits.PTC3
#define PTC_PTC4                        _PTC.Bits.PTC4
#define PTC_PTC                         _PTC.MergedBits.grpPTC

#define PTC_PTC0_MASK                   1
#define PTC_PTC1_MASK                   2
#define PTC_PTC2_MASK                   4
#define PTC_PTC3_MASK                   8
#define PTC_PTC4_MASK                   16
#define PTC_PTC_MASK                    31
#define PTC_PTC_BITNUM                  0


/*** PTD - Port D Data Register; 0x00000003 ***/
typedef union {
  byte Byte;
  struct {
    byte PTD0        :1;                                       /* Port D Data Bit 0 */
    byte PTD1        :1;                                       /* Port D Data Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpPTD  :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} PTDSTR;
extern volatile PTDSTR _PTD;
#define PTD                             _PTD.Byte
#define PTD_PTD0                        _PTD.Bits.PTD0
#define PTD_PTD1                        _PTD.Bits.PTD1
#define PTD_PTD                         _PTD.MergedBits.grpPTD

#define PTD_PTD0_MASK                   1
#define PTD_PTD1_MASK                   2
#define PTD_PTD_MASK                    3
#define PTD_PTD_BITNUM                  0


/*** DDRA - Data Direction Register A; 0x00000004 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRA0       :1;                                       /* Data Direction Register A Bit 0 */
    byte DDRA1       :1;                                       /* Data Direction Register A Bit 1 */
    byte DDRA2       :1;                                       /* Data Direction Register A Bit 2 */
    byte DDRA3       :1;                                       /* Data Direction Register A Bit 3 */
    byte DDRA4       :1;                                       /* Data Direction Register A Bit 4 */
    byte DDRA5       :1;                                       /* Data Direction Register A Bit 5 */
    byte DDRA6       :1;                                       /* Data Direction Register A Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpDDRA :7;
    byte         :1;
  } MergedBits;
} DDRASTR;
extern volatile DDRASTR _DDRA;
#define DDRA                            _DDRA.Byte
#define DDRA_DDRA0                      _DDRA.Bits.DDRA0
#define DDRA_DDRA1                      _DDRA.Bits.DDRA1
#define DDRA_DDRA2                      _DDRA.Bits.DDRA2
#define DDRA_DDRA3                      _DDRA.Bits.DDRA3
#define DDRA_DDRA4                      _DDRA.Bits.DDRA4
#define DDRA_DDRA5                      _DDRA.Bits.DDRA5
#define DDRA_DDRA6                      _DDRA.Bits.DDRA6
#define DDRA_DDRA                       _DDRA.MergedBits.grpDDRA

#define DDRA_DDRA0_MASK                 1
#define DDRA_DDRA1_MASK                 2
#define DDRA_DDRA2_MASK                 4
#define DDRA_DDRA3_MASK                 8
#define DDRA_DDRA4_MASK                 16
#define DDRA_DDRA5_MASK                 32
#define DDRA_DDRA6_MASK                 64
#define DDRA_DDRA_MASK                  127
#define DDRA_DDRA_BITNUM                0


/*** DDRB - Data Direction Register B; 0x00000005 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRB0       :1;                                       /* Data Direction Register B Bit 0 */
    byte DDRB1       :1;                                       /* Data Direction Register B Bit 1 */
    byte DDRB2       :1;                                       /* Data Direction Register B Bit 2 */
    byte DDRB3       :1;                                       /* Data Direction Register B Bit 3 */
    byte DDRB4       :1;                                       /* Data Direction Register B Bit 4 */
    byte DDRB5       :1;                                       /* Data Direction Register B Bit 5 */
    byte DDRB6       :1;                                       /* Data Direction Register B Bit 6 */
    byte DDRB7       :1;                                       /* Data Direction Register B Bit 7 */
  } Bits;
} DDRBSTR;
extern volatile DDRBSTR _DDRB;
#define DDRB                            _DDRB.Byte
#define DDRB_DDRB0                      _DDRB.Bits.DDRB0
#define DDRB_DDRB1                      _DDRB.Bits.DDRB1
#define DDRB_DDRB2                      _DDRB.Bits.DDRB2
#define DDRB_DDRB3                      _DDRB.Bits.DDRB3
#define DDRB_DDRB4                      _DDRB.Bits.DDRB4
#define DDRB_DDRB5                      _DDRB.Bits.DDRB5
#define DDRB_DDRB6                      _DDRB.Bits.DDRB6
#define DDRB_DDRB7                      _DDRB.Bits.DDRB7

#define DDRB_DDRB0_MASK                 1
#define DDRB_DDRB1_MASK                 2
#define DDRB_DDRB2_MASK                 4
#define DDRB_DDRB3_MASK                 8
#define DDRB_DDRB4_MASK                 16
#define DDRB_DDRB5_MASK                 32
#define DDRB_DDRB6_MASK                 64
#define DDRB_DDRB7_MASK                 128


/*** DDRC - Data Direction Register C; 0x00000006 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRC0       :1;                                       /* Data Direction Register C Bit 0 */
    byte DDRC1       :1;                                       /* Data Direction Register C Bit 1 */
    byte DDRC2       :1;                                       /* Data Direction Register C Bit 2 */
    byte DDRC3       :1;                                       /* Data Direction Register C Bit 3 */
    byte DDRC4       :1;                                       /* Data Direction Register C Bit 4 */
    byte             :1; 
    byte             :1; 
    byte MCLKEN      :1;                                       /* MCLK Enable Bit */
  } Bits;
  struct {
    byte grpDDRC :5;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DDRCSTR;
extern volatile DDRCSTR _DDRC;
#define DDRC                            _DDRC.Byte
#define DDRC_DDRC0                      _DDRC.Bits.DDRC0
#define DDRC_DDRC1                      _DDRC.Bits.DDRC1
#define DDRC_DDRC2                      _DDRC.Bits.DDRC2
#define DDRC_DDRC3                      _DDRC.Bits.DDRC3
#define DDRC_DDRC4                      _DDRC.Bits.DDRC4
#define DDRC_MCLKEN                     _DDRC.Bits.MCLKEN
#define DDRC_DDRC                       _DDRC.MergedBits.grpDDRC

#define DDRC_DDRC0_MASK                 1
#define DDRC_DDRC1_MASK                 2
#define DDRC_DDRC2_MASK                 4
#define DDRC_DDRC3_MASK                 8
#define DDRC_DDRC4_MASK                 16
#define DDRC_MCLKEN_MASK                128
#define DDRC_DDRC_MASK                  31
#define DDRC_DDRC_BITNUM                0


/*** DDRD - Data Direction Register D; 0x00000007 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRD0       :1;                                       /* Data Direction Register D Bit 0 */
    byte DDRD1       :1;                                       /* Data Direction Register D Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDDRD :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DDRDSTR;
extern volatile DDRDSTR _DDRD;
#define DDRD                            _DDRD.Byte
#define DDRD_DDRD0                      _DDRD.Bits.DDRD0
#define DDRD_DDRD1                      _DDRD.Bits.DDRD1
#define DDRD_DDRD                       _DDRD.MergedBits.grpDDRD

#define DDRD_DDRD0_MASK                 1
#define DDRD_DDRD1_MASK                 2
#define DDRD_DDRD_MASK                  3
#define DDRD_DDRD_BITNUM                0


/*** PTE - Port E Data Register; 0x00000008 ***/
typedef union {
  byte Byte;
  struct {
    byte PTE0        :1;                                       /* Port E Data Bit 0 */
    byte PTE1        :1;                                       /* Port E Data Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpPTE  :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} PTESTR;
extern volatile PTESTR _PTE;
#define PTE                             _PTE.Byte
#define PTE_PTE0                        _PTE.Bits.PTE0
#define PTE_PTE1                        _PTE.Bits.PTE1
#define PTE_PTE                         _PTE.MergedBits.grpPTE

#define PTE_PTE0_MASK                   1
#define PTE_PTE1_MASK                   2
#define PTE_PTE_MASK                    3
#define PTE_PTE_BITNUM                  0


/*** DDRE - Data Direction Register E; 0x0000000A ***/
typedef union {
  byte Byte;
  struct {
    byte DDRE0       :1;                                       /* Data Direction Register E Bit 0 */
    byte DDRE1       :1;                                       /* Data Direction Register E Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDDRE :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DDRESTR;
extern volatile DDRESTR _DDRE;
#define DDRE                            _DDRE.Byte
#define DDRE_DDRE0                      _DDRE.Bits.DDRE0
#define DDRE_DDRE1                      _DDRE.Bits.DDRE1
#define DDRE_DDRE                       _DDRE.MergedBits.grpDDRE

#define DDRE_DDRE0_MASK                 1
#define DDRE_DDRE1_MASK                 2
#define DDRE_DDRE_MASK                  3
#define DDRE_DDRE_BITNUM                0


/*** BEMF - BEMF Register; 0x0000000B ***/
typedef union {
  byte Byte;
  struct {
    byte BEMF0       :1;                                       /* BEMF Counter Bit 0 */
    byte BEMF1       :1;                                       /* BEMF Counter Bit 1 */
    byte BEMF2       :1;                                       /* BEMF Counter Bit 2 */
    byte BEMF3       :1;                                       /* BEMF Counter Bit 3 */
    byte BEMF4       :1;                                       /* BEMF Counter Bit 4 */
    byte BEMF5       :1;                                       /* BEMF Counter Bit 5 */
    byte BEMF6       :1;                                       /* BEMF Counter Bit 6 */
    byte BEMF7       :1;                                       /* BEMF Counter Bit 7 */
  } Bits;
} BEMFSTR;
extern volatile BEMFSTR _BEMF;
#define BEMF                            _BEMF.Byte
#define BEMF_BEMF0                      _BEMF.Bits.BEMF0
#define BEMF_BEMF1                      _BEMF.Bits.BEMF1
#define BEMF_BEMF2                      _BEMF.Bits.BEMF2
#define BEMF_BEMF3                      _BEMF.Bits.BEMF3
#define BEMF_BEMF4                      _BEMF.Bits.BEMF4
#define BEMF_BEMF5                      _BEMF.Bits.BEMF5
#define BEMF_BEMF6                      _BEMF.Bits.BEMF6
#define BEMF_BEMF7                      _BEMF.Bits.BEMF7

#define BEMF_BEMF0_MASK                 1
#define BEMF_BEMF1_MASK                 2
#define BEMF_BEMF2_MASK                 4
#define BEMF_BEMF3_MASK                 8
#define BEMF_BEMF4_MASK                 16
#define BEMF_BEMF5_MASK                 32
#define BEMF_BEMF6_MASK                 64
#define BEMF_BEMF7_MASK                 128


/*** SPCR - SPI Control Register; 0x0000000D ***/
typedef union {
  byte Byte;
  struct {
    byte SPTIE       :1;                                       /* SPI Transmit Interrupt Enable Bit */
    byte SPE         :1;                                       /* SPI Enable Bit */
    byte SPWOM       :1;                                       /* SPI Wired-OR Mode Bit */
    byte CPHA        :1;                                       /* Clock Phase Bit */
    byte CPOL        :1;                                       /* Clock Polarity Bit */
    byte SPMSTR      :1;                                       /* SPI Master Bit */
    byte             :1; 
    byte SPRIE       :1;                                       /* SPI Receiver Interrupt Enable Bit */
  } Bits;
} SPCRSTR;
extern volatile SPCRSTR _SPCR;
#define SPCR                            _SPCR.Byte
#define SPCR_SPTIE                      _SPCR.Bits.SPTIE
#define SPCR_SPE                        _SPCR.Bits.SPE
#define SPCR_SPWOM                      _SPCR.Bits.SPWOM
#define SPCR_CPHA                       _SPCR.Bits.CPHA
#define SPCR_CPOL                       _SPCR.Bits.CPOL
#define SPCR_SPMSTR                     _SPCR.Bits.SPMSTR
#define SPCR_SPRIE                      _SPCR.Bits.SPRIE

#define SPCR_SPTIE_MASK                 1
#define SPCR_SPE_MASK                   2
#define SPCR_SPWOM_MASK                 4
#define SPCR_CPHA_MASK                  8
#define SPCR_CPOL_MASK                  16
#define SPCR_SPMSTR_MASK                32
#define SPCR_SPRIE_MASK                 128


/*** SPSCR - SPI Status and Control Register; 0x0000000E ***/
typedef union {
  byte Byte;
  struct {
    byte SPR0        :1;                                       /* SPI Baud Rate Select Bit 0 */
    byte SPR1        :1;                                       /* SPI Baud Rate Select Bit 1 */
    byte MODFEN      :1;                                       /* Mode Fault Enable Bit */
    byte SPTE        :1;                                       /* SPI Transmitter Empty Bit */
    byte MODF        :1;                                       /* Mode Fault Bit */
    byte OVRF        :1;                                       /* Overflow Bit */
    byte ERRIE       :1;                                       /* Error Interrupt Enable Bit */
    byte SPRF        :1;                                       /* SPI Receiver Full Bit */
  } Bits;
  struct {
    byte grpSPR  :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} SPSCRSTR;
extern volatile SPSCRSTR _SPSCR;
#define SPSCR                           _SPSCR.Byte
#define SPSCR_SPR0                      _SPSCR.Bits.SPR0
#define SPSCR_SPR1                      _SPSCR.Bits.SPR1
#define SPSCR_MODFEN                    _SPSCR.Bits.MODFEN
#define SPSCR_SPTE                      _SPSCR.Bits.SPTE
#define SPSCR_MODF                      _SPSCR.Bits.MODF
#define SPSCR_OVRF                      _SPSCR.Bits.OVRF
#define SPSCR_ERRIE                     _SPSCR.Bits.ERRIE
#define SPSCR_SPRF                      _SPSCR.Bits.SPRF
#define SPSCR_SPR                       _SPSCR.MergedBits.grpSPR

#define SPSCR_SPR0_MASK                 1
#define SPSCR_SPR1_MASK                 2
#define SPSCR_MODFEN_MASK               4
#define SPSCR_SPTE_MASK                 8
#define SPSCR_MODF_MASK                 16
#define SPSCR_OVRF_MASK                 32
#define SPSCR_ERRIE_MASK                64
#define SPSCR_SPRF_MASK                 128
#define SPSCR_SPR_MASK                  3
#define SPSCR_SPR_BITNUM                0


/*** SPDR - SPI Data Register; 0x0000000F ***/
typedef union {
  byte Byte;
  struct {
    byte R0_T0       :1;                                       /* Receive/Transmit Data Bit 0 */
    byte R1_T1       :1;                                       /* Receive/Transmit Data Bit 1 */
    byte R2_T2       :1;                                       /* Receive/Transmit Data Bit 2 */
    byte R3_T3       :1;                                       /* Receive/Transmit Data Bit 3 */
    byte R4_T4       :1;                                       /* Receive/Transmit Data Bit 4 */
    byte R5_T5       :1;                                       /* Receive/Transmit Data Bit 5 */
    byte R6_T6       :1;                                       /* Receive/Transmit Data Bit 6 */
    byte R7_T7       :1;                                       /* Receive/Transmit Data Bit 7 */
  } Bits;
} SPDRSTR;
extern volatile SPDRSTR _SPDR;
#define SPDR                            _SPDR.Byte
#define SPDR_R0_T0                      _SPDR.Bits.R0_T0
#define SPDR_R1_T1                      _SPDR.Bits.R1_T1
#define SPDR_R2_T2                      _SPDR.Bits.R2_T2
#define SPDR_R3_T3                      _SPDR.Bits.R3_T3
#define SPDR_R4_T4                      _SPDR.Bits.R4_T4
#define SPDR_R5_T5                      _SPDR.Bits.R5_T5
#define SPDR_R6_T6                      _SPDR.Bits.R6_T6
#define SPDR_R7_T7                      _SPDR.Bits.R7_T7

#define SPDR_R0_T0_MASK                 1
#define SPDR_R1_T1_MASK                 2
#define SPDR_R2_T2_MASK                 4
#define SPDR_R3_T3_MASK                 8
#define SPDR_R4_T4_MASK                 16
#define SPDR_R5_T5_MASK                 32
#define SPDR_R6_T6_MASK                 64
#define SPDR_R7_T7_MASK                 128


/*** SCC1 - ESCI Control Register 1; 0x00000010 ***/
typedef union {
  byte Byte;
  struct {
    byte PTY         :1;                                       /* Parity Bit */
    byte PEN         :1;                                       /* Parity Enable Bit */
    byte ILTY        :1;                                       /* Idle Line Type Bit */
    byte WAKE        :1;                                       /* Wakeup Condition Bit */
    byte M           :1;                                       /* Mode (Character Length) Bit */
    byte TXINV       :1;                                       /* Transmit Inversion Bit */
    byte ENSCI       :1;                                       /* Enable SCI Bit */
    byte LOOPS       :1;                                       /* Loop Mode Select Bit */
  } Bits;
} SCC1STR;
extern volatile SCC1STR _SCC1;
#define SCC1                            _SCC1.Byte
#define SCC1_PTY                        _SCC1.Bits.PTY
#define SCC1_PEN                        _SCC1.Bits.PEN
#define SCC1_ILTY                       _SCC1.Bits.ILTY
#define SCC1_WAKE                       _SCC1.Bits.WAKE
#define SCC1_M                          _SCC1.Bits.M
#define SCC1_TXINV                      _SCC1.Bits.TXINV
#define SCC1_ENSCI                      _SCC1.Bits.ENSCI
#define SCC1_LOOPS                      _SCC1.Bits.LOOPS

#define SCC1_PTY_MASK                   1
#define SCC1_PEN_MASK                   2
#define SCC1_ILTY_MASK                  4
#define SCC1_WAKE_MASK                  8
#define SCC1_M_MASK                     16
#define SCC1_TXINV_MASK                 32
#define SCC1_ENSCI_MASK                 64
#define SCC1_LOOPS_MASK                 128


/*** SCC2 - ESCI Control Register 2; 0x00000011 ***/
typedef union {
  byte Byte;
  struct {
    byte SBK         :1;                                       /* Send Break Bit */
    byte RWU         :1;                                       /* Receiver Wakeup Bit */
    byte RE          :1;                                       /* Receiver Enable Bit */
    byte TE          :1;                                       /* Transmitter Enable Bit */
    byte ILIE        :1;                                       /* Idle Line Interrupt Enable Bit */
    byte SCRIE       :1;                                       /* ESCI Receive Interrupt Enable Bit */
    byte TCIE        :1;                                       /* Transmission Complete Interrupt Enable Bit */
    byte SCTIE       :1;                                       /* ESCI Transmit Interrupt Enable Bit */
  } Bits;
} SCC2STR;
extern volatile SCC2STR _SCC2;
#define SCC2                            _SCC2.Byte
#define SCC2_SBK                        _SCC2.Bits.SBK
#define SCC2_RWU                        _SCC2.Bits.RWU
#define SCC2_RE                         _SCC2.Bits.RE
#define SCC2_TE                         _SCC2.Bits.TE
#define SCC2_ILIE                       _SCC2.Bits.ILIE
#define SCC2_SCRIE                      _SCC2.Bits.SCRIE
#define SCC2_TCIE                       _SCC2.Bits.TCIE
#define SCC2_SCTIE                      _SCC2.Bits.SCTIE

#define SCC2_SBK_MASK                   1
#define SCC2_RWU_MASK                   2
#define SCC2_RE_MASK                    4
#define SCC2_TE_MASK                    8
#define SCC2_ILIE_MASK                  16
#define SCC2_SCRIE_MASK                 32
#define SCC2_TCIE_MASK                  64
#define SCC2_SCTIE_MASK                 128


/*** SCC3 - ESCI Control Register 3; 0x00000012 ***/
typedef union {
  byte Byte;
  struct {
    byte PEIE        :1;                                       /* Receiver Parity Error Interrupt Enable Bit */
    byte FEIE        :1;                                       /* Receiver Framing Error Interrupt Enable Bit */
    byte NEIE        :1;                                       /* Receiver Noise Error Interrupt Enable Bit */
    byte ORIE        :1;                                       /* Receiver Overrun Interrupt Enable Bit */
    byte             :1; 
    byte             :1; 
    byte T8          :1;                                       /* Transmitted Bit 8 */
    byte R8          :1;                                       /* Received Bit 8 */
  } Bits;
} SCC3STR;
extern volatile SCC3STR _SCC3;
#define SCC3                            _SCC3.Byte
#define SCC3_PEIE                       _SCC3.Bits.PEIE
#define SCC3_FEIE                       _SCC3.Bits.FEIE
#define SCC3_NEIE                       _SCC3.Bits.NEIE
#define SCC3_ORIE                       _SCC3.Bits.ORIE
#define SCC3_T8                         _SCC3.Bits.T8
#define SCC3_R8                         _SCC3.Bits.R8

#define SCC3_PEIE_MASK                  1
#define SCC3_FEIE_MASK                  2
#define SCC3_NEIE_MASK                  4
#define SCC3_ORIE_MASK                  8
#define SCC3_T8_MASK                    64
#define SCC3_R8_MASK                    128


/*** SCS1 - SCI Status Register 1; 0x00000013 ***/
typedef union {
  byte Byte;
  struct {
    byte PE          :1;                                       /* Receiver Parity Error Bit */
    byte FE          :1;                                       /* Receiver Framing Error Bit */
    byte NF          :1;                                       /* Receiver Noise Flag Bit */
    byte OR          :1;                                       /* Receiver Overrun Bit */
    byte IDLE        :1;                                       /* Receiver Idle Bit */
    byte SCRF        :1;                                       /* ESCI Receiver Full Bit */
    byte TC          :1;                                       /* Transmission Complete Bit */
    byte SCTE        :1;                                       /* ESCI Transmitter Empty Bit */
  } Bits;
} SCS1STR;
extern volatile SCS1STR _SCS1;
#define SCS1                            _SCS1.Byte
#define SCS1_PE                         _SCS1.Bits.PE
#define SCS1_FE                         _SCS1.Bits.FE
#define SCS1_NF                         _SCS1.Bits.NF
#define SCS1_OR                         _SCS1.Bits.OR
#define SCS1_IDLE                       _SCS1.Bits.IDLE
#define SCS1_SCRF                       _SCS1.Bits.SCRF
#define SCS1_TC                         _SCS1.Bits.TC
#define SCS1_SCTE                       _SCS1.Bits.SCTE

#define SCS1_PE_MASK                    1
#define SCS1_FE_MASK                    2
#define SCS1_NF_MASK                    4
#define SCS1_OR_MASK                    8
#define SCS1_IDLE_MASK                  16
#define SCS1_SCRF_MASK                  32
#define SCS1_TC_MASK                    64
#define SCS1_SCTE_MASK                  128


/*** SCS2 - SCI Status Register 2; 0x00000014 ***/
typedef union {
  byte Byte;
  struct {
    byte RPF         :1;                                       /* Reception in Progress Flag Bit */
    byte BKF         :1;                                       /* Break Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SCS2STR;
extern volatile SCS2STR _SCS2;
#define SCS2                            _SCS2.Byte
#define SCS2_RPF                        _SCS2.Bits.RPF
#define SCS2_BKF                        _SCS2.Bits.BKF

#define SCS2_RPF_MASK                   1
#define SCS2_BKF_MASK                   2


/*** SCDR - SCI Data Register; 0x00000015 ***/
typedef union {
  byte Byte;
  struct {
    byte R0_T0       :1;                                       /* Receive/Transmit Data Bit 0 */
    byte R1_T1       :1;                                       /* Receive/Transmit Data Bit 1 */
    byte R2_T2       :1;                                       /* Receive/Transmit Data Bit 2 */
    byte R3_T3       :1;                                       /* Receive/Transmit Data Bit 3 */
    byte R4_T4       :1;                                       /* Receive/Transmit Data Bit 4 */
    byte R5_T5       :1;                                       /* Receive/Transmit Data Bit 5 */
    byte R6_T6       :1;                                       /* Receive/Transmit Data Bit 6 */
    byte R7_T7       :1;                                       /* Receive/Transmit Data Bit 7 */
  } Bits;
} SCDRSTR;
extern volatile SCDRSTR _SCDR;
#define SCDR                            _SCDR.Byte
#define SCDR_R0_T0                      _SCDR.Bits.R0_T0
#define SCDR_R1_T1                      _SCDR.Bits.R1_T1
#define SCDR_R2_T2                      _SCDR.Bits.R2_T2
#define SCDR_R3_T3                      _SCDR.Bits.R3_T3
#define SCDR_R4_T4                      _SCDR.Bits.R4_T4
#define SCDR_R5_T5                      _SCDR.Bits.R5_T5
#define SCDR_R6_T6                      _SCDR.Bits.R6_T6
#define SCDR_R7_T7                      _SCDR.Bits.R7_T7

#define SCDR_R0_T0_MASK                 1
#define SCDR_R1_T1_MASK                 2
#define SCDR_R2_T2_MASK                 4
#define SCDR_R3_T3_MASK                 8
#define SCDR_R4_T4_MASK                 16
#define SCDR_R5_T5_MASK                 32
#define SCDR_R6_T6_MASK                 64
#define SCDR_R7_T7_MASK                 128


/*** SCBR - SCI Baud Rate Register; 0x00000016 ***/
typedef union {
  byte Byte;
  struct {
    byte SCR0        :1;                                       /* ESCI Baud Rate Select Bit 0 */
    byte SCR1        :1;                                       /* ESCI Baud Rate Select Bit 1 */
    byte SCR2        :1;                                       /* ESCI Baud Rate Select Bit 2 */
    byte             :1; 
    byte SCP0        :1;                                       /* ESCI Baud Rate Prescaler Bit 0 */
    byte SCP1        :1;                                       /* ESCI Baud Rate Prescaler Bit 1 */
    byte LINR        :1;                                       /* LIN Receiver Bit */
    byte             :1; 
  } Bits;
  struct {
    byte grpSCR  :3;
    byte         :1;
    byte grpSCP  :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} SCBRSTR;
extern volatile SCBRSTR _SCBR;
#define SCBR                            _SCBR.Byte
#define SCBR_SCR0                       _SCBR.Bits.SCR0
#define SCBR_SCR1                       _SCBR.Bits.SCR1
#define SCBR_SCR2                       _SCBR.Bits.SCR2
#define SCBR_SCP0                       _SCBR.Bits.SCP0
#define SCBR_SCP1                       _SCBR.Bits.SCP1
#define SCBR_LINR                       _SCBR.Bits.LINR
#define SCBR_SCR                        _SCBR.MergedBits.grpSCR
#define SCBR_SCP                        _SCBR.MergedBits.grpSCP

#define SCBR_SCR0_MASK                  1
#define SCBR_SCR1_MASK                  2
#define SCBR_SCR2_MASK                  4
#define SCBR_SCP0_MASK                  16
#define SCBR_SCP1_MASK                  32
#define SCBR_LINR_MASK                  64
#define SCBR_SCR_MASK                   7
#define SCBR_SCR_BITNUM                 0
#define SCBR_SCP_MASK                   48
#define SCBR_SCP_BITNUM                 4


/*** SCPSC - ESCI Prescale Register; 0x00000017 ***/
typedef union {
  byte Byte;
  struct {
    byte PSSB0       :1;                                       /* Clock Insertion Select Bit 0 */
    byte PSSB1       :1;                                       /* Clock Insertion Select Bit 1 */
    byte PSSB2       :1;                                       /* Clock Insertion Select Bit 2 */
    byte PSSB3       :1;                                       /* Clock Insertion Select Bit 3 */
    byte PSSB4       :1;                                       /* Clock Insertion Select Bit 4 */
    byte PDS0        :1;                                       /* Prescaler Divisor Select Bit 0 */
    byte PDS1        :1;                                       /* Prescaler Divisor Select Bit 1 */
    byte PDS2        :1;                                       /* Prescaler Divisor Select Bit 2 */
  } Bits;
  struct {
    byte grpPSSB :5;
    byte grpPDS  :3;
  } MergedBits;
} SCPSCSTR;
extern volatile SCPSCSTR _SCPSC;
#define SCPSC                           _SCPSC.Byte
#define SCPSC_PSSB0                     _SCPSC.Bits.PSSB0
#define SCPSC_PSSB1                     _SCPSC.Bits.PSSB1
#define SCPSC_PSSB2                     _SCPSC.Bits.PSSB2
#define SCPSC_PSSB3                     _SCPSC.Bits.PSSB3
#define SCPSC_PSSB4                     _SCPSC.Bits.PSSB4
#define SCPSC_PDS0                      _SCPSC.Bits.PDS0
#define SCPSC_PDS1                      _SCPSC.Bits.PDS1
#define SCPSC_PDS2                      _SCPSC.Bits.PDS2
#define SCPSC_PSSB                      _SCPSC.MergedBits.grpPSSB
#define SCPSC_PDS                       _SCPSC.MergedBits.grpPDS

#define SCPSC_PSSB0_MASK                1
#define SCPSC_PSSB1_MASK                2
#define SCPSC_PSSB2_MASK                4
#define SCPSC_PSSB3_MASK                8
#define SCPSC_PSSB4_MASK                16
#define SCPSC_PDS0_MASK                 32
#define SCPSC_PDS1_MASK                 64
#define SCPSC_PDS2_MASK                 128
#define SCPSC_PSSB_MASK                 31
#define SCPSC_PSSB_BITNUM               0
#define SCPSC_PDS_MASK                  224
#define SCPSC_PDS_BITNUM                5


/*** SCIACTL - ESCI Arbiter Control Register; 0x00000018 ***/
typedef union {
  byte Byte;
  struct {
    byte ARD8        :1;                                       /* Arbiter Counter MSB */
    byte AROVFL      :1;                                       /* Arbiter Counter Overflow Bit */
    byte ARUN        :1;                                       /* Arbiter Counter Running Flag */
    byte AFIN        :1;                                       /* Arbiter Bit Time Measurement Finish Flag */
    byte ACLK        :1;                                       /* Arbiter Counter Clock Select Bit */
    byte AM0         :1;                                       /* Arbiter Mode Select Bit 0 */
    byte ALOST       :1;                                       /* Arbitration Lost Flag */
    byte AM1         :1;                                       /* Arbiter Mode Select Bit 1 */
  } Bits;
} SCIACTLSTR;
extern volatile SCIACTLSTR _SCIACTL;
#define SCIACTL                         _SCIACTL.Byte
#define SCIACTL_ARD8                    _SCIACTL.Bits.ARD8
#define SCIACTL_AROVFL                  _SCIACTL.Bits.AROVFL
#define SCIACTL_ARUN                    _SCIACTL.Bits.ARUN
#define SCIACTL_AFIN                    _SCIACTL.Bits.AFIN
#define SCIACTL_ACLK                    _SCIACTL.Bits.ACLK
#define SCIACTL_AM0                     _SCIACTL.Bits.AM0
#define SCIACTL_ALOST                   _SCIACTL.Bits.ALOST
#define SCIACTL_AM1                     _SCIACTL.Bits.AM1

#define SCIACTL_ARD8_MASK               1
#define SCIACTL_AROVFL_MASK             2
#define SCIACTL_ARUN_MASK               4
#define SCIACTL_AFIN_MASK               8
#define SCIACTL_ACLK_MASK               16
#define SCIACTL_AM0_MASK                32
#define SCIACTL_ALOST_MASK              64
#define SCIACTL_AM1_MASK                128


/*** SCIADAT - ESCI Arbiter Data Register; 0x00000019 ***/
typedef union {
  byte Byte;
  struct {
    byte ARD0        :1;                                       /* Arbiter Least Significant Counter Bit 0 */
    byte ARD1        :1;                                       /* Arbiter Least Significant Counter Bit 1 */
    byte ARD2        :1;                                       /* Arbiter Least Significant Counter Bit 2 */
    byte ARD3        :1;                                       /* Arbiter Least Significant Counter Bit 3 */
    byte ARD4        :1;                                       /* Arbiter Least Significant Counter Bit 4 */
    byte ARD5        :1;                                       /* Arbiter Least Significant Counter Bit 5 */
    byte ARD6        :1;                                       /* Arbiter Least Significant Counter Bit 6 */
    byte ARD7        :1;                                       /* Arbiter Least Significant Counter Bit 7 */
  } Bits;
} SCIADATSTR;
extern volatile SCIADATSTR _SCIADAT;
#define SCIADAT                         _SCIADAT.Byte
#define SCIADAT_ARD0                    _SCIADAT.Bits.ARD0
#define SCIADAT_ARD1                    _SCIADAT.Bits.ARD1
#define SCIADAT_ARD2                    _SCIADAT.Bits.ARD2
#define SCIADAT_ARD3                    _SCIADAT.Bits.ARD3
#define SCIADAT_ARD4                    _SCIADAT.Bits.ARD4
#define SCIADAT_ARD5                    _SCIADAT.Bits.ARD5
#define SCIADAT_ARD6                    _SCIADAT.Bits.ARD6
#define SCIADAT_ARD7                    _SCIADAT.Bits.ARD7

#define SCIADAT_ARD0_MASK               1
#define SCIADAT_ARD1_MASK               2
#define SCIADAT_ARD2_MASK               4
#define SCIADAT_ARD3_MASK               8
#define SCIADAT_ARD4_MASK               16
#define SCIADAT_ARD5_MASK               32
#define SCIADAT_ARD6_MASK               64
#define SCIADAT_ARD7_MASK               128


/*** INTKBSCR - Keyboard Status and Control Register; 0x0000001A ***/
typedef union {
  byte Byte;
  struct {
    byte MODEK       :1;                                       /* Keyboard Triggering Sensitivity Bit */
    byte IMASKK      :1;                                       /* Keyboard Interrupt Mask Bit */
    byte ACKK        :1;                                       /* Keyboard Acknowledge Bit */
    byte KEYF        :1;                                       /* Keyboard Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} INTKBSCRSTR;
extern volatile INTKBSCRSTR _INTKBSCR;
#define INTKBSCR                        _INTKBSCR.Byte
#define INTKBSCR_MODEK                  _INTKBSCR.Bits.MODEK
#define INTKBSCR_IMASKK                 _INTKBSCR.Bits.IMASKK
#define INTKBSCR_ACKK                   _INTKBSCR.Bits.ACKK
#define INTKBSCR_KEYF                   _INTKBSCR.Bits.KEYF

#define INTKBSCR_MODEK_MASK             1
#define INTKBSCR_IMASKK_MASK            2
#define INTKBSCR_ACKK_MASK              4
#define INTKBSCR_KEYF_MASK              8


/*** INTKBIER - Keyboard Interrupt Enable Register; 0x0000001B ***/
typedef union {
  byte Byte;
  struct {
    byte KBIE0       :1;                                       /* Keyboard Interrupt Enable Bit 0 */
    byte KBIE1       :1;                                       /* Keyboard Interrupt Enable Bit 1 */
    byte KBIE2       :1;                                       /* Keyboard Interrupt Enable Bit 2 */
    byte KBIE3       :1;                                       /* Keyboard Interrupt Enable Bit 3 */
    byte KBIE4       :1;                                       /* Keyboard Interrupt Enable Bit 4 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpKBIE :5;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} INTKBIERSTR;
extern volatile INTKBIERSTR _INTKBIER;
#define INTKBIER                        _INTKBIER.Byte
#define INTKBIER_KBIE0                  _INTKBIER.Bits.KBIE0
#define INTKBIER_KBIE1                  _INTKBIER.Bits.KBIE1
#define INTKBIER_KBIE2                  _INTKBIER.Bits.KBIE2
#define INTKBIER_KBIE3                  _INTKBIER.Bits.KBIE3
#define INTKBIER_KBIE4                  _INTKBIER.Bits.KBIE4
#define INTKBIER_KBIE                   _INTKBIER.MergedBits.grpKBIE

#define INTKBIER_KBIE0_MASK             1
#define INTKBIER_KBIE1_MASK             2
#define INTKBIER_KBIE2_MASK             4
#define INTKBIER_KBIE3_MASK             8
#define INTKBIER_KBIE4_MASK             16
#define INTKBIER_KBIE_MASK              31
#define INTKBIER_KBIE_BITNUM            0


/*** TBCR - Timebase Control Register; 0x0000001C ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte TBON        :1;                                       /* Timebase Enabled Bit */
    byte TBIE        :1;                                       /* Timebase Interrupt Enabled Bit */
    byte TACK        :1;                                       /* Timebase ACKnowledge Bit */
    byte TBR0        :1;                                       /* Timebase Divider Selection Bit 0 */
    byte TBR1        :1;                                       /* Timebase Divider Selection Bit 1 */
    byte TBR2        :1;                                       /* Timebase Divider Selection Bit 2 */
    byte TBIF        :1;                                       /* Timebase Interrupt Flag */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpTBR  :3;
    byte         :1;
  } MergedBits;
} TBCRSTR;
extern volatile TBCRSTR _TBCR;
#define TBCR                            _TBCR.Byte
#define TBCR_TBON                       _TBCR.Bits.TBON
#define TBCR_TBIE                       _TBCR.Bits.TBIE
#define TBCR_TACK                       _TBCR.Bits.TACK
#define TBCR_TBR0                       _TBCR.Bits.TBR0
#define TBCR_TBR1                       _TBCR.Bits.TBR1
#define TBCR_TBR2                       _TBCR.Bits.TBR2
#define TBCR_TBIF                       _TBCR.Bits.TBIF
#define TBCR_TBR                        _TBCR.MergedBits.grpTBR

#define TBCR_TBON_MASK                  2
#define TBCR_TBIE_MASK                  4
#define TBCR_TACK_MASK                  8
#define TBCR_TBR0_MASK                  16
#define TBCR_TBR1_MASK                  32
#define TBCR_TBR2_MASK                  64
#define TBCR_TBIF_MASK                  128
#define TBCR_TBR_MASK                   112
#define TBCR_TBR_BITNUM                 4


/*** ISCR - IRQ Status and Control Register; 0x0000001D ***/
typedef union {
  byte Byte;
  struct {
    byte MODE        :1;                                       /* IRQ Edge/Level Select Bit */
    byte IMASK       :1;                                       /* IRQ Interrupt Mask Bit */
    byte ACK         :1;                                       /* IRQ Interrupt Request Acknowledge Bit */
    byte IRQF        :1;                                       /* IRQ Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} ISCRSTR;
extern volatile ISCRSTR _ISCR;
#define ISCR                            _ISCR.Byte
#define ISCR_MODE                       _ISCR.Bits.MODE
#define ISCR_IMASK                      _ISCR.Bits.IMASK
#define ISCR_ACK                        _ISCR.Bits.ACK
#define ISCR_IRQF                       _ISCR.Bits.IRQF

#define ISCR_MODE_MASK                  1
#define ISCR_IMASK_MASK                 2
#define ISCR_ACK_MASK                   4
#define ISCR_IRQF_MASK                  8


/*** CONFIG2 - Configuration Register; 0x0000001E ***/
typedef union {
  byte Byte;
  struct {
    byte SSBPUENB    :1;                                       /* SSB Pull-up Enable Bit */
    byte OSCENINSTOP :1;                                       /* Oscillator Enable In Stop Mode Bit */
    byte TMBCLKSEL   :1;                                       /* Timebase Clock Select Bit */
    byte EXTCLKEN    :1;                                       /* External Clock Enable Bit */
    byte EXTSLOW     :1;                                       /* Slow External Crystal Enable Bit */
    byte EXTXTALEN   :1;                                       /* External Crystal Enable Bit */
    byte ESCIBDSRC   :1;                                       /* ESCI Baud Rate Clock Source Bit */
    byte             :1; 
  } Bits;
} CONFIG2STR;
extern volatile CONFIG2STR _CONFIG2;
#define CONFIG2                         _CONFIG2.Byte
#define CONFIG2_SSBPUENB                _CONFIG2.Bits.SSBPUENB
#define CONFIG2_OSCENINSTOP             _CONFIG2.Bits.OSCENINSTOP
#define CONFIG2_TMBCLKSEL               _CONFIG2.Bits.TMBCLKSEL
#define CONFIG2_EXTCLKEN                _CONFIG2.Bits.EXTCLKEN
#define CONFIG2_EXTSLOW                 _CONFIG2.Bits.EXTSLOW
#define CONFIG2_EXTXTALEN               _CONFIG2.Bits.EXTXTALEN
#define CONFIG2_ESCIBDSRC               _CONFIG2.Bits.ESCIBDSRC

#define CONFIG2_SSBPUENB_MASK           1
#define CONFIG2_OSCENINSTOP_MASK        2
#define CONFIG2_TMBCLKSEL_MASK          4
#define CONFIG2_EXTCLKEN_MASK           8
#define CONFIG2_EXTSLOW_MASK            16
#define CONFIG2_EXTXTALEN_MASK          32
#define CONFIG2_ESCIBDSRC_MASK          64


/*** CONFIG1 - Configuration Register; 0x0000001F ***/
typedef union {
  byte Byte;
  struct {
    byte COPD        :1;                                       /* COP Disable Bit */
    byte STOP        :1;                                       /* STOP Instruction Enable Bit */
    byte SSREC       :1;                                       /* Short Stop Recovery Bit */
    byte LVI5OR3     :1;                                       /* LVI 5-V or 3-V Operating Mode Bit */
    byte LVIPWRD     :1;                                       /* LVI Power Disable Bit */
    byte LVIRSTD     :1;                                       /* LVI Reset Disable Bit */
    byte LVISTOP     :1;                                       /* LVI Enable in Stop Mode Bit */
    byte COPRS       :1;                                       /* COP Rate Select Bit */
  } Bits;
} CONFIG1STR;
extern volatile CONFIG1STR _CONFIG1;
#define CONFIG1                         _CONFIG1.Byte
#define CONFIG1_COPD                    _CONFIG1.Bits.COPD
#define CONFIG1_STOP                    _CONFIG1.Bits.STOP
#define CONFIG1_SSREC                   _CONFIG1.Bits.SSREC
#define CONFIG1_LVI5OR3                 _CONFIG1.Bits.LVI5OR3
#define CONFIG1_LVIPWRD                 _CONFIG1.Bits.LVIPWRD
#define CONFIG1_LVIRSTD                 _CONFIG1.Bits.LVIRSTD
#define CONFIG1_LVISTOP                 _CONFIG1.Bits.LVISTOP
#define CONFIG1_COPRS                   _CONFIG1.Bits.COPRS

#define CONFIG1_COPD_MASK               1
#define CONFIG1_STOP_MASK               2
#define CONFIG1_SSREC_MASK              4
#define CONFIG1_LVI5OR3_MASK            8
#define CONFIG1_LVIPWRD_MASK            16
#define CONFIG1_LVIRSTD_MASK            32
#define CONFIG1_LVISTOP_MASK            64
#define CONFIG1_COPRS_MASK              128


/*** TASC - TIMA Status/Control Register; 0x00000020 ***/
typedef union {
  byte Byte;
  struct {
    byte PS0         :1;                                       /* Prescaler Select Bit 0 */
    byte PS1         :1;                                       /* Prescaler Select Bit 1 */
    byte PS2         :1;                                       /* Prescaler Select Bit 2 */
    byte             :1; 
    byte TRST        :1;                                       /* TIMA Reset Bit */
    byte TSTOP       :1;                                       /* TIMA Stop Bit */
    byte TOIE        :1;                                       /* TIMA Overflow Interrupt Enable Bit */
    byte TOF         :1;                                       /* TIMA Overflow Flag Bit */
  } Bits;
  struct {
    byte grpPS   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TASCSTR;
extern volatile TASCSTR _TASC;
#define TASC                            _TASC.Byte
#define TASC_PS0                        _TASC.Bits.PS0
#define TASC_PS1                        _TASC.Bits.PS1
#define TASC_PS2                        _TASC.Bits.PS2
#define TASC_TRST                       _TASC.Bits.TRST
#define TASC_TSTOP                      _TASC.Bits.TSTOP
#define TASC_TOIE                       _TASC.Bits.TOIE
#define TASC_TOF                        _TASC.Bits.TOF
#define TASC_PS                         _TASC.MergedBits.grpPS

#define TASC_PS0_MASK                   1
#define TASC_PS1_MASK                   2
#define TASC_PS2_MASK                   4
#define TASC_TRST_MASK                  16
#define TASC_TSTOP_MASK                 32
#define TASC_TOIE_MASK                  64
#define TASC_TOF_MASK                   128
#define TASC_PS_MASK                    7
#define TASC_PS_BITNUM                  0


/*** TACNT - TIMA Counter Register; 0x00000021 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TACNTH - TIMA Counter Register High; 0x00000021 ***/
    union {
      byte Byte;
    } TACNTHSTR;
    #define TACNTH                      _TACNT.Overlap_STR.TACNTHSTR.Byte
    

    /*** TACNTL - TIMA Counter Register Low; 0x00000022 ***/
    union {
      byte Byte;
    } TACNTLSTR;
    #define TACNTL                      _TACNT.Overlap_STR.TACNTLSTR.Byte
    
  } Overlap_STR;

} TACNTSTR;
extern volatile TACNTSTR _TACNT;
#define TACNT                           _TACNT.Word


/*** TAMOD - TIMA Counter Modulo Register; 0x00000023 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TAMODH - TIMA Counter Modulo Register; 0x00000023 ***/
    union {
      byte Byte;
    } TAMODHSTR;
    #define TAMODH                      _TAMOD.Overlap_STR.TAMODHSTR.Byte
    

    /*** TAMODL - TIMA Counter Modulo Register; 0x00000024 ***/
    union {
      byte Byte;
    } TAMODLSTR;
    #define TAMODL                      _TAMOD.Overlap_STR.TAMODLSTR.Byte
    
  } Overlap_STR;

} TAMODSTR;
extern volatile TAMODSTR _TAMOD;
#define TAMOD                           _TAMOD.Word


/*** TASC0 - TIMA Channel 0 Status/Control Register; 0x00000025 ***/
typedef union {
  byte Byte;
  struct {
    byte CH0MAX      :1;                                       /* Channel 0 Maximum Duty Cycle Bit */
    byte TOV0        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS0A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS0B       :1;                                       /* Edge/Level Select Bit B */
    byte MS0A        :1;                                       /* Mode Select Bit A */
    byte MS0B        :1;                                       /* Mode Select Bit B */
    byte CH0IE       :1;                                       /* Channel 0 Interrupt Enable Bit */
    byte CH0F        :1;                                       /* Channel 0 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV  :1;
    byte grpELS0x :2;
    byte grpMS0x :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} TASC0STR;
extern volatile TASC0STR _TASC0;
#define TASC0                           _TASC0.Byte
#define TASC0_CH0MAX                    _TASC0.Bits.CH0MAX
#define TASC0_TOV0                      _TASC0.Bits.TOV0
#define TASC0_ELS0A                     _TASC0.Bits.ELS0A
#define TASC0_ELS0B                     _TASC0.Bits.ELS0B
#define TASC0_MS0A                      _TASC0.Bits.MS0A
#define TASC0_MS0B                      _TASC0.Bits.MS0B
#define TASC0_CH0IE                     _TASC0.Bits.CH0IE
#define TASC0_CH0F                      _TASC0.Bits.CH0F
#define TASC0_ELS0x                     _TASC0.MergedBits.grpELS0x
#define TASC0_MS0x                      _TASC0.MergedBits.grpMS0x

#define TASC0_CH0MAX_MASK               1
#define TASC0_TOV0_MASK                 2
#define TASC0_ELS0A_MASK                4
#define TASC0_ELS0B_MASK                8
#define TASC0_MS0A_MASK                 16
#define TASC0_MS0B_MASK                 32
#define TASC0_CH0IE_MASK                64
#define TASC0_CH0F_MASK                 128
#define TASC0_ELS0x_MASK                12
#define TASC0_ELS0x_BITNUM              2
#define TASC0_MS0x_MASK                 48
#define TASC0_MS0x_BITNUM               4


/*** TACH0 - TIMA Channel 0 Register; 0x00000026 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TACH0H - TIMA Channel 0 Register High; 0x00000026 ***/
    union {
      byte Byte;
    } TACH0HSTR;
    #define TACH0H                      _TACH0.Overlap_STR.TACH0HSTR.Byte
    

    /*** TACH0L - TIMA Channel 0 Register Low; 0x00000027 ***/
    union {
      byte Byte;
    } TACH0LSTR;
    #define TACH0L                      _TACH0.Overlap_STR.TACH0LSTR.Byte
    
  } Overlap_STR;

} TACH0STR;
extern volatile TACH0STR _TACH0;
#define TACH0                           _TACH0.Word


/*** TASC1 - TIMA Channel 1 Status/Control Register; 0x00000028 ***/
typedef union {
  byte Byte;
  struct {
    byte CH1MAX      :1;                                       /* Channel 1 Maximum Duty Cycle Bit */
    byte TOV1        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS1A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS1B       :1;                                       /* Edge/Level Select Bit B */
    byte MS1A        :1;                                       /* Mode Select Bit A */
    byte             :1; 
    byte CH1IE       :1;                                       /* Channel 1 Interrupt Enable Bit */
    byte CH1F        :1;                                       /* Channel 1 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_1 :1;
    byte grpELS1x :2;
    byte grpMS1x :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TASC1STR;
extern volatile TASC1STR _TASC1;
#define TASC1                           _TASC1.Byte
#define TASC1_CH1MAX                    _TASC1.Bits.CH1MAX
#define TASC1_TOV1                      _TASC1.Bits.TOV1
#define TASC1_ELS1A                     _TASC1.Bits.ELS1A
#define TASC1_ELS1B                     _TASC1.Bits.ELS1B
#define TASC1_MS1A                      _TASC1.Bits.MS1A
#define TASC1_CH1IE                     _TASC1.Bits.CH1IE
#define TASC1_CH1F                      _TASC1.Bits.CH1F
#define TASC1_ELS1x                     _TASC1.MergedBits.grpELS1x

#define TASC1_CH1MAX_MASK               1
#define TASC1_TOV1_MASK                 2
#define TASC1_ELS1A_MASK                4
#define TASC1_ELS1B_MASK                8
#define TASC1_MS1A_MASK                 16
#define TASC1_CH1IE_MASK                64
#define TASC1_CH1F_MASK                 128
#define TASC1_ELS1x_MASK                12
#define TASC1_ELS1x_BITNUM              2


/*** TACH1 - TIMA Channel 1 Register; 0x00000029 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TACH1H - TIMA Channel 1 Register High; 0x00000029 ***/
    union {
      byte Byte;
    } TACH1HSTR;
    #define TACH1H                      _TACH1.Overlap_STR.TACH1HSTR.Byte
    

    /*** TACH1L - TIMA Channel 1 Register Low; 0x0000002A ***/
    union {
      byte Byte;
    } TACH1LSTR;
    #define TACH1L                      _TACH1.Overlap_STR.TACH1LSTR.Byte
    
  } Overlap_STR;

} TACH1STR;
extern volatile TACH1STR _TACH1;
#define TACH1                           _TACH1.Word


/*** TBSC - TIMB Status/Control Register; 0x0000002B ***/
typedef union {
  byte Byte;
  struct {
    byte PS0         :1;                                       /* Prescaler Select Bit 0 */
    byte PS1         :1;                                       /* Prescaler Select Bit 1 */
    byte PS2         :1;                                       /* Prescaler Select Bit 2 */
    byte             :1; 
    byte TRST        :1;                                       /* TIMB Reset Bit */
    byte TSTOP       :1;                                       /* TIMB Stop Bit */
    byte TOIE        :1;                                       /* TIMB Overflow Interrupt Enable Bit */
    byte TOF         :1;                                       /* TIMB Overflow Flag Bit */
  } Bits;
  struct {
    byte grpPS   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TBSCSTR;
extern volatile TBSCSTR _TBSC;
#define TBSC                            _TBSC.Byte
#define TBSC_PS0                        _TBSC.Bits.PS0
#define TBSC_PS1                        _TBSC.Bits.PS1
#define TBSC_PS2                        _TBSC.Bits.PS2
#define TBSC_TRST                       _TBSC.Bits.TRST
#define TBSC_TSTOP                      _TBSC.Bits.TSTOP
#define TBSC_TOIE                       _TBSC.Bits.TOIE
#define TBSC_TOF                        _TBSC.Bits.TOF
#define TBSC_PS                         _TBSC.MergedBits.grpPS

#define TBSC_PS0_MASK                   1
#define TBSC_PS1_MASK                   2
#define TBSC_PS2_MASK                   4
#define TBSC_TRST_MASK                  16
#define TBSC_TSTOP_MASK                 32
#define TBSC_TOIE_MASK                  64
#define TBSC_TOF_MASK                   128
#define TBSC_PS_MASK                    7
#define TBSC_PS_BITNUM                  0


/*** TBCNT - TIMB Counter Register; 0x0000002C ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TBCNTH - TIMB Counter Register High; 0x0000002C ***/
    union {
      byte Byte;
    } TBCNTHSTR;
    #define TBCNTH                      _TBCNT.Overlap_STR.TBCNTHSTR.Byte
    

    /*** TBCNTL - TIMB Counter Register Low; 0x0000002D ***/
    union {
      byte Byte;
    } TBCNTLSTR;
    #define TBCNTL                      _TBCNT.Overlap_STR.TBCNTLSTR.Byte
    
  } Overlap_STR;

} TBCNTSTR;
extern volatile TBCNTSTR _TBCNT;
#define TBCNT                           _TBCNT.Word


/*** TBMOD - TIMB Counter Modulo Register; 0x0000002E ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TBMODH - TIMB Counter Modulo Register High; 0x0000002E ***/
    union {
      byte Byte;
    } TBMODHSTR;
    #define TBMODH                      _TBMOD.Overlap_STR.TBMODHSTR.Byte
    

    /*** TBMODL - TIMB Counter Modulo Register; 0x0000002F ***/
    union {
      byte Byte;
    } TBMODLSTR;
    #define TBMODL                      _TBMOD.Overlap_STR.TBMODLSTR.Byte
    
  } Overlap_STR;

} TBMODSTR;
extern volatile TBMODSTR _TBMOD;
#define TBMOD                           _TBMOD.Word


/*** TBSC0 - TIMB Channel 0 Status/Control Register; 0x00000030 ***/
typedef union {
  byte Byte;
  struct {
    byte CH0MAX      :1;                                       /* Channel 0 Maximum Duty Cycle Bit */
    byte TOV0        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS0A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS0B       :1;                                       /* Edge/Level Select Bit B */
    byte MS0A        :1;                                       /* Mode Select Bit A */
    byte MS0B        :1;                                       /* Mode Select Bit B */
    byte CH0IE       :1;                                       /* Channel 0 Interrupt Enable Bit */
    byte CH0F        :1;                                       /* Channel 0 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV  :1;
    byte grpELS0x :2;
    byte grpMS0x :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} TBSC0STR;
extern volatile TBSC0STR _TBSC0;
#define TBSC0                           _TBSC0.Byte
#define TBSC0_CH0MAX                    _TBSC0.Bits.CH0MAX
#define TBSC0_TOV0                      _TBSC0.Bits.TOV0
#define TBSC0_ELS0A                     _TBSC0.Bits.ELS0A
#define TBSC0_ELS0B                     _TBSC0.Bits.ELS0B
#define TBSC0_MS0A                      _TBSC0.Bits.MS0A
#define TBSC0_MS0B                      _TBSC0.Bits.MS0B
#define TBSC0_CH0IE                     _TBSC0.Bits.CH0IE
#define TBSC0_CH0F                      _TBSC0.Bits.CH0F
#define TBSC0_ELS0x                     _TBSC0.MergedBits.grpELS0x
#define TBSC0_MS0x                      _TBSC0.MergedBits.grpMS0x

#define TBSC0_CH0MAX_MASK               1
#define TBSC0_TOV0_MASK                 2
#define TBSC0_ELS0A_MASK                4
#define TBSC0_ELS0B_MASK                8
#define TBSC0_MS0A_MASK                 16
#define TBSC0_MS0B_MASK                 32
#define TBSC0_CH0IE_MASK                64
#define TBSC0_CH0F_MASK                 128
#define TBSC0_ELS0x_MASK                12
#define TBSC0_ELS0x_BITNUM              2
#define TBSC0_MS0x_MASK                 48
#define TBSC0_MS0x_BITNUM               4


/*** TBCH0 - TIMB Channel 0 Register; 0x00000031 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TBCH0H - TIMB Channel 0 Register High; 0x00000031 ***/
    union {
      byte Byte;
    } TBCH0HSTR;
    #define TBCH0H                      _TBCH0.Overlap_STR.TBCH0HSTR.Byte
    

    /*** TBCH0L - TIMB Channel 0 Register Low; 0x00000032 ***/
    union {
      byte Byte;
    } TBCH0LSTR;
    #define TBCH0L                      _TBCH0.Overlap_STR.TBCH0LSTR.Byte
    
  } Overlap_STR;

} TBCH0STR;
extern volatile TBCH0STR _TBCH0;
#define TBCH0                           _TBCH0.Word


/*** TBSC1 - IMB Channel Status and Control Register; 0x00000033 ***/
typedef union {
  byte Byte;
  struct {
    byte CH1MAX      :1;                                       /* Channel 1 Maximum Duty Cycle Bit */
    byte TOV1        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS1A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS1B       :1;                                       /* Edge/Level Select Bit B */
    byte MS1A        :1;                                       /* Mode Select Bit A */
    byte             :1; 
    byte CH1IE       :1;                                       /* Channel 1 Interrupt Enable Bit */
    byte CH1F        :1;                                       /* Channel 1 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_1 :1;
    byte grpELS1x :2;
    byte grpMS1x :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TBSC1STR;
extern volatile TBSC1STR _TBSC1;
#define TBSC1                           _TBSC1.Byte
#define TBSC1_CH1MAX                    _TBSC1.Bits.CH1MAX
#define TBSC1_TOV1                      _TBSC1.Bits.TOV1
#define TBSC1_ELS1A                     _TBSC1.Bits.ELS1A
#define TBSC1_ELS1B                     _TBSC1.Bits.ELS1B
#define TBSC1_MS1A                      _TBSC1.Bits.MS1A
#define TBSC1_CH1IE                     _TBSC1.Bits.CH1IE
#define TBSC1_CH1F                      _TBSC1.Bits.CH1F
#define TBSC1_ELS1x                     _TBSC1.MergedBits.grpELS1x

#define TBSC1_CH1MAX_MASK               1
#define TBSC1_TOV1_MASK                 2
#define TBSC1_ELS1A_MASK                4
#define TBSC1_ELS1B_MASK                8
#define TBSC1_MS1A_MASK                 16
#define TBSC1_CH1IE_MASK                64
#define TBSC1_CH1F_MASK                 128
#define TBSC1_ELS1x_MASK                12
#define TBSC1_ELS1x_BITNUM              2


/*** TBCH1 - TIMB Channel 1 Register; 0x00000034 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TBCH1H - TIMB Channel 1 Register High; 0x00000034 ***/
    union {
      byte Byte;
    } TBCH1HSTR;
    #define TBCH1H                      _TBCH1.Overlap_STR.TBCH1HSTR.Byte
    

    /*** TBCH1L - TIMB Channel 1 Register Low; 0x00000035 ***/
    union {
      byte Byte;
    } TBCH1LSTR;
    #define TBCH1L                      _TBCH1.Overlap_STR.TBCH1LSTR.Byte
    
  } Overlap_STR;

} TBCH1STR;
extern volatile TBCH1STR _TBCH1;
#define TBCH1                           _TBCH1.Word


/*** ICGCR - ICG Control Register; 0x00000036 ***/
typedef union {
  byte Byte;
  struct {
    byte ECGS        :1;                                       /* External Clock Generator Stable Bit */
    byte ECGON       :1;                                       /* External Clock Generator On Bit */
    byte ICGS        :1;                                       /* Internal Clock Generator Stable Bit */
    byte ICGON       :1;                                       /* Internal Clock Generator On Bit */
    byte CS          :1;                                       /* Clock Select Bit */
    byte CMON        :1;                                       /* Clock Monitor On Bit */
    byte CMF         :1;                                       /* Clock Monitor Interrupt Flag */
    byte CMIE        :1;                                       /* Clock Monitor Interrupt Enable Bit */
  } Bits;
} ICGCRSTR;
extern volatile ICGCRSTR _ICGCR;
#define ICGCR                           _ICGCR.Byte
#define ICGCR_ECGS                      _ICGCR.Bits.ECGS
#define ICGCR_ECGON                     _ICGCR.Bits.ECGON
#define ICGCR_ICGS                      _ICGCR.Bits.ICGS
#define ICGCR_ICGON                     _ICGCR.Bits.ICGON
#define ICGCR_CS                        _ICGCR.Bits.CS
#define ICGCR_CMON                      _ICGCR.Bits.CMON
#define ICGCR_CMF                       _ICGCR.Bits.CMF
#define ICGCR_CMIE                      _ICGCR.Bits.CMIE

#define ICGCR_ECGS_MASK                 1
#define ICGCR_ECGON_MASK                2
#define ICGCR_ICGS_MASK                 4
#define ICGCR_ICGON_MASK                8
#define ICGCR_CS_MASK                   16
#define ICGCR_CMON_MASK                 32
#define ICGCR_CMF_MASK                  64
#define ICGCR_CMIE_MASK                 128


/*** ICGMR - ICG Multiplier Register; 0x00000037 ***/
typedef union {
  byte Byte;
  struct {
    byte N0          :1;                                       /* ICG Multiplier Factor Bit 0 */
    byte N1          :1;                                       /* ICG Multiplier Factor Bit 1 */
    byte N2          :1;                                       /* ICG Multiplier Factor Bit 2 */
    byte N3          :1;                                       /* ICG Multiplier Factor Bit 3 */
    byte N4          :1;                                       /* ICG Multiplier Factor Bit 4 */
    byte N5          :1;                                       /* ICG Multiplier Factor Bit 5 */
    byte N6          :1;                                       /* ICG Multiplier Factor Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpN    :7;
    byte         :1;
  } MergedBits;
} ICGMRSTR;
extern volatile ICGMRSTR _ICGMR;
#define ICGMR                           _ICGMR.Byte
#define ICGMR_N0                        _ICGMR.Bits.N0
#define ICGMR_N1                        _ICGMR.Bits.N1
#define ICGMR_N2                        _ICGMR.Bits.N2
#define ICGMR_N3                        _ICGMR.Bits.N3
#define ICGMR_N4                        _ICGMR.Bits.N4
#define ICGMR_N5                        _ICGMR.Bits.N5
#define ICGMR_N6                        _ICGMR.Bits.N6
#define ICGMR_N                         _ICGMR.MergedBits.grpN

#define ICGMR_N0_MASK                   1
#define ICGMR_N1_MASK                   2
#define ICGMR_N2_MASK                   4
#define ICGMR_N3_MASK                   8
#define ICGMR_N4_MASK                   16
#define ICGMR_N5_MASK                   32
#define ICGMR_N6_MASK                   64
#define ICGMR_N_MASK                    127
#define ICGMR_N_BITNUM                  0


/*** ICGTR - ICG Trim Register; 0x00000038 ***/
typedef union {
  byte Byte;
  struct {
    byte TRIM0       :1;                                       /* ICG Trim Factor Bit 0 */
    byte TRIM1       :1;                                       /* ICG Trim Factor Bit 1 */
    byte TRIM2       :1;                                       /* ICG Trim Factor Bit 2 */
    byte TRIM3       :1;                                       /* ICG Trim Factor Bit 3 */
    byte TRIM4       :1;                                       /* ICG Trim Factor Bit 4 */
    byte TRIM5       :1;                                       /* ICG Trim Factor Bit 5 */
    byte TRIM6       :1;                                       /* ICG Trim Factor Bit 6 */
    byte TRIM7       :1;                                       /* ICG Trim Factor Bit 7 */
  } Bits;
} ICGTRSTR;
extern volatile ICGTRSTR _ICGTR;
#define ICGTR                           _ICGTR.Byte
#define ICGTR_TRIM0                     _ICGTR.Bits.TRIM0
#define ICGTR_TRIM1                     _ICGTR.Bits.TRIM1
#define ICGTR_TRIM2                     _ICGTR.Bits.TRIM2
#define ICGTR_TRIM3                     _ICGTR.Bits.TRIM3
#define ICGTR_TRIM4                     _ICGTR.Bits.TRIM4
#define ICGTR_TRIM5                     _ICGTR.Bits.TRIM5
#define ICGTR_TRIM6                     _ICGTR.Bits.TRIM6
#define ICGTR_TRIM7                     _ICGTR.Bits.TRIM7

#define ICGTR_TRIM0_MASK                1
#define ICGTR_TRIM1_MASK                2
#define ICGTR_TRIM2_MASK                4
#define ICGTR_TRIM3_MASK                8
#define ICGTR_TRIM4_MASK                16
#define ICGTR_TRIM5_MASK                32
#define ICGTR_TRIM6_MASK                64
#define ICGTR_TRIM7_MASK                128


/*** ICGDVR - ICG Divider Control Register; 0x00000039 ***/
typedef union {
  byte Byte;
  struct {
    byte DDIV0       :1;                                       /* ICG DCO Divider Control Bit 0 */
    byte DDIV1       :1;                                       /* ICG DCO Divider Control Bit 1 */
    byte DDIV2       :1;                                       /* ICG DCO Divider Control Bit 2 */
    byte DDIV3       :1;                                       /* ICG DCO Divider Control Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDDIV :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} ICGDVRSTR;
extern volatile ICGDVRSTR _ICGDVR;
#define ICGDVR                          _ICGDVR.Byte
#define ICGDVR_DDIV0                    _ICGDVR.Bits.DDIV0
#define ICGDVR_DDIV1                    _ICGDVR.Bits.DDIV1
#define ICGDVR_DDIV2                    _ICGDVR.Bits.DDIV2
#define ICGDVR_DDIV3                    _ICGDVR.Bits.DDIV3
#define ICGDVR_DDIV                     _ICGDVR.MergedBits.grpDDIV

#define ICGDVR_DDIV0_MASK               1
#define ICGDVR_DDIV1_MASK               2
#define ICGDVR_DDIV2_MASK               4
#define ICGDVR_DDIV3_MASK               8
#define ICGDVR_DDIV_MASK                15
#define ICGDVR_DDIV_BITNUM              0


/*** ICGDSR - ICG DCO State Control Register; 0x0000003A ***/
typedef union {
  byte Byte;
  struct {
    byte DSTG0       :1;                                       /* ICG DCO Stage Control Bit 0 */
    byte DSTG1       :1;                                       /* ICG DCO Stage Control Bit 1 */
    byte DSTG2       :1;                                       /* ICG DCO Stage Control Bit 2 */
    byte DSTG3       :1;                                       /* ICG DCO Stage Control Bit 3 */
    byte DSTG4       :1;                                       /* ICG DCO Stage Control Bit 4 */
    byte DSTG5       :1;                                       /* ICG DCO Stage Control Bit 5 */
    byte DSTG6       :1;                                       /* ICG DCO Stage Control Bit 6 */
    byte DSTG7       :1;                                       /* ICG DCO Stage Control Bit 7 */
  } Bits;
} ICGDSRSTR;
extern volatile ICGDSRSTR _ICGDSR;
#define ICGDSR                          _ICGDSR.Byte
#define ICGDSR_DSTG0                    _ICGDSR.Bits.DSTG0
#define ICGDSR_DSTG1                    _ICGDSR.Bits.DSTG1
#define ICGDSR_DSTG2                    _ICGDSR.Bits.DSTG2
#define ICGDSR_DSTG3                    _ICGDSR.Bits.DSTG3
#define ICGDSR_DSTG4                    _ICGDSR.Bits.DSTG4
#define ICGDSR_DSTG5                    _ICGDSR.Bits.DSTG5
#define ICGDSR_DSTG6                    _ICGDSR.Bits.DSTG6
#define ICGDSR_DSTG7                    _ICGDSR.Bits.DSTG7

#define ICGDSR_DSTG0_MASK               1
#define ICGDSR_DSTG1_MASK               2
#define ICGDSR_DSTG2_MASK               4
#define ICGDSR_DSTG3_MASK               8
#define ICGDSR_DSTG4_MASK               16
#define ICGDSR_DSTG5_MASK               32
#define ICGDSR_DSTG6_MASK               64
#define ICGDSR_DSTG7_MASK               128


/*** ADSCR - ADC Status and Control Register; 0x0000003C ***/
typedef union {
  byte Byte;
  struct {
    byte ADCH0       :1;                                       /* ADC Channel Select Bit 0 */
    byte ADCH1       :1;                                       /* ADC Channel Select Bit 1 */
    byte ADCH2       :1;                                       /* ADC Channel Select Bit 2 */
    byte ADCH3       :1;                                       /* ADC Channel Select Bit 3 */
    byte ADCH4       :1;                                       /* ADC Channel Select Bit 4 */
    byte ADCO        :1;                                       /* ADC Continuous Conversion Bit */
    byte AIEN        :1;                                       /* ADC Interrupt Enable Bit */
    byte COCO        :1;                                       /* Conversions Complete Bit */
  } Bits;
  struct {
    byte grpADCH :5;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} ADSCRSTR;
extern volatile ADSCRSTR _ADSCR;
#define ADSCR                           _ADSCR.Byte
#define ADSCR_ADCH0                     _ADSCR.Bits.ADCH0
#define ADSCR_ADCH1                     _ADSCR.Bits.ADCH1
#define ADSCR_ADCH2                     _ADSCR.Bits.ADCH2
#define ADSCR_ADCH3                     _ADSCR.Bits.ADCH3
#define ADSCR_ADCH4                     _ADSCR.Bits.ADCH4
#define ADSCR_ADCO                      _ADSCR.Bits.ADCO
#define ADSCR_AIEN                      _ADSCR.Bits.AIEN
#define ADSCR_COCO                      _ADSCR.Bits.COCO
#define ADSCR_ADCH                      _ADSCR.MergedBits.grpADCH

#define ADSCR_ADCH0_MASK                1
#define ADSCR_ADCH1_MASK                2
#define ADSCR_ADCH2_MASK                4
#define ADSCR_ADCH3_MASK                8
#define ADSCR_ADCH4_MASK                16
#define ADSCR_ADCO_MASK                 32
#define ADSCR_AIEN_MASK                 64
#define ADSCR_COCO_MASK                 128
#define ADSCR_ADCH_MASK                 31
#define ADSCR_ADCH_BITNUM               0


/*** ADR - ADC Data Register Right Justified; 0x0000003D ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ADRH - ADC Data Register High ~ Right Justified Mode; 0x0000003D ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* ADC Data Bit 8 */
        byte BIT9        :1;                                       /* ADC Data Bit 9 */
        byte BIT10       :1;                                       /* ADC Data Bit 10 */
        byte BIT11       :1;                                       /* ADC Data Bit 11 */
        byte BIT12       :1;                                       /* ADC Data Bit 12 */
        byte BIT13       :1;                                       /* ADC Data Bit 13 */
        byte BIT14       :1;                                       /* ADC Data Bit 14 */
        byte BIT15       :1;                                       /* ADC Data Bit 15 */
      } Bits;
    } ADRHSTR;
    #define ADRH                        _ADR.Overlap_STR.ADRHSTR.Byte
    #define ADRH_BIT8                   _ADR.Overlap_STR.ADRHSTR.Bits.BIT8
    #define ADRH_BIT9                   _ADR.Overlap_STR.ADRHSTR.Bits.BIT9
    #define ADRH_BIT10                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT10
    #define ADRH_BIT11                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT11
    #define ADRH_BIT12                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT12
    #define ADRH_BIT13                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT13
    #define ADRH_BIT14                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT14
    #define ADRH_BIT15                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT15
    
    #define ADRH_BIT8_MASK              1
    #define ADRH_BIT9_MASK              2
    #define ADRH_BIT10_MASK             4
    #define ADRH_BIT11_MASK             8
    #define ADRH_BIT12_MASK             16
    #define ADRH_BIT13_MASK             32
    #define ADRH_BIT14_MASK             64
    #define ADRH_BIT15_MASK             128
    

    /*** ADRL - ADC Data Register Low ~ Right Justified Mode; 0x0000003E ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* ADC Data Bit 0 */
        byte BIT1        :1;                                       /* ADC Data Bit 1 */
        byte BIT2        :1;                                       /* ADC Data Bit 2 */
        byte BIT3        :1;                                       /* ADC Data Bit 3 */
        byte BIT4        :1;                                       /* ADC Data Bit 4 */
        byte BIT5        :1;                                       /* ADC Data Bit 5 */
        byte BIT6        :1;                                       /* ADC Data Bit 6 */
        byte BIT7        :1;                                       /* ADC Data Bit 7 */
      } Bits;
    } ADRLSTR;
    #define ADRL                        _ADR.Overlap_STR.ADRLSTR.Byte
    #define ADRL_BIT0                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT0
    #define ADRL_BIT1                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT1
    #define ADRL_BIT2                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT2
    #define ADRL_BIT3                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT3
    #define ADRL_BIT4                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT4
    #define ADRL_BIT5                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT5
    #define ADRL_BIT6                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT6
    #define ADRL_BIT7                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT7
    
    #define ADRL_BIT0_MASK              1
    #define ADRL_BIT1_MASK              2
    #define ADRL_BIT2_MASK              4
    #define ADRL_BIT3_MASK              8
    #define ADRL_BIT4_MASK              16
    #define ADRL_BIT5_MASK              32
    #define ADRL_BIT6_MASK              64
    #define ADRL_BIT7_MASK              128
    
  } Overlap_STR;

} ADRSTR;
extern volatile ADRSTR _ADR;
#define ADR                             _ADR.Word


/*** ADCLK - ADC Clock Register; 0x0000003F ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte MODE0       :1;                                       /* Mode of Result Justification Bit 0 */
    byte MODE1       :1;                                       /* Mode of Result Justification Bit 1 */
    byte ADICLK      :1;                                       /* ADC Input Clock Select Bit */
    byte ADIV0       :1;                                       /* ADC Clock Prescaler Bit 0 */
    byte ADIV1       :1;                                       /* ADC Clock Prescaler Bit 1 */
    byte ADIV2       :1;                                       /* ADC Clock Prescaler Bit 2 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpMODE :2;
    byte         :1;
    byte grpADIV :3;
  } MergedBits;
} ADCLKSTR;
extern volatile ADCLKSTR _ADCLK;
#define ADCLK                           _ADCLK.Byte
#define ADCLK_MODE0                     _ADCLK.Bits.MODE0
#define ADCLK_MODE1                     _ADCLK.Bits.MODE1
#define ADCLK_ADICLK                    _ADCLK.Bits.ADICLK
#define ADCLK_ADIV0                     _ADCLK.Bits.ADIV0
#define ADCLK_ADIV1                     _ADCLK.Bits.ADIV1
#define ADCLK_ADIV2                     _ADCLK.Bits.ADIV2
#define ADCLK_MODE                      _ADCLK.MergedBits.grpMODE
#define ADCLK_ADIV                      _ADCLK.MergedBits.grpADIV

#define ADCLK_MODE0_MASK                4
#define ADCLK_MODE1_MASK                8
#define ADCLK_ADICLK_MASK               16
#define ADCLK_ADIV0_MASK                32
#define ADCLK_ADIV1_MASK                64
#define ADCLK_ADIV2_MASK                128
#define ADCLK_MODE_MASK                 12
#define ADCLK_MODE_BITNUM               2
#define ADCLK_ADIV_MASK                 224
#define ADCLK_ADIV_BITNUM               5


/*** SBSR - SIM Break Status Register; 0x0000FE00 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte SBSW        :1;                                       /* SIM Break STOP/WAIT */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SBSRSTR;
extern volatile SBSRSTR _SBSR;
#define SBSR                            _SBSR.Byte
#define SBSR_SBSW                       _SBSR.Bits.SBSW

#define SBSR_SBSW_MASK                  2


/*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte LVI         :1;                                       /* Low-Voltage Inhibit Reset bit */
    byte MENRST      :1;                                       /* Forced Monitor Mode Entry Reset Bit */
    byte ILAD        :1;                                       /* Illegal Address Reset Bit */
    byte ILOP        :1;                                       /* Illegal Opcode Reset Bit */
    byte COP         :1;                                       /* Computer Operating Properly Reset Bit */
    byte PIN         :1;                                       /* External Reset Bit */
    byte POR         :1;                                       /* Power-On Reset Bit */
  } Bits;
} SRSRSTR;
extern volatile SRSRSTR _SRSR;
#define SRSR                            _SRSR.Byte
#define SRSR_LVI                        _SRSR.Bits.LVI
#define SRSR_MENRST                     _SRSR.Bits.MENRST
#define SRSR_ILAD                       _SRSR.Bits.ILAD
#define SRSR_ILOP                       _SRSR.Bits.ILOP
#define SRSR_COP                        _SRSR.Bits.COP
#define SRSR_PIN                        _SRSR.Bits.PIN
#define SRSR_POR                        _SRSR.Bits.POR

#define SRSR_LVI_MASK                   2
#define SRSR_MENRST_MASK                4
#define SRSR_ILAD_MASK                  8
#define SRSR_ILOP_MASK                  16
#define SRSR_COP_MASK                   32
#define SRSR_PIN_MASK                   64
#define SRSR_POR_MASK                   128


/*** SBFCR - SIM Break Flag Control Register; 0x0000FE03 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BCFE        :1;                                       /* Break Clear Flag Enable Bit */
  } Bits;
} SBFCRSTR;
extern volatile SBFCRSTR _SBFCR;
#define SBFCR                           _SBFCR.Byte
#define SBFCR_BCFE                      _SBFCR.Bits.BCFE

#define SBFCR_BCFE_MASK                 128


/*** FLCR - FLASH Control Register; 0x0000FE08 ***/
typedef union {
  byte Byte;
  struct {
    byte PGM         :1;                                       /* Program Control Bit */
    byte ERASE       :1;                                       /* Erase Control Bit */
    byte MASS        :1;                                       /* Mass Erase Control Bit */
    byte HVEN        :1;                                       /* High-Voltage Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} FLCRSTR;
extern volatile FLCRSTR _FLCR;
#define FLCR                            _FLCR.Byte
#define FLCR_PGM                        _FLCR.Bits.PGM
#define FLCR_ERASE                      _FLCR.Bits.ERASE
#define FLCR_MASS                       _FLCR.Bits.MASS
#define FLCR_HVEN                       _FLCR.Bits.HVEN

#define FLCR_PGM_MASK                   1
#define FLCR_ERASE_MASK                 2
#define FLCR_MASS_MASK                  4
#define FLCR_HVEN_MASK                  8


/*** BRK - Break Address Register; 0x0000FE09 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** BRKH - Break Address Register High; 0x0000FE09 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Break Address Bit 8 */
        byte BIT9        :1;                                       /* Break Address Bit 9 */
        byte BIT10       :1;                                       /* Break Address Bit 10 */
        byte BIT11       :1;                                       /* Break Address Bit 11 */
        byte BIT12       :1;                                       /* Break Address Bit 12 */
        byte BIT13       :1;                                       /* Break Address Bit 13 */
        byte BIT14       :1;                                       /* Break Address Bit 14 */
        byte BIT15       :1;                                       /* Break Address Bit 15 */
      } Bits;
    } BRKHSTR;
    #define BRKH                        _BRK.Overlap_STR.BRKHSTR.Byte
    #define BRKH_BIT8                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT8
    #define BRKH_BIT9                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT9
    #define BRKH_BIT10                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT10
    #define BRKH_BIT11                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT11
    #define BRKH_BIT12                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT12
    #define BRKH_BIT13                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT13
    #define BRKH_BIT14                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT14
    #define BRKH_BIT15                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT15
    
    #define BRKH_BIT8_MASK              1
    #define BRKH_BIT9_MASK              2
    #define BRKH_BIT10_MASK             4
    #define BRKH_BIT11_MASK             8
    #define BRKH_BIT12_MASK             16
    #define BRKH_BIT13_MASK             32
    #define BRKH_BIT14_MASK             64
    #define BRKH_BIT15_MASK             128
    

    /*** BRKL - Break Address Register; 0x0000FE0A ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Break Address Bit 0 */
        byte BIT1        :1;                                       /* Break Address Bit 1 */
        byte BIT2        :1;                                       /* Break Address Bit 2 */
        byte BIT3        :1;                                       /* Break Address Bit 3 */
        byte BIT4        :1;                                       /* Break Address Bit 4 */
        byte BIT5        :1;                                       /* Break Address Bit 5 */
        byte BIT6        :1;                                       /* Break Address Bit 6 */
        byte BIT7        :1;                                       /* Break Address Bit 7 */
      } Bits;
    } BRKLSTR;
    #define BRKL                        _BRK.Overlap_STR.BRKLSTR.Byte
    #define BRKL_BIT0                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT0
    #define BRKL_BIT1                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT1
    #define BRKL_BIT2                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT2
    #define BRKL_BIT3                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT3
    #define BRKL_BIT4                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT4
    #define BRKL_BIT5                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT5
    #define BRKL_BIT6                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT6
    #define BRKL_BIT7                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT7
    
    #define BRKL_BIT0_MASK              1
    #define BRKL_BIT1_MASK              2
    #define BRKL_BIT2_MASK              4
    #define BRKL_BIT3_MASK              8
    #define BRKL_BIT4_MASK              16
    #define BRKL_BIT5_MASK              32
    #define BRKL_BIT6_MASK              64
    #define BRKL_BIT7_MASK              128
    
  } Overlap_STR;

} BRKSTR;
extern volatile BRKSTR _BRK;
#define BRK                             _BRK.Word


/*** BSCR - Break Status and Control Register; 0x0000FE0B ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BRKA        :1;                                       /* Break Active Bit */
    byte BRKE        :1;                                       /* Break Enable Bit */
  } Bits;
} BSCRSTR;
extern volatile BSCRSTR _BSCR;
#define BSCR                            _BSCR.Byte
#define BSCR_BRKA                       _BSCR.Bits.BRKA
#define BSCR_BRKE                       _BSCR.Bits.BRKE

#define BSCR_BRKA_MASK                  64
#define BSCR_BRKE_MASK                  128


/*** LVISR - LVI Status and Control Register; 0x0000FE0C ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte LVIOUT      :1;                                       /* LVI Output Bit */
  } Bits;
} LVISRSTR;
extern volatile LVISRSTR _LVISR;
#define LVISR                           _LVISR.Byte
#define LVISR_LVIOUT                    _LVISR.Bits.LVIOUT

#define LVISR_LVIOUT_MASK               128


/*** FLBPR - FLASH Block Protect Register; 0x0000FF7E ***/
typedef union {
  byte Byte;
  struct {
    byte BPR0        :1;                                       /* Flash Block Protect Bit 0 */
    byte BPR1        :1;                                       /* Flash Block Protect Bit 1 */
    byte BPR2        :1;                                       /* Flash Block Protect Bit 2 */
    byte BPR3        :1;                                       /* Flash Block Protect Bit 3 */
    byte BPR4        :1;                                       /* Flash Block Protect Bit 4 */
    byte BPR5        :1;                                       /* Flash Block Protect Bit 5 */
    byte BPR6        :1;                                       /* Flash Block Protect Bit 6 */
    byte BPR7        :1;                                       /* Flash Block Protect Bit 7 */
  } Bits;
} FLBPRSTR;
/* Tip for register initialization in the user code:  const byte FLBPR_INIT @0x0000FF7E = <FLBPR_INITVAL>; */
#define _FLBPR (*(const FLBPRSTR * __far)0x0000FF7E)
#define FLBPR                           _FLBPR.Byte
#define FLBPR_BPR0                      _FLBPR.Bits.BPR0
#define FLBPR_BPR1                      _FLBPR.Bits.BPR1
#define FLBPR_BPR2                      _FLBPR.Bits.BPR2
#define FLBPR_BPR3                      _FLBPR.Bits.BPR3
#define FLBPR_BPR4                      _FLBPR.Bits.BPR4
#define FLBPR_BPR5                      _FLBPR.Bits.BPR5
#define FLBPR_BPR6                      _FLBPR.Bits.BPR6
#define FLBPR_BPR7                      _FLBPR.Bits.BPR7

#define FLBPR_BPR0_MASK                 1
#define FLBPR_BPR1_MASK                 2
#define FLBPR_BPR2_MASK                 4
#define FLBPR_BPR3_MASK                 8
#define FLBPR_BPR4_MASK                 16
#define FLBPR_BPR5_MASK                 32
#define FLBPR_BPR6_MASK                 64
#define FLBPR_BPR7_MASK                 128


/*** ICGT - Internal Oscillator Trim Value; 0x0000FF80 ***/
typedef union {
  byte Byte;
  struct {
    byte TRIM0       :1;                                       /* Internal Oscillator Trim Value Bit 0 */
    byte TRIM1       :1;                                       /* Internal Oscillator Trim Value Bit 1 */
    byte TRIM2       :1;                                       /* Internal Oscillator Trim Value Bit 2 */
    byte TRIM3       :1;                                       /* Internal Oscillator Trim Value Bit 3 */
    byte TRIM4       :1;                                       /* Internal Oscillator Trim Value Bit 4 */
    byte TRIM5       :1;                                       /* Internal Oscillator Trim Value Bit 5 */
    byte TRIM6       :1;                                       /* Internal Oscillator Trim Value Bit 6 */
    byte TRIM7       :1;                                       /* Internal Oscillator Trim Value Bit 7 */
  } Bits;
} ICGTSTR;
/* Tip for register initialization in the user code:  const byte ICGT_INIT @0x0000FF80 = <ICGT_INITVAL>; */
#define _ICGT (*(const ICGTSTR * __far)0x0000FF80)
#define ICGT                            _ICGT.Byte
#define ICGT_TRIM0                      _ICGT.Bits.TRIM0
#define ICGT_TRIM1                      _ICGT.Bits.TRIM1
#define ICGT_TRIM2                      _ICGT.Bits.TRIM2
#define ICGT_TRIM3                      _ICGT.Bits.TRIM3
#define ICGT_TRIM4                      _ICGT.Bits.TRIM4
#define ICGT_TRIM5                      _ICGT.Bits.TRIM5
#define ICGT_TRIM6                      _ICGT.Bits.TRIM6
#define ICGT_TRIM7                      _ICGT.Bits.TRIM7

#define ICGT_TRIM0_MASK                 1
#define ICGT_TRIM1_MASK                 2
#define ICGT_TRIM2_MASK                 4
#define ICGT_TRIM3_MASK                 8
#define ICGT_TRIM4_MASK                 16
#define ICGT_TRIM5_MASK                 32
#define ICGT_TRIM6_MASK                 64
#define ICGT_TRIM7_MASK                 128


/*** COPCTL - COP Control Register; 0x0000FFFF ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Bit 0 */
    byte BIT1        :1;                                       /* Bit 1 */
    byte BIT2        :1;                                       /* Bit 2 */
    byte BIT3        :1;                                       /* Bit 3 */
    byte BIT4        :1;                                       /* Bit 4 */
    byte BIT5        :1;                                       /* Bit 5 */
    byte BIT6        :1;                                       /* Bit 6 */
    byte BIT7        :1;                                       /* Bit 7 */
  } Bits;
} COPCTLSTR;
extern volatile COPCTLSTR _COPCTL;
#define COPCTL                          _COPCTL.Byte
#define COPCTL_BIT0                     _COPCTL.Bits.BIT0
#define COPCTL_BIT1                     _COPCTL.Bits.BIT1
#define COPCTL_BIT2                     _COPCTL.Bits.BIT2
#define COPCTL_BIT3                     _COPCTL.Bits.BIT3
#define COPCTL_BIT4                     _COPCTL.Bits.BIT4
#define COPCTL_BIT5                     _COPCTL.Bits.BIT5
#define COPCTL_BIT6                     _COPCTL.Bits.BIT6
#define COPCTL_BIT7                     _COPCTL.Bits.BIT7

#define COPCTL_BIT0_MASK                1
#define COPCTL_BIT1_MASK                2
#define COPCTL_BIT2_MASK                4
#define COPCTL_BIT3_MASK                8
#define COPCTL_BIT4_MASK                16
#define COPCTL_BIT5_MASK                32
#define COPCTL_BIT6_MASK                64
#define COPCTL_BIT7_MASK                128



/***********************************************/
/**   D E P R E C I A T E D   S Y M B O L S   **/
/***********************************************/
/* ---------------------------------------------------------------------------------------------------
Exceptions in bit names of timer status and control registers
due to backward compatibility with previous releases  */
#define TASC0_CHxMAX    _TASC0.Bits.CH0MAX
#define TASC0_TOVx      _TASC0.Bits.TOV0
#define TASC0_ELSxA     _TASC0.Bits.ELS0A
#define TASC0_ELSxB     _TASC0.Bits.ELS0B
#define TASC0_MSxA      _TASC0.Bits.MS0A
#define TASC0_MSxB      _TASC0.Bits.MS0B
#define TASC0_CHxIE     _TASC0.Bits.CH0IE
#define TASC0_CHxF      _TASC0.Bits.CH0F

#define TASC1_CHxMAX    _TASC1.Bits.CH1MAX
#define TASC1_TOVx      _TASC1.Bits.TOV1
#define TASC1_ELSxA     _TASC1.Bits.ELS1A
#define TASC1_ELSxB     _TASC1.Bits.ELS1B
#define TASC1_MSxA      _TASC1.Bits.MS1A
#define TASC1_CHxIE     _TASC1.Bits.CH1IE
#define TASC1_CHxF      _TASC1.Bits.CH1F

#define TBSC0_CHxMAX    _TBSC0.Bits.CH0MAX
#define TBSC0_TOVx      _TBSC0.Bits.TOV0
#define TBSC0_ELSxA     _TBSC0.Bits.ELS0A
#define TBSC0_ELSxB     _TBSC0.Bits.ELS0B
#define TBSC0_MSxA      _TBSC0.Bits.MS0A
#define TBSC0_MSxB      _TBSC0.Bits.MS0B
#define TBSC0_CHxIE     _TBSC0.Bits.CH0IE
#define TBSC0_CHxF      _TBSC0.Bits.CH0F

#define TBSC1_CHxMAX    _TBSC1.Bits.CH1MAX
#define TBSC1_TOVx      _TBSC1.Bits.TOV1
#define TBSC1_ELSxA     _TBSC1.Bits.ELS1A
#define TBSC1_ELSxB     _TBSC1.Bits.ELS1B
#define TBSC1_MSxA      _TBSC1.Bits.MS1A
#define TBSC1_CHxIE     _TBSC1.Bits.CH1IE
#define TBSC1_CHxF      _TBSC1.Bits.CH1F

/* --------------------------------------------------------------------------- */
/* The following symbols were removed, because they were invalid or irrelevant */
/* --------------------------------------------------------------------------- */


/* **** 11.9.2009 12:42:35 */

#define TACH_ARR                         This_symb_has_been_depreciated
#define TBCH_ARR                         This_symb_has_been_depreciated
#endif
