/* Based on CPU DB MC68HC908MR8_32, version 2.89.064 (RegistersPrg V2.30) */
/*
** ###################################################################
**     Filename  : mc68hc908mr8.h
**     Processor : MC68HC908MR8CFU
**     FileFormat: V2.30
**     DataSheet : MC68HC908MR8/D Rev. 4.1 August 16, 2005
**     Compiler  : CodeWarrior compiler
**     Date/Time : 11.9.2009, 14:09
**     Abstract  :
**         This header implements the mapping of I/O devices.
**
**     Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved.
**     
**     http      : www.freescale.com
**     mail      : support@freescale.com
**
**     CPU Registers Revisions:
**               - none
**
**     File-Format-Revisions:
**      - 14.11.2005, V2.00 :
**               - Deprecated symbols added for backward compatibility (section at the end of this file)
**      - 15.11.2005, V2.01 :
**               - Changes have not affected this file (because they are related to another family)
**      - 17.12.2005, V2.02 :
**               - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778
**      - 16.01.2006, V2.03 :
**               - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920.
**               - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const")
**      - 08.03.2006, V2.04 :
**               - Support for bit(s) names duplicated with any register name in .h header files
**      - 24.03.2006, V2.05 :
**               - Changes have not affected this file (because they are related to another family)
**      - 26.04.2006, V2.06 :
**               - Absolute assembly supported (depreciated symbols are not defined)
**      - 27.04.2006, V2.07 :
**               - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA).
**      - 07.06.2006, V2.08 :
**               - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM.
**      - 03.07.2006, V2.09 :
**               - Flash commands constants supported
**      - 27.10.2006, V2.10 :
**               - __RESET_WATCHDOG improved formating and re-definition
**      - 23.11.2006, V2.11 :
**               - Changes have not affected this file (because they are related to another family)
**      - 22.01.2007, V2.12 :
**               - Changes have not affected this file (because they are related to another family)
**      - 01.03.2007, V2.13 :
**               - Flash commands constants values converted to HEX format
**      - 02.03.2007, V2.14 :
**               - Interrupt vector numbers added into .H, see VectorNumber_*
**      - 26.03.2007, V2.15 :
**               - Changes have not affected this file (because they are related to another family)
**      - 10.05.2007, V2.16 :
**               - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ)
**      - 05.06.2007, V2.17 :
**               - Changes have not affected this file (because they are related to another family)
**      - 19.07.2007, V2.18 :
**               - Improved number of blanked lines inside register structures
**      - 06.08.2007, V2.19 :
**               - CPUDB revisions generated ahead of the file-format revisions.
**      - 11.09.2007, V2.20 :
**               - Added comment about initialization of unbonded pins.
**      - 02.01.2008, V2.21 :
**               - Changes have not affected this file (because they are related to another family)
**      - 13.02.2008, V2.22 :
**               - Changes have not affected this file (because they are related to another family)
**      - 20.02.2008, V2.23 :
**               - Changes have not affected this file (because they are related to another family)
**      - 03.07.2008, V2.24 :
**               - Added support for bits with name starting with number (like "1HZ")
**      - 28.11.2008, V2.25 :
**               - StandBy RAM array declaration for ANSI-C added
**      - 1.12.2008, V2.26 :
**               - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map.
**      - 17.3.2009, V2.27 :
**               - Merged bit-group is not generated, if the name matches with another bit name in the register
**      - 6.4.2009, V2.28 :
**               - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB
**      - 3.8.2009, V2.29 :
**               - If there is just one bits group matching register name, single bits are not generated
**      - 10.9.2009, V2.30 :
**               - Fixed generation of registers arrays.
**
**     Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific
**     derivative device. To avoid extra current drain from floating input pins, the user’s reset
**     initialization routine in the application program must either enable on-chip pull-up devices
**     or change the direction of unconnected pins to outputs so the pins do not float.
** ###################################################################
*/

#ifndef _MC68HC908MR8_H
#define _MC68HC908MR8_H

/* Types definition */
typedef unsigned char byte;
typedef unsigned int word;
typedef unsigned long dword;
typedef unsigned long dlong[2];

/* Watchdog reset macro */
#ifndef __RESET_WATCHDOG
#ifdef _lint
  #define __RESET_WATCHDOG()  /* empty */
#else
  #define __RESET_WATCHDOG() {asm sta COPCTL;}
#endif
#endif /* __RESET_WATCHDOG */

#define REG_BASE 0x0000                /* Base address for the I/O register block */


#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */

/**************** interrupt vector numbers ****************/
#define VectorNumber_SCITransmit        22
#define VectorNumber_SCIReceive         21
#define VectorNumber_SCIError           20
#define VectorNumber_Int4               19
#define VectorNumber_Int5               18
#define VectorNumber_ADC                17
#define VectorNumber_TIMBOvr            16
#define VectorNumber_TIMBCH1            15
#define VectorNumber_TIMBCH0            14
#define VectorNumber_TIMAOvr            13
#define VectorNumber_Int11              12
#define VectorNumber_Int12              11
#define VectorNumber_TIMACH1            10
#define VectorNumber_TIMACH0            9
#define VectorNumber_PWMMC              8
#define VectorNumber_FAULT4             7
#define VectorNumber_Int17              6
#define VectorNumber_Int18              5
#define VectorNumber_FAULT1             4
#define VectorNumber_PLL                3
#define VectorNumber_IRQ1               2
#define VectorNumber_SWI                1
#define VectorNumber_RESET              0

/**************** interrupt vector table ****************/
#define INT_SCITransmit                 0x0000FFD2
#define INT_SCIReceive                  0x0000FFD4
#define INT_SCIError                    0x0000FFD6
#define Int4                            0x0000FFD8
#define Int5                            0x0000FFDA
#define INT_ADC                         0x0000FFDC
#define INT_TIMBOvr                     0x0000FFDE
#define INT_TIMBCH1                     0x0000FFE0
#define INT_TIMBCH0                     0x0000FFE2
#define INT_TIMAOvr                     0x0000FFE4
#define Int11                           0x0000FFE6
#define Int12                           0x0000FFE8
#define INT_TIMACH1                     0x0000FFEA
#define INT_TIMACH0                     0x0000FFEC
#define INT_PWMMC                       0x0000FFEE
#define INT_FAULT4                      0x0000FFF0
#define Int17                           0x0000FFF2
#define Int18                           0x0000FFF4
#define INT_FAULT1                      0x0000FFF6
#define INT_PLL                         0x0000FFF8
#define INT_IRQ1                        0x0000FFFA
#define INT_SWI                         0x0000FFFC
#define INT_RESET                       0x0000FFFE

/**************** registers I/O map ****************/

/*** PTA - Port A Data Register; 0x00000000 ***/
typedef union {
  byte Byte;
  struct {
    byte PTA0        :1;                                       /* Port A Data Bit 0 */
    byte PTA1        :1;                                       /* Port A Data Bit 1 */
    byte PTA2        :1;                                       /* Port A Data Bit 2 */
    byte PTA3        :1;                                       /* Port A Data Bit 3 */
    byte PTA4        :1;                                       /* Port A Data Bit 4 */
    byte PTA5        :1;                                       /* Port A Data Bit 5 */
    byte PTA6        :1;                                       /* Port A Data Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpPTA  :7;
    byte         :1;
  } MergedBits;
} PTASTR;
extern volatile PTASTR _PTA;
#define PTA                             _PTA.Byte
#define PTA_PTA0                        _PTA.Bits.PTA0
#define PTA_PTA1                        _PTA.Bits.PTA1
#define PTA_PTA2                        _PTA.Bits.PTA2
#define PTA_PTA3                        _PTA.Bits.PTA3
#define PTA_PTA4                        _PTA.Bits.PTA4
#define PTA_PTA5                        _PTA.Bits.PTA5
#define PTA_PTA6                        _PTA.Bits.PTA6
#define PTA_PTA                         _PTA.MergedBits.grpPTA

#define PTA_PTA0_MASK                   1
#define PTA_PTA1_MASK                   2
#define PTA_PTA2_MASK                   4
#define PTA_PTA3_MASK                   8
#define PTA_PTA4_MASK                   16
#define PTA_PTA5_MASK                   32
#define PTA_PTA6_MASK                   64
#define PTA_PTA_MASK                    127
#define PTA_PTA_BITNUM                  0


/*** PTB - Port B Data Register; 0x00000001 ***/
typedef union {
  byte Byte;
  struct {
    byte PTB0        :1;                                       /* Port B Data Bit 0 */
    byte PTB1        :1;                                       /* Port B Data Bit 1 */
    byte PTB2        :1;                                       /* Port B Data Bit 2 */
    byte PTB3        :1;                                       /* Port B Data Bit 3 */
    byte PTB4        :1;                                       /* Port B Data Bit 4 */
    byte PTB5        :1;                                       /* Port B Data Bit 5 */
    byte PTB6        :1;                                       /* Port B Data Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpPTB  :7;
    byte         :1;
  } MergedBits;
} PTBSTR;
extern volatile PTBSTR _PTB;
#define PTB                             _PTB.Byte
#define PTB_PTB0                        _PTB.Bits.PTB0
#define PTB_PTB1                        _PTB.Bits.PTB1
#define PTB_PTB2                        _PTB.Bits.PTB2
#define PTB_PTB3                        _PTB.Bits.PTB3
#define PTB_PTB4                        _PTB.Bits.PTB4
#define PTB_PTB5                        _PTB.Bits.PTB5
#define PTB_PTB6                        _PTB.Bits.PTB6
#define PTB_PTB                         _PTB.MergedBits.grpPTB

#define PTB_PTB0_MASK                   1
#define PTB_PTB1_MASK                   2
#define PTB_PTB2_MASK                   4
#define PTB_PTB3_MASK                   8
#define PTB_PTB4_MASK                   16
#define PTB_PTB5_MASK                   32
#define PTB_PTB6_MASK                   64
#define PTB_PTB_MASK                    127
#define PTB_PTB_BITNUM                  0


/*** PTC - Port C Data Register; 0x00000002 ***/
typedef union {
  byte Byte;
  struct {
    byte PTC0        :1;                                       /* Port C Data Bit 0 */
    byte PTC1        :1;                                       /* Port C Data Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpPTC  :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} PTCSTR;
extern volatile PTCSTR _PTC;
#define PTC                             _PTC.Byte
#define PTC_PTC0                        _PTC.Bits.PTC0
#define PTC_PTC1                        _PTC.Bits.PTC1
#define PTC_PTC                         _PTC.MergedBits.grpPTC

#define PTC_PTC0_MASK                   1
#define PTC_PTC1_MASK                   2
#define PTC_PTC_MASK                    3
#define PTC_PTC_BITNUM                  0


/*** DDRA - Data Direction Register A; 0x00000004 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRA0       :1;                                       /* Data Direction Register A Bit 0 */
    byte DDRA1       :1;                                       /* Data Direction Register A Bit 1 */
    byte DDRA2       :1;                                       /* Data Direction Register A Bit 2 */
    byte DDRA3       :1;                                       /* Data Direction Register A Bit 3 */
    byte DDRA4       :1;                                       /* Data Direction Register A Bit 4 */
    byte DDRA5       :1;                                       /* Data Direction Register A Bit 5 */
    byte DDRA6       :1;                                       /* Data Direction Register A Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpDDRA :7;
    byte         :1;
  } MergedBits;
} DDRASTR;
extern volatile DDRASTR _DDRA;
#define DDRA                            _DDRA.Byte
#define DDRA_DDRA0                      _DDRA.Bits.DDRA0
#define DDRA_DDRA1                      _DDRA.Bits.DDRA1
#define DDRA_DDRA2                      _DDRA.Bits.DDRA2
#define DDRA_DDRA3                      _DDRA.Bits.DDRA3
#define DDRA_DDRA4                      _DDRA.Bits.DDRA4
#define DDRA_DDRA5                      _DDRA.Bits.DDRA5
#define DDRA_DDRA6                      _DDRA.Bits.DDRA6
#define DDRA_DDRA                       _DDRA.MergedBits.grpDDRA

#define DDRA_DDRA0_MASK                 1
#define DDRA_DDRA1_MASK                 2
#define DDRA_DDRA2_MASK                 4
#define DDRA_DDRA3_MASK                 8
#define DDRA_DDRA4_MASK                 16
#define DDRA_DDRA5_MASK                 32
#define DDRA_DDRA6_MASK                 64
#define DDRA_DDRA_MASK                  127
#define DDRA_DDRA_BITNUM                0


/*** DDRB - Data Direction Register B; 0x00000005 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRB0       :1;                                       /* Data Direction Register B Bit 0 */
    byte DDRB1       :1;                                       /* Data Direction Register B Bit 1 */
    byte DDRB2       :1;                                       /* Data Direction Register B Bit 2 */
    byte DDRB3       :1;                                       /* Data Direction Register B Bit 3 */
    byte DDRB4       :1;                                       /* Data Direction Register B Bit 4 */
    byte DDRB5       :1;                                       /* Data Direction Register B Bit 5 */
    byte DDRB6       :1;                                       /* Data Direction Register B Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpDDRB :7;
    byte         :1;
  } MergedBits;
} DDRBSTR;
extern volatile DDRBSTR _DDRB;
#define DDRB                            _DDRB.Byte
#define DDRB_DDRB0                      _DDRB.Bits.DDRB0
#define DDRB_DDRB1                      _DDRB.Bits.DDRB1
#define DDRB_DDRB2                      _DDRB.Bits.DDRB2
#define DDRB_DDRB3                      _DDRB.Bits.DDRB3
#define DDRB_DDRB4                      _DDRB.Bits.DDRB4
#define DDRB_DDRB5                      _DDRB.Bits.DDRB5
#define DDRB_DDRB6                      _DDRB.Bits.DDRB6
#define DDRB_DDRB                       _DDRB.MergedBits.grpDDRB

#define DDRB_DDRB0_MASK                 1
#define DDRB_DDRB1_MASK                 2
#define DDRB_DDRB2_MASK                 4
#define DDRB_DDRB3_MASK                 8
#define DDRB_DDRB4_MASK                 16
#define DDRB_DDRB5_MASK                 32
#define DDRB_DDRB6_MASK                 64
#define DDRB_DDRB_MASK                  127
#define DDRB_DDRB_BITNUM                0


/*** DDRC - Data Direction Register C; 0x00000006 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRC0       :1;                                       /* Data Direction Register C Bit 0 */
    byte DDRC1       :1;                                       /* Data Direction Register C Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDDRC :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DDRCSTR;
extern volatile DDRCSTR _DDRC;
#define DDRC                            _DDRC.Byte
#define DDRC_DDRC0                      _DDRC.Bits.DDRC0
#define DDRC_DDRC1                      _DDRC.Bits.DDRC1
#define DDRC_DDRC                       _DDRC.MergedBits.grpDDRC

#define DDRC_DDRC0_MASK                 1
#define DDRC_DDRC1_MASK                 2
#define DDRC_DDRC_MASK                  3
#define DDRC_DDRC_BITNUM                0


/*** TASC - TIMA Status/Control Register; 0x0000000E ***/
typedef union {
  byte Byte;
  struct {
    byte PS0         :1;                                       /* Prescaler Select Bit 0 */
    byte PS1         :1;                                       /* Prescaler Select Bit 1 */
    byte PS2         :1;                                       /* Prescaler Select Bit 2 */
    byte             :1; 
    byte TRST        :1;                                       /* TIMA Reset Bit */
    byte TSTOP       :1;                                       /* TIMA Stop Bit */
    byte TOIE        :1;                                       /* TIMA Overflow Interrupt Enable Bit */
    byte TOF         :1;                                       /* TIMA Overflow Flag Bit */
  } Bits;
  struct {
    byte grpPS   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TASCSTR;
extern volatile TASCSTR _TASC;
#define TASC                            _TASC.Byte
#define TASC_PS0                        _TASC.Bits.PS0
#define TASC_PS1                        _TASC.Bits.PS1
#define TASC_PS2                        _TASC.Bits.PS2
#define TASC_TRST                       _TASC.Bits.TRST
#define TASC_TSTOP                      _TASC.Bits.TSTOP
#define TASC_TOIE                       _TASC.Bits.TOIE
#define TASC_TOF                        _TASC.Bits.TOF
#define TASC_PS                         _TASC.MergedBits.grpPS

#define TASC_PS0_MASK                   1
#define TASC_PS1_MASK                   2
#define TASC_PS2_MASK                   4
#define TASC_TRST_MASK                  16
#define TASC_TSTOP_MASK                 32
#define TASC_TOIE_MASK                  64
#define TASC_TOF_MASK                   128
#define TASC_PS_MASK                    7
#define TASC_PS_BITNUM                  0


/*** TACNT - TIMA Counter Register; 0x0000000F ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TACNTH - TIMA Counter Register High; 0x0000000F ***/
    union {
      byte Byte;
    } TACNTHSTR;
    #define TACNTH                      _TACNT.Overlap_STR.TACNTHSTR.Byte
    

    /*** TACNTL - TIMA Counter Register Low; 0x00000010 ***/
    union {
      byte Byte;
    } TACNTLSTR;
    #define TACNTL                      _TACNT.Overlap_STR.TACNTLSTR.Byte
    
  } Overlap_STR;

} TACNTSTR;
extern volatile TACNTSTR _TACNT;
#define TACNT                           _TACNT.Word


/*** TAMOD - TIMA Counter Modulo Register; 0x00000011 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TAMODH - TIMA Counter Modulo Register High; 0x00000011 ***/
    union {
      byte Byte;
    } TAMODHSTR;
    #define TAMODH                      _TAMOD.Overlap_STR.TAMODHSTR.Byte
    

    /*** TAMODL - TIMA Counter Modulo Register Low; 0x00000012 ***/
    union {
      byte Byte;
    } TAMODLSTR;
    #define TAMODL                      _TAMOD.Overlap_STR.TAMODLSTR.Byte
    
  } Overlap_STR;

} TAMODSTR;
extern volatile TAMODSTR _TAMOD;
#define TAMOD                           _TAMOD.Word


/*** TASC0 - TIMA Channel 0 Status/Control Register; 0x00000013 ***/
typedef union {
  byte Byte;
  struct {
    byte CH0MAX      :1;                                       /* Channel 0 Maximum Duty Cycle Bit */
    byte TOV0        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS0A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS0B       :1;                                       /* Edge/Level Select Bit B */
    byte MS0A        :1;                                       /* Mode Select Bit A */
    byte MS0B        :1;                                       /* Mode Select Bit B */
    byte CH0IE       :1;                                       /* Channel 0 Interrupt Enable Bit */
    byte CH0F        :1;                                       /* Channel 0 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV  :1;
    byte grpELS0x :2;
    byte grpMS0x :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} TASC0STR;
extern volatile TASC0STR _TASC0;
#define TASC0                           _TASC0.Byte
#define TASC0_CH0MAX                    _TASC0.Bits.CH0MAX
#define TASC0_TOV0                      _TASC0.Bits.TOV0
#define TASC0_ELS0A                     _TASC0.Bits.ELS0A
#define TASC0_ELS0B                     _TASC0.Bits.ELS0B
#define TASC0_MS0A                      _TASC0.Bits.MS0A
#define TASC0_MS0B                      _TASC0.Bits.MS0B
#define TASC0_CH0IE                     _TASC0.Bits.CH0IE
#define TASC0_CH0F                      _TASC0.Bits.CH0F
#define TASC0_ELS0x                     _TASC0.MergedBits.grpELS0x
#define TASC0_MS0x                      _TASC0.MergedBits.grpMS0x

#define TASC0_CH0MAX_MASK               1
#define TASC0_TOV0_MASK                 2
#define TASC0_ELS0A_MASK                4
#define TASC0_ELS0B_MASK                8
#define TASC0_MS0A_MASK                 16
#define TASC0_MS0B_MASK                 32
#define TASC0_CH0IE_MASK                64
#define TASC0_CH0F_MASK                 128
#define TASC0_ELS0x_MASK                12
#define TASC0_ELS0x_BITNUM              2
#define TASC0_MS0x_MASK                 48
#define TASC0_MS0x_BITNUM               4


/*** TACH0 - TIMA Channel 0 Register; 0x00000014 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TACH0H - TIMA Channel 0 Register High; 0x00000014 ***/
    union {
      byte Byte;
    } TACH0HSTR;
    #define TACH0H                      _TACH0.Overlap_STR.TACH0HSTR.Byte
    

    /*** TACH0L - TIMA Channel 0 Register Low; 0x00000015 ***/
    union {
      byte Byte;
    } TACH0LSTR;
    #define TACH0L                      _TACH0.Overlap_STR.TACH0LSTR.Byte
    
  } Overlap_STR;

} TACH0STR;
extern volatile TACH0STR _TACH0;
#define TACH0                           _TACH0.Word


/*** TASC1 - TIMA Channel 1 Status/Control Register; 0x00000016 ***/
typedef union {
  byte Byte;
  struct {
    byte CH1MAX      :1;                                       /* Channel 1 Maximum Duty Cycle Bit */
    byte TOV1        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS1A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS1B       :1;                                       /* Edge/Level Select Bit B */
    byte MS1A        :1;                                       /* Mode Select Bit A */
    byte             :1; 
    byte CH1IE       :1;                                       /* Channel 1 Interrupt Enable Bit */
    byte CH1F        :1;                                       /* Channel 1 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_1 :1;
    byte grpELS1x :2;
    byte grpMS1x :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TASC1STR;
extern volatile TASC1STR _TASC1;
#define TASC1                           _TASC1.Byte
#define TASC1_CH1MAX                    _TASC1.Bits.CH1MAX
#define TASC1_TOV1                      _TASC1.Bits.TOV1
#define TASC1_ELS1A                     _TASC1.Bits.ELS1A
#define TASC1_ELS1B                     _TASC1.Bits.ELS1B
#define TASC1_MS1A                      _TASC1.Bits.MS1A
#define TASC1_CH1IE                     _TASC1.Bits.CH1IE
#define TASC1_CH1F                      _TASC1.Bits.CH1F
#define TASC1_ELS1x                     _TASC1.MergedBits.grpELS1x

#define TASC1_CH1MAX_MASK               1
#define TASC1_TOV1_MASK                 2
#define TASC1_ELS1A_MASK                4
#define TASC1_ELS1B_MASK                8
#define TASC1_MS1A_MASK                 16
#define TASC1_CH1IE_MASK                64
#define TASC1_CH1F_MASK                 128
#define TASC1_ELS1x_MASK                12
#define TASC1_ELS1x_BITNUM              2


/*** TACH1 - TIMA Channel 1 Register; 0x00000017 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TACH1H - TIMA Channel 1 Register High; 0x00000017 ***/
    union {
      byte Byte;
    } TACH1HSTR;
    #define TACH1H                      _TACH1.Overlap_STR.TACH1HSTR.Byte
    

    /*** TACH1L - TIMA Channel 1 Register Low; 0x00000018 ***/
    union {
      byte Byte;
    } TACH1LSTR;
    #define TACH1L                      _TACH1.Overlap_STR.TACH1LSTR.Byte
    
  } Overlap_STR;

} TACH1STR;
extern volatile TACH1STR _TACH1;
#define TACH1                           _TACH1.Word


/*** CONFIG - Configuration Register; 0x0000001F ***/
typedef union {
  byte Byte;
  struct {
    byte COPD        :1;                                       /* COP Disable Bit */
    byte STOPE       :1;                                       /* Stop Enable Bit */
    byte LVIPWR      :1;                                       /* LVI Power Enable Bit */
    byte LVIRST      :1;                                       /* LVI Reset Enable Bit */
    byte INDEP       :1;                                       /* Independent Mode Enable Bit */
    byte TOPNEG      :1;                                       /* Top-Side PWM Polarity Bit */
    byte BOTNEG      :1;                                       /* Bottom-Side PWM Polarity Bit */
    byte EDGE        :1;                                       /* Edge-Align Enable Bit */
  } Bits;
} CONFIGSTR;
extern volatile CONFIGSTR _CONFIG;
#define CONFIG                          _CONFIG.Byte
#define CONFIG_COPD                     _CONFIG.Bits.COPD
#define CONFIG_STOPE                    _CONFIG.Bits.STOPE
#define CONFIG_LVIPWR                   _CONFIG.Bits.LVIPWR
#define CONFIG_LVIRST                   _CONFIG.Bits.LVIRST
#define CONFIG_INDEP                    _CONFIG.Bits.INDEP
#define CONFIG_TOPNEG                   _CONFIG.Bits.TOPNEG
#define CONFIG_BOTNEG                   _CONFIG.Bits.BOTNEG
#define CONFIG_EDGE                     _CONFIG.Bits.EDGE

#define CONFIG_COPD_MASK                1
#define CONFIG_STOPE_MASK               2
#define CONFIG_LVIPWR_MASK              4
#define CONFIG_LVIRST_MASK              8
#define CONFIG_INDEP_MASK               16
#define CONFIG_TOPNEG_MASK              32
#define CONFIG_BOTNEG_MASK              64
#define CONFIG_EDGE_MASK                128


/*** PCTL1 - PWM Control Register 1; 0x00000020 ***/
typedef union {
  byte Byte;
  struct {
    byte PWMEN       :1;                                       /* PWM Module Enable Bit */
    byte LDOK        :1;                                       /* Load OK Bit */
    byte             :1; 
    byte             :1; 
    byte PWMF        :1;                                       /* PWM Reload Flag */
    byte PWMINT      :1;                                       /* PWM Interrupt Enable Bit */
    byte DISY        :1;                                       /* Software Disable for Bank Y Bit */
    byte DISX        :1;                                       /* Software Disable for Bank X Bit */
  } Bits;
} PCTL1STR;
extern volatile PCTL1STR _PCTL1;
#define PCTL1                           _PCTL1.Byte
#define PCTL1_PWMEN                     _PCTL1.Bits.PWMEN
#define PCTL1_LDOK                      _PCTL1.Bits.LDOK
#define PCTL1_PWMF                      _PCTL1.Bits.PWMF
#define PCTL1_PWMINT                    _PCTL1.Bits.PWMINT
#define PCTL1_DISY                      _PCTL1.Bits.DISY
#define PCTL1_DISX                      _PCTL1.Bits.DISX

#define PCTL1_PWMEN_MASK                1
#define PCTL1_LDOK_MASK                 2
#define PCTL1_PWMF_MASK                 16
#define PCTL1_PWMINT_MASK               32
#define PCTL1_DISY_MASK                 64
#define PCTL1_DISX_MASK                 128


/*** PCTL2 - PWM Control Register 2; 0x00000021 ***/
typedef union {
  byte Byte;
  struct {
    byte PRSC0       :1;                                       /* PWM Prescaler Bit 0 */
    byte PRSC1       :1;                                       /* PWM Prescaler Bit 1 */
    byte SEL56       :1;                                       /* Top/Bottom Correction Bit for PWM Pair 3 (PWMs 5 & 6) */
    byte SEL34       :1;                                       /* Top/Bottom Correction Bit for PWM Pair 2 (PWMs 3 & 4) */
    byte SEL12       :1;                                       /* Top/Bottom Correction Bit for PWM Pair 1 (PWMs 1 & 2) */
    byte             :1; 
    byte LDFQ0       :1;                                       /* PWM Load Frequency Bit 0 */
    byte LDFQ1       :1;                                       /* PWM Load Frequency Bit 1 */
  } Bits;
  struct {
    byte grpPRSC :2;
    byte grpSEL_56 :1;
    byte grpSEL_34 :1;
    byte grpSEL_12 :1;
    byte         :1;
    byte grpLDFQ :2;
  } MergedBits;
} PCTL2STR;
extern volatile PCTL2STR _PCTL2;
#define PCTL2                           _PCTL2.Byte
#define PCTL2_PRSC0                     _PCTL2.Bits.PRSC0
#define PCTL2_PRSC1                     _PCTL2.Bits.PRSC1
#define PCTL2_SEL56                     _PCTL2.Bits.SEL56
#define PCTL2_SEL34                     _PCTL2.Bits.SEL34
#define PCTL2_SEL12                     _PCTL2.Bits.SEL12
#define PCTL2_LDFQ0                     _PCTL2.Bits.LDFQ0
#define PCTL2_LDFQ1                     _PCTL2.Bits.LDFQ1
#define PCTL2_PRSC                      _PCTL2.MergedBits.grpPRSC
#define PCTL2_LDFQ                      _PCTL2.MergedBits.grpLDFQ

#define PCTL2_PRSC0_MASK                1
#define PCTL2_PRSC1_MASK                2
#define PCTL2_SEL56_MASK                4
#define PCTL2_SEL34_MASK                8
#define PCTL2_SEL12_MASK                16
#define PCTL2_LDFQ0_MASK                64
#define PCTL2_LDFQ1_MASK                128
#define PCTL2_PRSC_MASK                 3
#define PCTL2_PRSC_BITNUM               0
#define PCTL2_LDFQ_MASK                 192
#define PCTL2_LDFQ_BITNUM               6


/*** FCR - Fault Control Register; 0x00000022 ***/
typedef union {
  byte Byte;
  struct {
    byte FMODE1      :1;                                       /* Fault Mode Selection for Fault Pin 1 Bit */
    byte FINT1       :1;                                       /* Fault 1 Interrupt Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte FMODE4      :1;                                       /* Fault Mode Selection for Fault Pin 4 Bit */
    byte FINT4       :1;                                       /* Fault 4 Interrupt Enable Bit */
  } Bits;
} FCRSTR;
extern volatile FCRSTR _FCR;
#define FCR                             _FCR.Byte
#define FCR_FMODE1                      _FCR.Bits.FMODE1
#define FCR_FINT1                       _FCR.Bits.FINT1
#define FCR_FMODE4                      _FCR.Bits.FMODE4
#define FCR_FINT4                       _FCR.Bits.FINT4

#define FCR_FMODE1_MASK                 1
#define FCR_FINT1_MASK                  2
#define FCR_FMODE4_MASK                 64
#define FCR_FINT4_MASK                  128


/*** FSR - Fault Status Register; 0x00000023 ***/
typedef union {
  byte Byte;
  struct {
    byte FFLAG1      :1;                                       /* Fault Event Flag 1 */
    byte FPIN1       :1;                                       /* State of Fault Pin 1 Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte FFLAG4      :1;                                       /* Fault Event Flag 4 */
    byte FPIN4       :1;                                       /* State of Fault Pin 4 Bit */
  } Bits;
} FSRSTR;
extern volatile FSRSTR _FSR;
#define FSR                             _FSR.Byte
#define FSR_FFLAG1                      _FSR.Bits.FFLAG1
#define FSR_FPIN1                       _FSR.Bits.FPIN1
#define FSR_FFLAG4                      _FSR.Bits.FFLAG4
#define FSR_FPIN4                       _FSR.Bits.FPIN4

#define FSR_FFLAG1_MASK                 1
#define FSR_FPIN1_MASK                  2
#define FSR_FFLAG4_MASK                 64
#define FSR_FPIN4_MASK                  128


/*** FTACK - Fault Acknowledge Register; 0x00000024 ***/
typedef union {
  byte Byte;
  struct {
    byte FTACK1      :1;                                       /* Fault Acknowledge 1 Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte FTACK4      :1;                                       /* Fault Acknowledge 4 Bit */
    byte             :1; 
  } Bits;
} FTACKSTR;
extern volatile FTACKSTR _FTACK;
#define FTACK                           _FTACK.Byte
#define FTACK_FTACK1                    _FTACK.Bits.FTACK1
#define FTACK_FTACK4                    _FTACK.Bits.FTACK4

#define FTACK_FTACK1_MASK               1
#define FTACK_FTACK4_MASK               64


/*** PWMOUT - PWM Output Control Register; 0x00000025 ***/
typedef union {
  byte Byte;
  struct {
    byte OUT1        :1;                                       /* PWM Pin Output Control Bit 1 */
    byte OUT2        :1;                                       /* PWM Pin Output Control Bit 2 */
    byte OUT3        :1;                                       /* PWM Pin Output Control Bit 3 */
    byte OUT4        :1;                                       /* PWM Pin Output Control Bit 4 */
    byte OUT5        :1;                                       /* PWM Pin Output Control Bit 5 */
    byte OUT6        :1;                                       /* PWM Pin Output Control Bit 6 */
    byte OUTCTL      :1;                                       /* Output Control Enable Bit */
    byte             :1; 
  } Bits;
  struct {
    byte grpOUT_1 :6;
    byte         :1;
    byte         :1;
  } MergedBits;
} PWMOUTSTR;
extern volatile PWMOUTSTR _PWMOUT;
#define PWMOUT                          _PWMOUT.Byte
#define PWMOUT_OUT1                     _PWMOUT.Bits.OUT1
#define PWMOUT_OUT2                     _PWMOUT.Bits.OUT2
#define PWMOUT_OUT3                     _PWMOUT.Bits.OUT3
#define PWMOUT_OUT4                     _PWMOUT.Bits.OUT4
#define PWMOUT_OUT5                     _PWMOUT.Bits.OUT5
#define PWMOUT_OUT6                     _PWMOUT.Bits.OUT6
#define PWMOUT_OUTCTL                   _PWMOUT.Bits.OUTCTL
#define PWMOUT_OUT_1                    _PWMOUT.MergedBits.grpOUT_1
#define PWMOUT_OUT                      PWMOUT_OUT_1

#define PWMOUT_OUT1_MASK                1
#define PWMOUT_OUT2_MASK                2
#define PWMOUT_OUT3_MASK                4
#define PWMOUT_OUT4_MASK                8
#define PWMOUT_OUT5_MASK                16
#define PWMOUT_OUT6_MASK                32
#define PWMOUT_OUTCTL_MASK              64
#define PWMOUT_OUT_1_MASK               63
#define PWMOUT_OUT_1_BITNUM             0


/*** PCNT - PWM Counter Register; 0x00000026 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PCNTH - PWM Counter Register High; 0x00000026 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* PWM Counter Bit 8 */
        byte BIT9        :1;                                       /* PWM Counter Bit 9 */
        byte BIT10       :1;                                       /* PWM Counter Bit 10 */
        byte BIT11       :1;                                       /* PWM Counter Bit 11 */
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
      } Bits;
      struct {
        byte grpBIT_8 :4;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
      } MergedBits;
    } PCNTHSTR;
    #define PCNTH                       _PCNT.Overlap_STR.PCNTHSTR.Byte
    #define PCNTH_BIT8                  _PCNT.Overlap_STR.PCNTHSTR.Bits.BIT8
    #define PCNTH_BIT9                  _PCNT.Overlap_STR.PCNTHSTR.Bits.BIT9
    #define PCNTH_BIT10                 _PCNT.Overlap_STR.PCNTHSTR.Bits.BIT10
    #define PCNTH_BIT11                 _PCNT.Overlap_STR.PCNTHSTR.Bits.BIT11
    #define PCNTH_BIT_8                 _PCNT.Overlap_STR.PCNTHSTR.MergedBits.grpBIT_8
    #define PCNTH_BIT                   PCNTH_BIT_8
    
    #define PCNTH_BIT8_MASK             1
    #define PCNTH_BIT9_MASK             2
    #define PCNTH_BIT10_MASK            4
    #define PCNTH_BIT11_MASK            8
    #define PCNTH_BIT_8_MASK            15
    #define PCNTH_BIT_8_BITNUM          0
    

    /*** PCNTL - PWM Counter Register Low; 0x00000027 ***/
    union {
      byte Byte;
    } PCNTLSTR;
    #define PCNTL                       _PCNT.Overlap_STR.PCNTLSTR.Byte
    
  } Overlap_STR;

} PCNTSTR;
extern volatile PCNTSTR _PCNT;
#define PCNT                            _PCNT.Word


/*** PMOD - PWM Counter Modulo Register; 0x00000028 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PMODH - PWM Counter Modulo Register High; 0x00000028 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* PWM Counter Modulo Bit 8 */
        byte BIT9        :1;                                       /* PWM Counter Modulo Bit 9 */
        byte BIT10       :1;                                       /* PWM Counter Modulo Bit 10 */
        byte BIT11       :1;                                       /* PWM Counter Modulo Bit 11 */
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
      } Bits;
      struct {
        byte grpBIT_8 :4;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
      } MergedBits;
    } PMODHSTR;
    #define PMODH                       _PMOD.Overlap_STR.PMODHSTR.Byte
    #define PMODH_BIT8                  _PMOD.Overlap_STR.PMODHSTR.Bits.BIT8
    #define PMODH_BIT9                  _PMOD.Overlap_STR.PMODHSTR.Bits.BIT9
    #define PMODH_BIT10                 _PMOD.Overlap_STR.PMODHSTR.Bits.BIT10
    #define PMODH_BIT11                 _PMOD.Overlap_STR.PMODHSTR.Bits.BIT11
    #define PMODH_BIT_8                 _PMOD.Overlap_STR.PMODHSTR.MergedBits.grpBIT_8
    #define PMODH_BIT                   PMODH_BIT_8
    
    #define PMODH_BIT8_MASK             1
    #define PMODH_BIT9_MASK             2
    #define PMODH_BIT10_MASK            4
    #define PMODH_BIT11_MASK            8
    #define PMODH_BIT_8_MASK            15
    #define PMODH_BIT_8_BITNUM          0
    

    /*** PMODL - PWM Counter Modulo Register Low; 0x00000029 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* PWM Counter Modulo Bit 0 */
        byte BIT1        :1;                                       /* PWM Counter Modulo Bit 1 */
        byte BIT2        :1;                                       /* PWM Counter Modulo Bit 2 */
        byte BIT3        :1;                                       /* PWM Counter Modulo Bit 3 */
        byte BIT4        :1;                                       /* PWM Counter Modulo Bit 4 */
        byte BIT5        :1;                                       /* PWM Counter Modulo Bit 5 */
        byte BIT6        :1;                                       /* PWM Counter Modulo Bit 6 */
        byte BIT7        :1;                                       /* PWM Counter Modulo Bit 7 */
      } Bits;
    } PMODLSTR;
    #define PMODL                       _PMOD.Overlap_STR.PMODLSTR.Byte
    #define PMODL_BIT0                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT0
    #define PMODL_BIT1                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT1
    #define PMODL_BIT2                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT2
    #define PMODL_BIT3                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT3
    #define PMODL_BIT4                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT4
    #define PMODL_BIT5                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT5
    #define PMODL_BIT6                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT6
    #define PMODL_BIT7                  _PMOD.Overlap_STR.PMODLSTR.Bits.BIT7
    
    #define PMODL_BIT0_MASK             1
    #define PMODL_BIT1_MASK             2
    #define PMODL_BIT2_MASK             4
    #define PMODL_BIT3_MASK             8
    #define PMODL_BIT4_MASK             16
    #define PMODL_BIT5_MASK             32
    #define PMODL_BIT6_MASK             64
    #define PMODL_BIT7_MASK             128
    
  } Overlap_STR;

} PMODSTR;
extern volatile PMODSTR _PMOD;
#define PMOD                            _PMOD.Word


/*** PVAL1 - PWM1 Value Register; 0x0000002A ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PVAL1H - PWM1 Value Register High; 0x0000002A ***/
    union {
      byte Byte;
    } PVAL1HSTR;
    #define PVAL1H                      _PVAL1.Overlap_STR.PVAL1HSTR.Byte
    

    /*** PVAL1L - PWM1 Value Register Low; 0x0000002B ***/
    union {
      byte Byte;
    } PVAL1LSTR;
    #define PVAL1L                      _PVAL1.Overlap_STR.PVAL1LSTR.Byte
    
  } Overlap_STR;

} PVAL1STR;
extern volatile PVAL1STR _PVAL1;
#define PVAL1                           _PVAL1.Word


/*** PVAL2 - PWM2 Value Register; 0x0000002C ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PVAL2H - PWM2 Value Register High; 0x0000002C ***/
    union {
      byte Byte;
    } PVAL2HSTR;
    #define PVAL2H                      _PVAL2.Overlap_STR.PVAL2HSTR.Byte
    

    /*** PVAL2L - PWM2 Value Register Low; 0x0000002D ***/
    union {
      byte Byte;
    } PVAL2LSTR;
    #define PVAL2L                      _PVAL2.Overlap_STR.PVAL2LSTR.Byte
    
  } Overlap_STR;

} PVAL2STR;
extern volatile PVAL2STR _PVAL2;
#define PVAL2                           _PVAL2.Word


/*** PVAL3 - PWM3 Value Register; 0x0000002E ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PVAL3H - PWM3 Value Register High; 0x0000002E ***/
    union {
      byte Byte;
    } PVAL3HSTR;
    #define PVAL3H                      _PVAL3.Overlap_STR.PVAL3HSTR.Byte
    

    /*** PVAL3L - PWM3 Value Register Low; 0x0000002F ***/
    union {
      byte Byte;
    } PVAL3LSTR;
    #define PVAL3L                      _PVAL3.Overlap_STR.PVAL3LSTR.Byte
    
  } Overlap_STR;

} PVAL3STR;
extern volatile PVAL3STR _PVAL3;
#define PVAL3                           _PVAL3.Word


/*** PVAL4 - PWM4 Value Register; 0x00000030 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PVAL4H - PWM4 Value Register High; 0x00000030 ***/
    union {
      byte Byte;
    } PVAL4HSTR;
    #define PVAL4H                      _PVAL4.Overlap_STR.PVAL4HSTR.Byte
    

    /*** PVAL4L - PWM4 Value Register Low; 0x00000031 ***/
    union {
      byte Byte;
    } PVAL4LSTR;
    #define PVAL4L                      _PVAL4.Overlap_STR.PVAL4LSTR.Byte
    
  } Overlap_STR;

} PVAL4STR;
extern volatile PVAL4STR _PVAL4;
#define PVAL4                           _PVAL4.Word


/*** PVAL5 - PWM5 Value Register; 0x00000032 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PVAL5H - PWM5 Value Register High; 0x00000032 ***/
    union {
      byte Byte;
    } PVAL5HSTR;
    #define PVAL5H                      _PVAL5.Overlap_STR.PVAL5HSTR.Byte
    

    /*** PVAL5L - PWM5 Value Register Low; 0x00000033 ***/
    union {
      byte Byte;
    } PVAL5LSTR;
    #define PVAL5L                      _PVAL5.Overlap_STR.PVAL5LSTR.Byte
    
  } Overlap_STR;

} PVAL5STR;
extern volatile PVAL5STR _PVAL5;
#define PVAL5                           _PVAL5.Word


/*** PVAL6 - PWM6 Value Register; 0x00000034 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PVAL6H - PWM6 Value Register High; 0x00000034 ***/
    union {
      byte Byte;
    } PVAL6HSTR;
    #define PVAL6H                      _PVAL6.Overlap_STR.PVAL6HSTR.Byte
    

    /*** PVAL6L - PWM6 Value Register Low; 0x00000035 ***/
    union {
      byte Byte;
    } PVAL6LSTR;
    #define PVAL6L                      _PVAL6.Overlap_STR.PVAL6LSTR.Byte
    
  } Overlap_STR;

} PVAL6STR;
extern volatile PVAL6STR _PVAL6;
#define PVAL6                           _PVAL6.Word


/*** DEADTM - Dead-Time Write-Once Register; 0x00000036 ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Dead-Time Value Bit 0 */
    byte BIT1        :1;                                       /* Dead-Time Value Bit 1 */
    byte BIT2        :1;                                       /* Dead-Time Value Bit 2 */
    byte BIT3        :1;                                       /* Dead-Time Value Bit 3 */
    byte BIT4        :1;                                       /* Dead-Time Value Bit 4 */
    byte BIT5        :1;                                       /* Dead-Time Value Bit 5 */
    byte BIT6        :1;                                       /* Dead-Time Value Bit 6 */
    byte BIT7        :1;                                       /* Dead-Time Value Bit 7 */
  } Bits;
} DEADTMSTR;
extern volatile DEADTMSTR _DEADTM;
#define DEADTM                          _DEADTM.Byte
#define DEADTM_BIT0                     _DEADTM.Bits.BIT0
#define DEADTM_BIT1                     _DEADTM.Bits.BIT1
#define DEADTM_BIT2                     _DEADTM.Bits.BIT2
#define DEADTM_BIT3                     _DEADTM.Bits.BIT3
#define DEADTM_BIT4                     _DEADTM.Bits.BIT4
#define DEADTM_BIT5                     _DEADTM.Bits.BIT5
#define DEADTM_BIT6                     _DEADTM.Bits.BIT6
#define DEADTM_BIT7                     _DEADTM.Bits.BIT7

#define DEADTM_BIT0_MASK                1
#define DEADTM_BIT1_MASK                2
#define DEADTM_BIT2_MASK                4
#define DEADTM_BIT3_MASK                8
#define DEADTM_BIT4_MASK                16
#define DEADTM_BIT5_MASK                32
#define DEADTM_BIT6_MASK                64
#define DEADTM_BIT7_MASK                128


/*** DISMAP - PWM Disable Mapping Write-Once Register; 0x00000037 ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* PWM Disable Mapping Bit 0 */
    byte BIT1        :1;                                       /* PWM Disable Mapping Bit 1 */
    byte BIT2        :1;                                       /* PWM Disable Mapping Bit 2 */
    byte BIT3        :1;                                       /* PWM Disable Mapping Bit 3 */
    byte BIT4        :1;                                       /* PWM Disable Mapping Bit 4 */
    byte BIT5        :1;                                       /* PWM Disable Mapping Bit 5 */
    byte BIT6        :1;                                       /* PWM Disable Mapping Bit 6 */
    byte BIT7        :1;                                       /* PWM Disable Mapping Bit 7 */
  } Bits;
} DISMAPSTR;
extern volatile DISMAPSTR _DISMAP;
#define DISMAP                          _DISMAP.Byte
#define DISMAP_BIT0                     _DISMAP.Bits.BIT0
#define DISMAP_BIT1                     _DISMAP.Bits.BIT1
#define DISMAP_BIT2                     _DISMAP.Bits.BIT2
#define DISMAP_BIT3                     _DISMAP.Bits.BIT3
#define DISMAP_BIT4                     _DISMAP.Bits.BIT4
#define DISMAP_BIT5                     _DISMAP.Bits.BIT5
#define DISMAP_BIT6                     _DISMAP.Bits.BIT6
#define DISMAP_BIT7                     _DISMAP.Bits.BIT7

#define DISMAP_BIT0_MASK                1
#define DISMAP_BIT1_MASK                2
#define DISMAP_BIT2_MASK                4
#define DISMAP_BIT3_MASK                8
#define DISMAP_BIT4_MASK                16
#define DISMAP_BIT5_MASK                32
#define DISMAP_BIT6_MASK                64
#define DISMAP_BIT7_MASK                128


/*** SCC1 - SCI Control Register 1; 0x00000038 ***/
typedef union {
  byte Byte;
  struct {
    byte PTY         :1;                                       /* Parity Bit */
    byte PEN         :1;                                       /* Parity Enable Bit */
    byte ILTY        :1;                                       /* Idle Line Type Bit */
    byte WAKE        :1;                                       /* Wakeup Condition Bit */
    byte M           :1;                                       /* Mode (Character Length) Bit */
    byte TXINV       :1;                                       /* Transmit Inversion Bit */
    byte ENSCI       :1;                                       /* Enable SCI Bit */
    byte LOOPS       :1;                                       /* Loop Mode Select Bit */
  } Bits;
} SCC1STR;
extern volatile SCC1STR _SCC1;
#define SCC1                            _SCC1.Byte
#define SCC1_PTY                        _SCC1.Bits.PTY
#define SCC1_PEN                        _SCC1.Bits.PEN
#define SCC1_ILTY                       _SCC1.Bits.ILTY
#define SCC1_WAKE                       _SCC1.Bits.WAKE
#define SCC1_M                          _SCC1.Bits.M
#define SCC1_TXINV                      _SCC1.Bits.TXINV
#define SCC1_ENSCI                      _SCC1.Bits.ENSCI
#define SCC1_LOOPS                      _SCC1.Bits.LOOPS

#define SCC1_PTY_MASK                   1
#define SCC1_PEN_MASK                   2
#define SCC1_ILTY_MASK                  4
#define SCC1_WAKE_MASK                  8
#define SCC1_M_MASK                     16
#define SCC1_TXINV_MASK                 32
#define SCC1_ENSCI_MASK                 64
#define SCC1_LOOPS_MASK                 128


/*** SCC2 - SCI Control Register 2; 0x00000039 ***/
typedef union {
  byte Byte;
  struct {
    byte SBK         :1;                                       /* Send Break Bit */
    byte RWU         :1;                                       /* Receiver Wakeup Bit */
    byte RE          :1;                                       /* Receiver Enable Bit */
    byte TE          :1;                                       /* Transmitter Enable Bit */
    byte ILIE        :1;                                       /* Idle Line Interrupt Enable Bit */
    byte SCRIE       :1;                                       /* SCI Receive Interrupt Enable Bit */
    byte TCIE        :1;                                       /* Transmission Complete Interrupt Enable Bit */
    byte SCTIE       :1;                                       /* SCI Transmit Interrupt Enable Bit */
  } Bits;
} SCC2STR;
extern volatile SCC2STR _SCC2;
#define SCC2                            _SCC2.Byte
#define SCC2_SBK                        _SCC2.Bits.SBK
#define SCC2_RWU                        _SCC2.Bits.RWU
#define SCC2_RE                         _SCC2.Bits.RE
#define SCC2_TE                         _SCC2.Bits.TE
#define SCC2_ILIE                       _SCC2.Bits.ILIE
#define SCC2_SCRIE                      _SCC2.Bits.SCRIE
#define SCC2_TCIE                       _SCC2.Bits.TCIE
#define SCC2_SCTIE                      _SCC2.Bits.SCTIE

#define SCC2_SBK_MASK                   1
#define SCC2_RWU_MASK                   2
#define SCC2_RE_MASK                    4
#define SCC2_TE_MASK                    8
#define SCC2_ILIE_MASK                  16
#define SCC2_SCRIE_MASK                 32
#define SCC2_TCIE_MASK                  64
#define SCC2_SCTIE_MASK                 128


/*** SCC3 - SCI Control Register 3; 0x0000003A ***/
typedef union {
  byte Byte;
  struct {
    byte PEIE        :1;                                       /* Receiver Parity Error Interrupt Enable Bit */
    byte FEIE        :1;                                       /* Receiver Framing Error Interrupt Enable Bit */
    byte NEIE        :1;                                       /* Receiver Noise Error Interrupt Enable Bit */
    byte ORIE        :1;                                       /* Receiver Overrun Interrupt Enable Bit */
    byte             :1; 
    byte             :1; 
    byte T8          :1;                                       /* Transmitted Bit 8 */
    byte R8          :1;                                       /* Received Bit 8 */
  } Bits;
} SCC3STR;
extern volatile SCC3STR _SCC3;
#define SCC3                            _SCC3.Byte
#define SCC3_PEIE                       _SCC3.Bits.PEIE
#define SCC3_FEIE                       _SCC3.Bits.FEIE
#define SCC3_NEIE                       _SCC3.Bits.NEIE
#define SCC3_ORIE                       _SCC3.Bits.ORIE
#define SCC3_T8                         _SCC3.Bits.T8
#define SCC3_R8                         _SCC3.Bits.R8

#define SCC3_PEIE_MASK                  1
#define SCC3_FEIE_MASK                  2
#define SCC3_NEIE_MASK                  4
#define SCC3_ORIE_MASK                  8
#define SCC3_T8_MASK                    64
#define SCC3_R8_MASK                    128


/*** SCS1 - SCI Status Register 1; 0x0000003B ***/
typedef union {
  byte Byte;
  struct {
    byte PE          :1;                                       /* Receiver Parity Error Bit */
    byte FE          :1;                                       /* Receiver Framing Error Bit */
    byte NF          :1;                                       /* Receiver Noise Flag Bit */
    byte OR          :1;                                       /* Receiver Overrun Bit */
    byte IDLE        :1;                                       /* Receiver Idle Bit */
    byte SCRF        :1;                                       /* SCI Receiver Full Bit */
    byte TC          :1;                                       /* Transmission Complete Bit */
    byte SCTE        :1;                                       /* SCI Transmitter Empty Bit */
  } Bits;
} SCS1STR;
extern volatile SCS1STR _SCS1;
#define SCS1                            _SCS1.Byte
#define SCS1_PE                         _SCS1.Bits.PE
#define SCS1_FE                         _SCS1.Bits.FE
#define SCS1_NF                         _SCS1.Bits.NF
#define SCS1_OR                         _SCS1.Bits.OR
#define SCS1_IDLE                       _SCS1.Bits.IDLE
#define SCS1_SCRF                       _SCS1.Bits.SCRF
#define SCS1_TC                         _SCS1.Bits.TC
#define SCS1_SCTE                       _SCS1.Bits.SCTE

#define SCS1_PE_MASK                    1
#define SCS1_FE_MASK                    2
#define SCS1_NF_MASK                    4
#define SCS1_OR_MASK                    8
#define SCS1_IDLE_MASK                  16
#define SCS1_SCRF_MASK                  32
#define SCS1_TC_MASK                    64
#define SCS1_SCTE_MASK                  128


/*** SCS2 - SCI Status Register 2; 0x0000003C ***/
typedef union {
  byte Byte;
  struct {
    byte RPF         :1;                                       /* Reception in Progress Flag Bit */
    byte BKF         :1;                                       /* Break Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SCS2STR;
extern volatile SCS2STR _SCS2;
#define SCS2                            _SCS2.Byte
#define SCS2_RPF                        _SCS2.Bits.RPF
#define SCS2_BKF                        _SCS2.Bits.BKF

#define SCS2_RPF_MASK                   1
#define SCS2_BKF_MASK                   2


/*** SCDR - SCI Data Register; 0x0000003D ***/
typedef union {
  byte Byte;
  struct {
    byte R0_T0       :1;                                       /* Receive/Transmit Data Bit 0 */
    byte R1_T1       :1;                                       /* Receive/Transmit Data Bit 1 */
    byte R2_T2       :1;                                       /* Receive/Transmit Data Bit 2 */
    byte R3_T3       :1;                                       /* Receive/Transmit Data Bit 3 */
    byte R4_T4       :1;                                       /* Receive/Transmit Data Bit 4 */
    byte R5_T5       :1;                                       /* Receive/Transmit Data Bit 5 */
    byte R6_T6       :1;                                       /* Receive/Transmit Data Bit 6 */
    byte R7_T7       :1;                                       /* Receive/Transmit Data Bit 7 */
  } Bits;
} SCDRSTR;
extern volatile SCDRSTR _SCDR;
#define SCDR                            _SCDR.Byte
#define SCDR_R0_T0                      _SCDR.Bits.R0_T0
#define SCDR_R1_T1                      _SCDR.Bits.R1_T1
#define SCDR_R2_T2                      _SCDR.Bits.R2_T2
#define SCDR_R3_T3                      _SCDR.Bits.R3_T3
#define SCDR_R4_T4                      _SCDR.Bits.R4_T4
#define SCDR_R5_T5                      _SCDR.Bits.R5_T5
#define SCDR_R6_T6                      _SCDR.Bits.R6_T6
#define SCDR_R7_T7                      _SCDR.Bits.R7_T7

#define SCDR_R0_T0_MASK                 1
#define SCDR_R1_T1_MASK                 2
#define SCDR_R2_T2_MASK                 4
#define SCDR_R3_T3_MASK                 8
#define SCDR_R4_T4_MASK                 16
#define SCDR_R5_T5_MASK                 32
#define SCDR_R6_T6_MASK                 64
#define SCDR_R7_T7_MASK                 128


/*** SCBR - SCI Baud Rate Register; 0x0000003E ***/
typedef union {
  byte Byte;
  struct {
    byte SCR0        :1;                                       /* SCI Baud Rate Select Bit 0 */
    byte SCR1        :1;                                       /* SCI Baud Rate Select Bit 1 */
    byte SCR2        :1;                                       /* SCI Baud Rate Select Bit 2 */
    byte             :1; 
    byte SCP0        :1;                                       /* SCI Baud Rate Prescaler Bit 0 */
    byte SCP1        :1;                                       /* SCI Baud Rate Prescaler Bit 1 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpSCR  :3;
    byte         :1;
    byte grpSCP  :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} SCBRSTR;
extern volatile SCBRSTR _SCBR;
#define SCBR                            _SCBR.Byte
#define SCBR_SCR0                       _SCBR.Bits.SCR0
#define SCBR_SCR1                       _SCBR.Bits.SCR1
#define SCBR_SCR2                       _SCBR.Bits.SCR2
#define SCBR_SCP0                       _SCBR.Bits.SCP0
#define SCBR_SCP1                       _SCBR.Bits.SCP1
#define SCBR_SCR                        _SCBR.MergedBits.grpSCR
#define SCBR_SCP                        _SCBR.MergedBits.grpSCP

#define SCBR_SCR0_MASK                  1
#define SCBR_SCR1_MASK                  2
#define SCBR_SCR2_MASK                  4
#define SCBR_SCP0_MASK                  16
#define SCBR_SCP1_MASK                  32
#define SCBR_SCR_MASK                   7
#define SCBR_SCR_BITNUM                 0
#define SCBR_SCP_MASK                   48
#define SCBR_SCP_BITNUM                 4


/*** ISCR - IRQ Status and Control Register; 0x0000003F ***/
typedef union {
  byte Byte;
  struct {
    byte MODE1       :1;                                       /* IRQ Edge/Level Select Bit */
    byte IMASK1      :1;                                       /* IRQ Interrupt Mask Bit */
    byte ACK1        :1;                                       /* IRQ Interrupt Request Acknowledge Bit */
    byte IRQF        :1;                                       /* IRQ Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} ISCRSTR;
extern volatile ISCRSTR _ISCR;
#define ISCR                            _ISCR.Byte
#define ISCR_MODE1                      _ISCR.Bits.MODE1
#define ISCR_IMASK1                     _ISCR.Bits.IMASK1
#define ISCR_ACK1                       _ISCR.Bits.ACK1
#define ISCR_IRQF                       _ISCR.Bits.IRQF

#define ISCR_MODE1_MASK                 1
#define ISCR_IMASK1_MASK                2
#define ISCR_ACK1_MASK                  4
#define ISCR_IRQF_MASK                  8


/*** ADSCR - ADC Status and Control Register; 0x00000040 ***/
typedef union {
  byte Byte;
  struct {
    byte ADCH0       :1;                                       /* ADC Channel Select Bit 0 */
    byte ADCH1       :1;                                       /* ADC Channel Select Bit 1 */
    byte ADCH2       :1;                                       /* ADC Channel Select Bit 2 */
    byte ADCH3       :1;                                       /* ADC Channel Select Bit 3 */
    byte ADCH4       :1;                                       /* ADC Channel Select Bit 4 */
    byte ADCO        :1;                                       /* ADC Continuous Conversion Bit */
    byte AIEN        :1;                                       /* ADC Interrupt Enable Bit */
    byte COCO        :1;                                       /* Conversions Complete Bit */
  } Bits;
  struct {
    byte grpADCH :5;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} ADSCRSTR;
extern volatile ADSCRSTR _ADSCR;
#define ADSCR                           _ADSCR.Byte
#define ADSCR_ADCH0                     _ADSCR.Bits.ADCH0
#define ADSCR_ADCH1                     _ADSCR.Bits.ADCH1
#define ADSCR_ADCH2                     _ADSCR.Bits.ADCH2
#define ADSCR_ADCH3                     _ADSCR.Bits.ADCH3
#define ADSCR_ADCH4                     _ADSCR.Bits.ADCH4
#define ADSCR_ADCO                      _ADSCR.Bits.ADCO
#define ADSCR_AIEN                      _ADSCR.Bits.AIEN
#define ADSCR_COCO                      _ADSCR.Bits.COCO
#define ADSCR_ADCH                      _ADSCR.MergedBits.grpADCH

#define ADSCR_ADCH0_MASK                1
#define ADSCR_ADCH1_MASK                2
#define ADSCR_ADCH2_MASK                4
#define ADSCR_ADCH3_MASK                8
#define ADSCR_ADCH4_MASK                16
#define ADSCR_ADCO_MASK                 32
#define ADSCR_AIEN_MASK                 64
#define ADSCR_COCO_MASK                 128
#define ADSCR_ADCH_MASK                 31
#define ADSCR_ADCH_BITNUM               0


/*** ADR - ADC Data Register; 0x00000041 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ADRH - ADC Data Register High; 0x00000041 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* ADC Data Bit 8 */
        byte BIT9        :1;                                       /* ADC Data Bit 9 */
        byte BIT10       :1;                                       /* ADC Data Bit 10 */
        byte BIT11       :1;                                       /* ADC Data Bit 11 */
        byte BIT12       :1;                                       /* ADC Data Bit 12 */
        byte BIT13       :1;                                       /* ADC Data Bit 13 */
        byte BIT14       :1;                                       /* ADC Data Bit 14 */
        byte BIT15       :1;                                       /* ADC Data Bit 15 */
      } Bits;
    } ADRHSTR;
    #define ADRH                        _ADR.Overlap_STR.ADRHSTR.Byte
    #define ADRH_BIT8                   _ADR.Overlap_STR.ADRHSTR.Bits.BIT8
    #define ADRH_BIT9                   _ADR.Overlap_STR.ADRHSTR.Bits.BIT9
    #define ADRH_BIT10                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT10
    #define ADRH_BIT11                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT11
    #define ADRH_BIT12                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT12
    #define ADRH_BIT13                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT13
    #define ADRH_BIT14                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT14
    #define ADRH_BIT15                  _ADR.Overlap_STR.ADRHSTR.Bits.BIT15
    
    #define ADRH_BIT8_MASK              1
    #define ADRH_BIT9_MASK              2
    #define ADRH_BIT10_MASK             4
    #define ADRH_BIT11_MASK             8
    #define ADRH_BIT12_MASK             16
    #define ADRH_BIT13_MASK             32
    #define ADRH_BIT14_MASK             64
    #define ADRH_BIT15_MASK             128
    

    /*** ADRL - ADC Data Register Low; 0x00000042 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* ADC Data Bit 0 */
        byte BIT1        :1;                                       /* ADC Data Bit 1 */
        byte BIT2        :1;                                       /* ADC Data Bit 2 */
        byte BIT3        :1;                                       /* ADC Data Bit 3 */
        byte BIT4        :1;                                       /* ADC Data Bit 4 */
        byte BIT5        :1;                                       /* ADC Data Bit 5 */
        byte BIT6        :1;                                       /* ADC Data Bit 6 */
        byte BIT7        :1;                                       /* ADC Data Bit 7 */
      } Bits;
    } ADRLSTR;
    #define ADRL                        _ADR.Overlap_STR.ADRLSTR.Byte
    #define ADRL_BIT0                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT0
    #define ADRL_BIT1                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT1
    #define ADRL_BIT2                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT2
    #define ADRL_BIT3                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT3
    #define ADRL_BIT4                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT4
    #define ADRL_BIT5                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT5
    #define ADRL_BIT6                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT6
    #define ADRL_BIT7                   _ADR.Overlap_STR.ADRLSTR.Bits.BIT7
    
    #define ADRL_BIT0_MASK              1
    #define ADRL_BIT1_MASK              2
    #define ADRL_BIT2_MASK              4
    #define ADRL_BIT3_MASK              8
    #define ADRL_BIT4_MASK              16
    #define ADRL_BIT5_MASK              32
    #define ADRL_BIT6_MASK              64
    #define ADRL_BIT7_MASK              128
    
  } Overlap_STR;

} ADRSTR;
extern volatile ADRSTR _ADR;
#define ADR                             _ADR.Word


/*** ADCLK - ADC Clock Register; 0x00000043 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte MODE0       :1;                                       /* Mode of Result Justification Bit 0 */
    byte MODE1       :1;                                       /* Mode of Result Justification Bit 1 */
    byte ADICLK      :1;                                       /* ADC Input Clock Select Bit */
    byte ADIV0       :1;                                       /* ADC Clock Prescaler Bit 0 */
    byte ADIV1       :1;                                       /* ADC Clock Prescaler Bit 1 */
    byte ADIV2       :1;                                       /* ADC Clock Prescaler Bit 2 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpMODE :2;
    byte         :1;
    byte grpADIV :3;
  } MergedBits;
} ADCLKSTR;
extern volatile ADCLKSTR _ADCLK;
#define ADCLK                           _ADCLK.Byte
#define ADCLK_MODE0                     _ADCLK.Bits.MODE0
#define ADCLK_MODE1                     _ADCLK.Bits.MODE1
#define ADCLK_ADICLK                    _ADCLK.Bits.ADICLK
#define ADCLK_ADIV0                     _ADCLK.Bits.ADIV0
#define ADCLK_ADIV1                     _ADCLK.Bits.ADIV1
#define ADCLK_ADIV2                     _ADCLK.Bits.ADIV2
#define ADCLK_MODE                      _ADCLK.MergedBits.grpMODE
#define ADCLK_ADIV                      _ADCLK.MergedBits.grpADIV

#define ADCLK_MODE0_MASK                4
#define ADCLK_MODE1_MASK                8
#define ADCLK_ADICLK_MASK               16
#define ADCLK_ADIV0_MASK                32
#define ADCLK_ADIV1_MASK                64
#define ADCLK_ADIV2_MASK                128
#define ADCLK_MODE_MASK                 12
#define ADCLK_MODE_BITNUM               2
#define ADCLK_ADIV_MASK                 224
#define ADCLK_ADIV_BITNUM               5


/*** TBSC - TIMB Status/Control Register; 0x00000051 ***/
typedef union {
  byte Byte;
  struct {
    byte PS0         :1;                                       /* Prescaler Select Bit 0 */
    byte PS1         :1;                                       /* Prescaler Select Bit 1 */
    byte PS2         :1;                                       /* Prescaler Select Bit 2 */
    byte             :1; 
    byte TRST        :1;                                       /* TIMB Reset Bit */
    byte TSTOP       :1;                                       /* TIMB Stop Bit */
    byte TOIE        :1;                                       /* TIMB Overflow Interrupt Enable Bit */
    byte TOF         :1;                                       /* TIMB Overflow Flag Bit */
  } Bits;
  struct {
    byte grpPS   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TBSCSTR;
extern volatile TBSCSTR _TBSC;
#define TBSC                            _TBSC.Byte
#define TBSC_PS0                        _TBSC.Bits.PS0
#define TBSC_PS1                        _TBSC.Bits.PS1
#define TBSC_PS2                        _TBSC.Bits.PS2
#define TBSC_TRST                       _TBSC.Bits.TRST
#define TBSC_TSTOP                      _TBSC.Bits.TSTOP
#define TBSC_TOIE                       _TBSC.Bits.TOIE
#define TBSC_TOF                        _TBSC.Bits.TOF
#define TBSC_PS                         _TBSC.MergedBits.grpPS

#define TBSC_PS0_MASK                   1
#define TBSC_PS1_MASK                   2
#define TBSC_PS2_MASK                   4
#define TBSC_TRST_MASK                  16
#define TBSC_TSTOP_MASK                 32
#define TBSC_TOIE_MASK                  64
#define TBSC_TOF_MASK                   128
#define TBSC_PS_MASK                    7
#define TBSC_PS_BITNUM                  0


/*** TBCNT - TIMB Counter Register; 0x00000052 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TBCNTH - TIMB Counter Register High; 0x00000052 ***/
    union {
      byte Byte;
    } TBCNTHSTR;
    #define TBCNTH                      _TBCNT.Overlap_STR.TBCNTHSTR.Byte
    

    /*** TBCNTL - TIMB Counter Register Low; 0x00000053 ***/
    union {
      byte Byte;
    } TBCNTLSTR;
    #define TBCNTL                      _TBCNT.Overlap_STR.TBCNTLSTR.Byte
    
  } Overlap_STR;

} TBCNTSTR;
extern volatile TBCNTSTR _TBCNT;
#define TBCNT                           _TBCNT.Word


/*** TBMOD - TIMB Counter Modulo Register; 0x00000054 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TBMODH - TIMB Counter Modulo Register High; 0x00000054 ***/
    union {
      byte Byte;
    } TBMODHSTR;
    #define TBMODH                      _TBMOD.Overlap_STR.TBMODHSTR.Byte
    

    /*** TBMODL - TIMB Counter Modulo Register Low; 0x00000055 ***/
    union {
      byte Byte;
    } TBMODLSTR;
    #define TBMODL                      _TBMOD.Overlap_STR.TBMODLSTR.Byte
    
  } Overlap_STR;

} TBMODSTR;
extern volatile TBMODSTR _TBMOD;
#define TBMOD                           _TBMOD.Word


/*** TBSC0 - TIMB Channel 0 Status/Control Register; 0x00000056 ***/
typedef union {
  byte Byte;
  struct {
    byte CH0MAX      :1;                                       /* Channel 0 Maximum Duty Cycle Bit */
    byte TOV0        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS0A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS0B       :1;                                       /* Edge/Level Select Bit B */
    byte MS0A        :1;                                       /* Mode Select Bit A */
    byte MS0B        :1;                                       /* Mode Select Bit B */
    byte CH0IE       :1;                                       /* Channel 0 Interrupt Enable Bit */
    byte CH0F        :1;                                       /* Channel 0 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV  :1;
    byte grpELS0x :2;
    byte grpMS0x :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} TBSC0STR;
extern volatile TBSC0STR _TBSC0;
#define TBSC0                           _TBSC0.Byte
#define TBSC0_CH0MAX                    _TBSC0.Bits.CH0MAX
#define TBSC0_TOV0                      _TBSC0.Bits.TOV0
#define TBSC0_ELS0A                     _TBSC0.Bits.ELS0A
#define TBSC0_ELS0B                     _TBSC0.Bits.ELS0B
#define TBSC0_MS0A                      _TBSC0.Bits.MS0A
#define TBSC0_MS0B                      _TBSC0.Bits.MS0B
#define TBSC0_CH0IE                     _TBSC0.Bits.CH0IE
#define TBSC0_CH0F                      _TBSC0.Bits.CH0F
#define TBSC0_ELS0x                     _TBSC0.MergedBits.grpELS0x
#define TBSC0_MS0x                      _TBSC0.MergedBits.grpMS0x

#define TBSC0_CH0MAX_MASK               1
#define TBSC0_TOV0_MASK                 2
#define TBSC0_ELS0A_MASK                4
#define TBSC0_ELS0B_MASK                8
#define TBSC0_MS0A_MASK                 16
#define TBSC0_MS0B_MASK                 32
#define TBSC0_CH0IE_MASK                64
#define TBSC0_CH0F_MASK                 128
#define TBSC0_ELS0x_MASK                12
#define TBSC0_ELS0x_BITNUM              2
#define TBSC0_MS0x_MASK                 48
#define TBSC0_MS0x_BITNUM               4


/*** TBCH0 - TIMB Channel 0 Register; 0x00000057 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TBCH0H - TIMB Channel 0 Register High; 0x00000057 ***/
    union {
      byte Byte;
    } TBCH0HSTR;
    #define TBCH0H                      _TBCH0.Overlap_STR.TBCH0HSTR.Byte
    

    /*** TBCH0L - TIMB Channel 0 Register Low; 0x00000058 ***/
    union {
      byte Byte;
    } TBCH0LSTR;
    #define TBCH0L                      _TBCH0.Overlap_STR.TBCH0LSTR.Byte
    
  } Overlap_STR;

} TBCH0STR;
extern volatile TBCH0STR _TBCH0;
#define TBCH0                           _TBCH0.Word


/*** TBSC1 - IMB Channel Status and Control Register; 0x00000059 ***/
typedef union {
  byte Byte;
  struct {
    byte CH1MAX      :1;                                       /* Channel 1 Maximum Duty Cycle Bit */
    byte TOV1        :1;                                       /* Toggle-On-Overflow Bit */
    byte ELS1A       :1;                                       /* Edge/Level Select Bit A */
    byte ELS1B       :1;                                       /* Edge/Level Select Bit B */
    byte MS1A        :1;                                       /* Mode Select Bit A */
    byte             :1; 
    byte CH1IE       :1;                                       /* Channel 1 Interrupt Enable Bit */
    byte CH1F        :1;                                       /* Channel 1 Flag Bit */
  } Bits;
  struct {
    byte         :1;
    byte grpTOV_1 :1;
    byte grpELS1x :2;
    byte grpMS1x :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TBSC1STR;
extern volatile TBSC1STR _TBSC1;
#define TBSC1                           _TBSC1.Byte
#define TBSC1_CH1MAX                    _TBSC1.Bits.CH1MAX
#define TBSC1_TOV1                      _TBSC1.Bits.TOV1
#define TBSC1_ELS1A                     _TBSC1.Bits.ELS1A
#define TBSC1_ELS1B                     _TBSC1.Bits.ELS1B
#define TBSC1_MS1A                      _TBSC1.Bits.MS1A
#define TBSC1_CH1IE                     _TBSC1.Bits.CH1IE
#define TBSC1_CH1F                      _TBSC1.Bits.CH1F
#define TBSC1_ELS1x                     _TBSC1.MergedBits.grpELS1x

#define TBSC1_CH1MAX_MASK               1
#define TBSC1_TOV1_MASK                 2
#define TBSC1_ELS1A_MASK                4
#define TBSC1_ELS1B_MASK                8
#define TBSC1_MS1A_MASK                 16
#define TBSC1_CH1IE_MASK                64
#define TBSC1_CH1F_MASK                 128
#define TBSC1_ELS1x_MASK                12
#define TBSC1_ELS1x_BITNUM              2


/*** TBCH1 - TIMB Channel 1 Register; 0x0000005A ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TBCH1H - TIMB Channel 1 Register High; 0x0000005A ***/
    union {
      byte Byte;
    } TBCH1HSTR;
    #define TBCH1H                      _TBCH1.Overlap_STR.TBCH1HSTR.Byte
    

    /*** TBCH1L - TIMB Channel 1 Register Low; 0x0000005B ***/
    union {
      byte Byte;
    } TBCH1LSTR;
    #define TBCH1L                      _TBCH1.Overlap_STR.TBCH1LSTR.Byte
    
  } Overlap_STR;

} TBCH1STR;
extern volatile TBCH1STR _TBCH1;
#define TBCH1                           _TBCH1.Word


/*** PCTL - PLL Control Register; 0x0000005C ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BCS         :1;                                       /* Base Clock Select Bit */
    byte PLLON       :1;                                       /* PLL On Bit */
    byte PLLF        :1;                                       /* PLL Interrupt Flag */
    byte PLLIE       :1;                                       /* PLL Interrupt Enable Bit */
  } Bits;
} PCTLSTR;
extern volatile PCTLSTR _PCTL;
#define PCTL                            _PCTL.Byte
#define PCTL_BCS                        _PCTL.Bits.BCS
#define PCTL_PLLON                      _PCTL.Bits.PLLON
#define PCTL_PLLF                       _PCTL.Bits.PLLF
#define PCTL_PLLIE                      _PCTL.Bits.PLLIE

#define PCTL_BCS_MASK                   16
#define PCTL_PLLON_MASK                 32
#define PCTL_PLLF_MASK                  64
#define PCTL_PLLIE_MASK                 128


/*** PBWC - PLL Bandwith Control Register; 0x0000005D ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte XLD         :1;                                       /* Crystal Loss Detect Bit */
    byte ACQ         :1;                                       /* Acquisition Mode Bit */
    byte LOCK        :1;                                       /* Lock Indicator Bit */
    byte AUTO        :1;                                       /* Automatic Bandwith Control Bit */
  } Bits;
} PBWCSTR;
extern volatile PBWCSTR _PBWC;
#define PBWC                            _PBWC.Byte
#define PBWC_XLD                        _PBWC.Bits.XLD
#define PBWC_ACQ                        _PBWC.Bits.ACQ
#define PBWC_LOCK                       _PBWC.Bits.LOCK
#define PBWC_AUTO                       _PBWC.Bits.AUTO

#define PBWC_XLD_MASK                   16
#define PBWC_ACQ_MASK                   32
#define PBWC_LOCK_MASK                  64
#define PBWC_AUTO_MASK                  128


/*** PPG - PLL Programming Register; 0x0000005E ***/
typedef union {
  byte Byte;
  struct {
    byte VRS4        :1;                                       /* VCO Range Select Bit 4 */
    byte VRS5        :1;                                       /* VCO Range Select Bit 5 */
    byte VRS6        :1;                                       /* VCO Range Select Bit 6 */
    byte VRS7        :1;                                       /* VCO Range Select Bit 7 */
    byte MUL4        :1;                                       /* Multiplier Select Bit 4 */
    byte MUL5        :1;                                       /* Multiplier Select Bit 5 */
    byte MUL6        :1;                                       /* Multiplier Select Bit 6 */
    byte MUL7        :1;                                       /* Multiplier Select Bit 7 */
  } Bits;
  struct {
    byte grpVRS_4 :4;
    byte grpMUL_4 :4;
  } MergedBits;
} PPGSTR;
extern volatile PPGSTR _PPG;
#define PPG                             _PPG.Byte
#define PPG_VRS4                        _PPG.Bits.VRS4
#define PPG_VRS5                        _PPG.Bits.VRS5
#define PPG_VRS6                        _PPG.Bits.VRS6
#define PPG_VRS7                        _PPG.Bits.VRS7
#define PPG_MUL4                        _PPG.Bits.MUL4
#define PPG_MUL5                        _PPG.Bits.MUL5
#define PPG_MUL6                        _PPG.Bits.MUL6
#define PPG_MUL7                        _PPG.Bits.MUL7
#define PPG_VRS_4                       _PPG.MergedBits.grpVRS_4
#define PPG_MUL_4                       _PPG.MergedBits.grpMUL_4
#define PPG_VRS                         PPG_VRS_4
#define PPG_MUL                         PPG_MUL_4

#define PPG_VRS4_MASK                   1
#define PPG_VRS5_MASK                   2
#define PPG_VRS6_MASK                   4
#define PPG_VRS7_MASK                   8
#define PPG_MUL4_MASK                   16
#define PPG_MUL5_MASK                   32
#define PPG_MUL6_MASK                   64
#define PPG_MUL7_MASK                   128
#define PPG_VRS_4_MASK                  15
#define PPG_VRS_4_BITNUM                0
#define PPG_MUL_4_MASK                  240
#define PPG_MUL_4_BITNUM                4


/*** SBSR - SIM Break Status Register; 0x0000FE00 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte BW          :1;                                       /* Break Wait Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SBSRSTR;
extern volatile SBSRSTR _SBSR;
#define SBSR                            _SBSR.Byte
#define SBSR_BW                         _SBSR.Bits.BW

#define SBSR_BW_MASK                    2


/*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte LVI         :1;                                       /* Low-Voltage Inhibit Reset bit */
    byte             :1; 
    byte ILAD        :1;                                       /* Illegal Address Reset Bit */
    byte ILOP        :1;                                       /* Illegal Opcode Reset Bit */
    byte COP         :1;                                       /* Computer Operating Properly Reset Bit */
    byte PIN         :1;                                       /* External Reset Bit */
    byte POR         :1;                                       /* Power-On Reset Bit */
  } Bits;
} SRSRSTR;
extern volatile SRSRSTR _SRSR;
#define SRSR                            _SRSR.Byte
#define SRSR_LVI                        _SRSR.Bits.LVI
#define SRSR_ILAD                       _SRSR.Bits.ILAD
#define SRSR_ILOP                       _SRSR.Bits.ILOP
#define SRSR_COP                        _SRSR.Bits.COP
#define SRSR_PIN                        _SRSR.Bits.PIN
#define SRSR_POR                        _SRSR.Bits.POR

#define SRSR_LVI_MASK                   2
#define SRSR_ILAD_MASK                  8
#define SRSR_ILOP_MASK                  16
#define SRSR_COP_MASK                   32
#define SRSR_PIN_MASK                   64
#define SRSR_POR_MASK                   128


/*** SBFCR - SIM Break Flag Control Register; 0x0000FE03 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BCFE        :1;                                       /* Break Clear Flag Enable Bit */
  } Bits;
} SBFCRSTR;
extern volatile SBFCRSTR _SBFCR;
#define SBFCR                           _SBFCR.Byte
#define SBFCR_BCFE                      _SBFCR.Bits.BCFE

#define SBFCR_BCFE_MASK                 128


/*** FLCR - FLASH Control Register; 0x0000FE08 ***/
typedef union {
  byte Byte;
  struct {
    byte PGM         :1;                                       /* Program Control Bit */
    byte ERASE       :1;                                       /* Erase Control Bit */
    byte MASS        :1;                                       /* Mass Erase Control Bit */
    byte HVEN        :1;                                       /* High-Voltage Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} FLCRSTR;
extern volatile FLCRSTR _FLCR;
#define FLCR                            _FLCR.Byte
#define FLCR_PGM                        _FLCR.Bits.PGM
#define FLCR_ERASE                      _FLCR.Bits.ERASE
#define FLCR_MASS                       _FLCR.Bits.MASS
#define FLCR_HVEN                       _FLCR.Bits.HVEN

#define FLCR_PGM_MASK                   1
#define FLCR_ERASE_MASK                 2
#define FLCR_MASS_MASK                  4
#define FLCR_HVEN_MASK                  8


/*** BRK - Break Address Register; 0x0000FE0C ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** BRKH - Break Address Register High; 0x0000FE0C ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Break Address Bit 8 */
        byte BIT9        :1;                                       /* Break Address Bit 9 */
        byte BIT10       :1;                                       /* Break Address Bit 10 */
        byte BIT11       :1;                                       /* Break Address Bit 11 */
        byte BIT12       :1;                                       /* Break Address Bit 12 */
        byte BIT13       :1;                                       /* Break Address Bit 13 */
        byte BIT14       :1;                                       /* Break Address Bit 14 */
        byte BIT15       :1;                                       /* Break Address Bit 15 */
      } Bits;
    } BRKHSTR;
    #define BRKH                        _BRK.Overlap_STR.BRKHSTR.Byte
    #define BRKH_BIT8                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT8
    #define BRKH_BIT9                   _BRK.Overlap_STR.BRKHSTR.Bits.BIT9
    #define BRKH_BIT10                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT10
    #define BRKH_BIT11                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT11
    #define BRKH_BIT12                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT12
    #define BRKH_BIT13                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT13
    #define BRKH_BIT14                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT14
    #define BRKH_BIT15                  _BRK.Overlap_STR.BRKHSTR.Bits.BIT15
    
    #define BRKH_BIT8_MASK              1
    #define BRKH_BIT9_MASK              2
    #define BRKH_BIT10_MASK             4
    #define BRKH_BIT11_MASK             8
    #define BRKH_BIT12_MASK             16
    #define BRKH_BIT13_MASK             32
    #define BRKH_BIT14_MASK             64
    #define BRKH_BIT15_MASK             128
    

    /*** BRKL - Break Address Register Low; 0x0000FE0D ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Break Address Bit 0 */
        byte BIT1        :1;                                       /* Break Address Bit 1 */
        byte BIT2        :1;                                       /* Break Address Bit 2 */
        byte BIT3        :1;                                       /* Break Address Bit 3 */
        byte BIT4        :1;                                       /* Break Address Bit 4 */
        byte BIT5        :1;                                       /* Break Address Bit 5 */
        byte BIT6        :1;                                       /* Break Address Bit 6 */
        byte BIT7        :1;                                       /* Break Address Bit 7 */
      } Bits;
    } BRKLSTR;
    #define BRKL                        _BRK.Overlap_STR.BRKLSTR.Byte
    #define BRKL_BIT0                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT0
    #define BRKL_BIT1                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT1
    #define BRKL_BIT2                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT2
    #define BRKL_BIT3                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT3
    #define BRKL_BIT4                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT4
    #define BRKL_BIT5                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT5
    #define BRKL_BIT6                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT6
    #define BRKL_BIT7                   _BRK.Overlap_STR.BRKLSTR.Bits.BIT7
    
    #define BRKL_BIT0_MASK              1
    #define BRKL_BIT1_MASK              2
    #define BRKL_BIT2_MASK              4
    #define BRKL_BIT3_MASK              8
    #define BRKL_BIT4_MASK              16
    #define BRKL_BIT5_MASK              32
    #define BRKL_BIT6_MASK              64
    #define BRKL_BIT7_MASK              128
    
  } Overlap_STR;

} BRKSTR;
extern volatile BRKSTR _BRK;
#define BRK                             _BRK.Word


/*** BRKSCR - Break Status and Control Register; 0x0000FE0E ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BRKA        :1;                                       /* Break Active Bit */
    byte BRKE        :1;                                       /* Break Enable Bit */
  } Bits;
} BRKSCRSTR;
extern volatile BRKSCRSTR _BRKSCR;
#define BRKSCR                          _BRKSCR.Byte
#define BRKSCR_BRKA                     _BRKSCR.Bits.BRKA
#define BRKSCR_BRKE                     _BRKSCR.Bits.BRKE

#define BRKSCR_BRKA_MASK                64
#define BRKSCR_BRKE_MASK                128


/*** LVISCR - LVI Status and Control Register; 0x0000FE0F ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte TRPSEL      :1;                                       /* LVI Trip Select Bit */
    byte             :1; 
    byte LVIOUT      :1;                                       /* LVI Output Bit */
  } Bits;
} LVISCRSTR;
extern volatile LVISCRSTR _LVISCR;
#define LVISCR                          _LVISCR.Byte
#define LVISCR_TRPSEL                   _LVISCR.Bits.TRPSEL
#define LVISCR_LVIOUT                   _LVISCR.Bits.LVIOUT

#define LVISCR_TRPSEL_MASK              32
#define LVISCR_LVIOUT_MASK              128


/*** FLBPR - FLASH Block Protect Register; 0x0000FF7E ***/
typedef union {
  byte Byte;
  struct {
    byte BPR0        :1;                                       /* Flash Block Protect Bit 0 */
    byte BPR1        :1;                                       /* Flash Block Protect Bit 1 */
    byte BPR2        :1;                                       /* Flash Block Protect Bit 2 */
    byte BPR3        :1;                                       /* Flash Block Protect Bit 3 */
    byte BPR4        :1;                                       /* Flash Block Protect Bit 4 */
    byte BPR5        :1;                                       /* Flash Block Protect Bit 5 */
    byte BPR6        :1;                                       /* Flash Block Protect Bit 6 */
    byte BPR7        :1;                                       /* Flash Block Protect Bit 7 */
  } Bits;
} FLBPRSTR;
/* Tip for register initialization in the user code:  const byte FLBPR_INIT @0x0000FF7E = <FLBPR_INITVAL>; */
#define _FLBPR (*(const FLBPRSTR * __far)0x0000FF7E)
#define FLBPR                           _FLBPR.Byte
#define FLBPR_BPR0                      _FLBPR.Bits.BPR0
#define FLBPR_BPR1                      _FLBPR.Bits.BPR1
#define FLBPR_BPR2                      _FLBPR.Bits.BPR2
#define FLBPR_BPR3                      _FLBPR.Bits.BPR3
#define FLBPR_BPR4                      _FLBPR.Bits.BPR4
#define FLBPR_BPR5                      _FLBPR.Bits.BPR5
#define FLBPR_BPR6                      _FLBPR.Bits.BPR6
#define FLBPR_BPR7                      _FLBPR.Bits.BPR7

#define FLBPR_BPR0_MASK                 1
#define FLBPR_BPR1_MASK                 2
#define FLBPR_BPR2_MASK                 4
#define FLBPR_BPR3_MASK                 8
#define FLBPR_BPR4_MASK                 16
#define FLBPR_BPR5_MASK                 32
#define FLBPR_BPR6_MASK                 64
#define FLBPR_BPR7_MASK                 128


/*** COPCTL - COP Control Register; 0x0000FFFF ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Bit 0 */
    byte BIT1        :1;                                       /* Bit 1 */
    byte BIT2        :1;                                       /* Bit 2 */
    byte BIT3        :1;                                       /* Bit 3 */
    byte BIT4        :1;                                       /* Bit 4 */
    byte BIT5        :1;                                       /* Bit 5 */
    byte BIT6        :1;                                       /* Bit 6 */
    byte BIT7        :1;                                       /* Bit 7 */
  } Bits;
} COPCTLSTR;
extern volatile COPCTLSTR _COPCTL;
#define COPCTL                          _COPCTL.Byte
#define COPCTL_BIT0                     _COPCTL.Bits.BIT0
#define COPCTL_BIT1                     _COPCTL.Bits.BIT1
#define COPCTL_BIT2                     _COPCTL.Bits.BIT2
#define COPCTL_BIT3                     _COPCTL.Bits.BIT3
#define COPCTL_BIT4                     _COPCTL.Bits.BIT4
#define COPCTL_BIT5                     _COPCTL.Bits.BIT5
#define COPCTL_BIT6                     _COPCTL.Bits.BIT6
#define COPCTL_BIT7                     _COPCTL.Bits.BIT7

#define COPCTL_BIT0_MASK                1
#define COPCTL_BIT1_MASK                2
#define COPCTL_BIT2_MASK                4
#define COPCTL_BIT3_MASK                8
#define COPCTL_BIT4_MASK                16
#define COPCTL_BIT5_MASK                32
#define COPCTL_BIT6_MASK                64
#define COPCTL_BIT7_MASK                128



/***********************************************/
/**   D E P R E C I A T E D   S Y M B O L S   **/
/***********************************************/
/* ---------------------------------------------------------------------------------------------------
Exceptions in bit names of timer status and control registers
due to backward compatibility with previous releases  */
#define TASC0_CHxMAX    _TASC0.Bits.CH0MAX
#define TASC0_TOVx      _TASC0.Bits.TOV0
#define TASC0_ELSxA     _TASC0.Bits.ELS0A
#define TASC0_ELSxB     _TASC0.Bits.ELS0B
#define TASC0_MSxA      _TASC0.Bits.MS0A
#define TASC0_MSxB      _TASC0.Bits.MS0B
#define TASC0_CHxIE     _TASC0.Bits.CH0IE
#define TASC0_CHxF      _TASC0.Bits.CH0F

#define TASC1_CHxMAX    _TASC1.Bits.CH1MAX
#define TASC1_TOVx      _TASC1.Bits.TOV1
#define TASC1_ELSxA     _TASC1.Bits.ELS1A
#define TASC1_ELSxB     _TASC1.Bits.ELS1B
#define TASC1_MSxA      _TASC1.Bits.MS1A
#define TASC1_CHxIE     _TASC1.Bits.CH1IE
#define TASC1_CHxF      _TASC1.Bits.CH1F

#define TBSC0_CHxMAX    _TBSC0.Bits.CH0MAX
#define TBSC0_TOVx      _TBSC0.Bits.TOV0
#define TBSC0_ELSxA     _TBSC0.Bits.ELS0A
#define TBSC0_ELSxB     _TBSC0.Bits.ELS0B
#define TBSC0_MSxA      _TBSC0.Bits.MS0A
#define TBSC0_MSxB      _TBSC0.Bits.MS0B
#define TBSC0_CHxIE     _TBSC0.Bits.CH0IE
#define TBSC0_CHxF      _TBSC0.Bits.CH0F

#define TBSC1_CHxMAX    _TBSC1.Bits.CH1MAX
#define TBSC1_TOVx      _TBSC1.Bits.TOV1
#define TBSC1_ELSxA     _TBSC1.Bits.ELS1A
#define TBSC1_ELSxB     _TBSC1.Bits.ELS1B
#define TBSC1_MSxA      _TBSC1.Bits.MS1A
#define TBSC1_CHxIE     _TBSC1.Bits.CH1IE
#define TBSC1_CHxF      _TBSC1.Bits.CH1F

/* --------------------------------------------------------------------------- */
/* The following symbols were removed, because they were invalid or irrelevant */
/* --------------------------------------------------------------------------- */


/* **** 11.9.2009 12:42:42 */

#define TACH_ARR                         This_symb_has_been_depreciated
#define TBCH_ARR                         This_symb_has_been_depreciated
#endif
